ST AN3140 APPLICATION NOTE

AN3140

Application note

How to configure the SPEAr3xx general purpose timers (GPTs)

Introduction

This application note provides information about how to configure the general purpose timers (GPTs) integrated in the SPEAr3xx embedded MPU family.

General purpose timers (GPTs) play an important role in any system as they provide a means of calculating time for controlling the execution of various operations. In case of an operating system, they are used for the system tick generation, usually every 10 ms; in other applications they can be used to get a finer granularity for controlling the timing of events.

The purpose of this application note is to explain how to read the free running timer counter and configure the clock source of the various GPTs that are integrated in the SPEAr3xx architecture. It also describes and proposes a solution for the problem reported during the Puppy Linux project concerning the status register interrupt bit clear issue.

May 2010

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Contents	AN3140

Contents

1	General purpose timers (GPTs) in SPEAr3xx . . . . . . . . . . . . . . . . . . . .		. 3
2	Reading a free-running timer counter . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
3	Scenario with slow CNT_Clk and fast READ_Clk . . . . . . . . . . . . . . . . .		7
4	How to configure CNT_Clk and READ_Clk to be synchronous . . . . . .		8
5	3-read software workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
6	Status register interrupt bit clear issue . . . . . . . . . . . . . . . . . . . . . . . .		10
	6.1	Problem description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	6.2	Proposed solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
7	Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13

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AN3140	General purpose timers (GPTs) in SPEAr3xx

1 General purpose timers (GPTs) in SPEAr3xx

In the SPEAr3xx architecture, there are three different GPT blocks located in the various subsystems. Each timer block consists of two independent channels, each one with a 16-bit counter register.

Table 1.	GPTs in SPEAr3xx
			Subsystem	Base address
	GPT1		ARM	0xF000_0000
	GPT2		Basic1	0xFC80_0000
	GPT3		Basic2	0xFCB0_0000

Each timer has a READ_Clk, input which is the APB clock (PCLK), and a CNT_Clk, which can be selected by the user from a list of clock sources.

●READ_Clk (PCLK): When SPEAr3xx is in normal mode, it takes the input from PLL1 divided by a programmable prescaler, whose reset values impose the ratio 1:2:4 to the core_clk, HCLK and PCLK clocks. When SPEAr3xx is in slow mode, it takes directly the input from the OSCI signal.

●CNT_Clk: The clock source can be selected as either a fixed 48 MHz or the PLL1 itself divided by a programmable prescaler, which is defined in the PRSC1_CLK_CFG register (0xFCA8_0044) for GPT1, PRSC2_CLK_CFG register (0xFCA8_0048) for GPT2 and PRSC3_CLK_CFG register (0xFCA8_004C) for GPT3. The CNT_Clk may then be further divided by a GPT internal 4-bit prescaler able to divide up to 256 times (‘/256’).

Figure 1. GPT clock sources

		HCLK/PCLK
	PLL1 (332MHz)/	prescaler	Read_CLK
	OSCI (24MHz)		(PCLK)
			GPT Ch1	GPT Ch2
PLL1 (332MHz)	PRSCx_CLK_CFG
		MUX
			int_prsc
			CNT_Clk
	PLL3 (48MHz)
		Clock_Sel

The following table describes the clock selectors (Clock_Sel) for each GPT.

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General purpose timers (GPTs) in SPEAr3xx						AN3140
	Table 2.	GPTx clock source selector
			Register	Address		Value
		GPT1	PRPH_CLK_CFG [08]	0xFCA8_0028	(bit8)	0: PLL3 48 MHz
						1: PLL1 (PRSC1_CLK_CFG)
		GPT2	PRPH_CLK_CFG[11]	0xFCA8_0028	(bit11)	0: PLL3 48 MHz
						1: PLL1 (PRSC2_CLK_CFG)
		GPT3	PRPH_CLK_CFG[12]	0xFCA8_0028	(bit12)	0: PLL3 48 MHz
						1: PLL1 (PRSC3_CLK_CFG)

The SPEAr3xx GPTs always generate precise alarm interrupts, for example in the case of a system tick for a RTOS. Nevertheless, as you can see in Section 2: Reading a free-running timer counter, GPTs can return unpredictable read values when they are running and the input clock is asynchronous (or not in phase).

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AN3140	Reading a free-running timer counter

2 Reading a free-running timer counter

When the GPT interrupt is enabled, the interrupts generated at each timer wrap-around condition are always triggered at the right frequency, however reading the timer counter when the timer itself is active and free-running may present some difficulties which are described below.

In a simplified scenario, a hardware timer block can be seen just as a simple counter register with two input clocks:CNT_Clk for incrementing/decrementing the counter and READ_Clk for synchronizing the READ accesses of the bus the timer is connected to.

Figure 2. Simplified timer

0	0	1	0	1	…
READ_Clk					CNT_Clk

The two clocks can be either synchronous, coming from the same source PCLK, or completely asynchronous, for example coming from two different sources.

When the two clocks involved in the scenario are asynchronous, then the value retrieved by the CPU in a read counter operation is unpredictable, and might be completely different from the real value in the register.

The situation is due to the fact that the READ_Clk is sampling the counter bits while they are in a transitioning, unstable phase.

Figure 3. Sampling a counter bit in an unstable state

Bit_N

CNT_Clk

READ_Clk

t0 t1 t2

t0: On CNT_Clk rising edge, Bit_N start a 0->1 transitioning

t1: On READ_Clk rising edge, Bit_N is sampled in an unstable state

t2: Bit_N reaches a stable state

The above scenario may take place during any kind of transition (0->1 or 1->0) and for any bit in the register.

If one of the bits impacted has a large weight (significant position) in the counter, then the difference between the value returned in the read transaction and the real value of the counter can be very large.

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