ST AN3123 APPLICATION NOTE
AN3123
Application note
Using the UART interfaces in the SPEAr embedded MPU family
Introduction
The SPEAr embedded MPU family is a family of configurable MPUs, based on the ARM926
CPU core. Each member of the SPEAr MPU family has one or more embedded ARM PL011
UARTs for asynchronous communications. This application note describes how to configure
the UART and transmit and receive data.
A Linux driver is available in the SPEAr Linux support package (LSP), refer to the SPEAR
Linux support package (LSP) user manual (UM0851) for a description of how to use this
driver.
Section 10 of this application note describes an OS independent hardware abstraction layer
(HAL) for the SPEAr UART which you can use as a starting point for developing your own
HAL code.
March 2012 Doc ID 16862 Rev 2 1/30
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Contents AN3123
Contents
1 Purpose and scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 UART signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 SPEAr600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 SPEAr300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 SPEAr310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 SPEAr320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5 SPEAr320S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Clock source and frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Clock related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Changing the UART baud rate on the fly . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Baud rate related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 UART protocol flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 UART controller data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 UART data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7 UART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2 Interrupt types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2.1 UARTRXINTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2.2 UARTTXINTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2.3 UARTRTINTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2.4 UARTMSINTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2.5 UARTEINTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2.6 UARTINTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.3 Interrupt related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.1 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/30 Doc ID 16862 Rev 2
AN3123 Contents
8.2 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9 UART modem operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10 OS-independent SPEAr UART HAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.1 SetBaseDevice() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.2 GetBaudDivisor() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.3 UART_Init() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10.4 UART_Configure() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10.5 UART_Transmit() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.6 UART_Receive() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.7 UART_Disable() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.8 UART_IsTxFIFOFull() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.9 UART_IsTxFIFOEmpty() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.10 UART_IsRxFIFOFull() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.11 UART_IsRxFIFOEmpty() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.12 UART_IntEnable() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.13 UART_IntDisable() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.14 UART_IntClear() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.15 UART_GetIntSrc() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Appendix A Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Doc ID 16862 Rev 2 3/30
Purpose and scope AN3123
1 Purpose and scope
UART is one of the most commonly used serial interface peripherals. It is also known as the
serial communications interface, or SCI. The most common use of the UART is to
communicate to a PC serial port using the RS-232 protocol.
RS-232 is a standard electrical interface for serial communications defined by the Electronic
Industries Association ("EIA").
Serial communications include most network devices, keyboards, mice, modems, and
terminals. When referring to serial devices or ports, they are either labeled as data
communications equipment ("DCE") or data terminal equipment ("DTE").
The UART can transmit and receive data serially. It is often necessary to regulate the flow of
data when transferring data between two serial interfaces. The first method is often called
"software" flow control and uses special characters to start (XON or DC1) or stop (XOFF or
DC3) the flow of data. The second method is called "hardware" flow control and uses the
RS-232 CTS and RTS signals instead of special characters. Because hardware flow control
uses a separate set of signals, it is much faster than software flow control which needs to
send or receive multiple bits of information to do the same thing.
4/30 Doc ID 16862 Rev 2
AN3123 UART signals
2 UART signals
SPEAr600 has 2 UARTs. SPEAr300, SPEAr310 and SPEAr320 have 1, 6 and 3 UARTs
respectively. The following tables list the UART pin connections and register base addresses
for each case.
2.1 SPEAr600
Table 1. External pin connection on SPEAr600
Signal name Ball Direction Function Pin type
UART1_TXD AA19 Output
UART1_RXD AB19 Input
Table 2. Memory map on SPEAr600
Peripheral Start address End address
UART1 0xD000.0000 0xD007.FFFF
UART2 0xD008.0000 0xD00F.FFFF
2.2 SPEAr300
Table 3. External pin connection
Signal Ball Direction Function Pin type
RX DATA D1 Input
TX DATA E4 Output
RTS B8
CTS A8
DTR D9
DSR B9
I/O
Serial Data Out
Serial Data In
Shared I/O
TTL output buffer
3.3 V capable, 4 mAUART2_TXD AA20 Output
TTL input buffer
3.3 V tolerant, PDUART2_RXD AB20 Input
TTL output buffer
3.3 V capable,
up to 10 mA
TTL input buffer
3.3 V tolerant, PU/PD
DCD A9
RI C9
Table 4. Memory map on SPEAr300
Peripheral Start address End address
UART 0xD000.0000 0xD007.FFFF
Doc ID 16862 Rev 2 5/30
UART signals AN3123
In SPEAr300, the device offers several different PL_GPIO sharing modes. Different
blocks/IPs are available in different configuration modes.
This has an effect on the above mentioned UART signals also. Not all SPEAR300 UART
signals in Ta bl e 3 are available in all configurations.
This is because for many applications UART is used in NULL modem mode and only
UART_RX & UART_TX are sufficient.
There are 13 possible UART configurations in SPEAr300 which can be selected by RAS
control register 2.
In configuration 1 & configuration 2, the UART with modem control lines is available.
In configurations 3 to 13, the UART without modem control lines is available (see Tab le 6 ).
Table 5. UART configurations for SPEAr300
Signal Configuration 1 Configuration 2 Configurations 3 to 13
PL_GPIO[42] UART_DTR UART_DTR -
PL_GPIO[41] UART_RI UART_RI -
PL_GPIO[40] UART_DSR UART_DSR -
PL_GPIO[39] UART_DCD UART_DCD -
PL_GPIO[38] UART_CTS UART_CTS -
PL_GPIO[37] UART_RTS UART_RTS -
PL_GPIO[3] UART_RX UART_RX UART_RX
PL_GPIO[2] UART_TX UART_TX UART_TX
Note: On PL_GPIO[3] and PL_GPIO[2] UART_RX and UART_TX are multiplexed with external
memory controller (FSMC) signals /E3 and /E4 respectively.
2.3 SPEAr310
In SPEAr310 the external pin connections of UART1 are the same as in SPEAr300.
You can configure the device to have either
● up to 6 UARTs without modem control lines or
● 1 UART with modem control lines.
Refer to Ta bl e 3 .
6/30 Doc ID 16862 Rev 2
AN3123 UART signals
Table 6. UART configurations for SPEAr310
Signal Ball Alternate function RAS normal mode Pin type
PL_GPIO[44] A10 - UART5_TX
PL_GPIO[43] E9 - UART5_RX
PL_GPIO[42] D9 UART0_DTR UART5_TX
PL_GPIO[41] C9 UART0_RI UART5_RX
PL_GPIO[40] B9 UART0_DSR UART4_TX
PL_GPIO[39] A9 UART0_DCD UART4_RX
PL_GPIO[38] A8 UART0_CTS UART3_TX
PL_GPIO[37] B8 UART0_RTS UART3_RX
PL_GPIO[3] D1 UART0_RX UART0_RX
PL_GPIO[2] E4 UART0_TX UART0_TX
PL_GPIO[1] E3 UART1_TX
PL_GPIO[0] F3 UART1_RX
Table 7. Memory map on SPEAr310
Peripheral Start address End address
TTL output buffer
3.3 V capable,
up to 10 mA
TTL input buffer
3.3 V tolerant, PU/PD
UART1 0xD000.0000 0xD007.FFFF
UART2 0xB200.0000 0xB207.FFFF
UART3 0xB208.0000 0xB20F.FFFF
UART4 0xB210.0000 0xB217.FFFF
UART5 0xB218.0000 0xB21F.FFFF
UART6 0xB220.0000 0xB227.FFFF
2.4 SPEAr320
In SPEAr320 the external pin connections of UART0 are the same as the UART in
SPEAr300. Refer to Ta bl e 3 .
You can configure the device to have:
● up to 3 UARTs, 1 without modem control lines and 2 with modem control lines.
Table 8. UART configurations for SPEAr320
Signal Ball Alternate
PL_GPIO[45] B10 UART1_DCD
PL_GPIO[44] A10 - UART1_DSR
Config. 1 Config. 2 Config. 3 Config. 4
function
PL_GPIO[43] E9 - UART1_RTS
Doc ID 16862 Rev 2 7/30
UART signals AN3123
Table 8. UART configurations for SPEAr320 (continued)
Signal Ball Alternate
Config. 1 Config. 2 Config. 3 Config. 4
function
PL_GPIO[42] D9 UART0_DTR
PL_GPIO[41] C9 UART0_RI
PL_GPIO[40] B9 UART0_DSR
PL_GPIO[39] A9 UART0_DCD
PL_GPIO[38] A8 UART0_CTS
PL_GPIO[37] B8 UART0_RTS
PL_GPIO[36] C8 UART1_CTS UART1_CTS
PL_GPIO[35] D8 UART1_DTR UART1_DTR
PL_GPIO[34] E8 UART1_RI UART1_RI
PL_GPIO[33] E7 UART1_DCD
PL_GPIO[32] D7 UART1_DSR
PL_GPIO[31] C7 UART1_RTS
PL_GPIO[29] A7 UART1_TX UART1_TX UART1_TX UART1_TX UART1_TX
PL_GPIO[28] A6 UART1_RX UART1_RX UART1_RX UART1_RX UART1_RX
PL_GPIO[3] D1 UART0_RX
PL_GPIO[2] E4 UART0_TX
PL_GPIO[1] E3 UART2_TX UART2_TX UART2_TX UART2_TX
PL_GPIO[0] F3 UART2_RX UART2_RX UART2_RX UART2_RX
Table 9. Memory map on SPEAr300
Peripheral Start address End address
UART0 0xD000.0000 0xD007.FFFF
UART1 0xA300.0000 0xA3FF.FFFF
UART2 0xA400.0000 0xA4FF.FFFF
2.5 SPEAr320S
In SPEAr320S the external pin connections of UART0 are the same as the UART in
SPEAr300. Refer to Ta bl e 3 .
You can configure the device to have:
● up to 7 UARTs, 5 without modem control lines and 2 with modem control lines.
● 1 UART_RS485
8/30 Doc ID 16862 Rev 2
AN3123 UART signals
Table 10. UART configurations for SPEAr320S
Signal Ball Alternate
function
PL_GPIO[95] H14 UART3_TX
PL_GPIO[94] H13 UART3_RX
PL_GPIO[93] G17 UART4_TX
PL_GPIO[92] G16 UART4_RX
PL_GPIO[91] G15 UART5_TX
PL_GPIO[90] G14 UART5_RX
PL_GPIO[89] F17 UART6_TX
PL_GPIO[88] F16 UART6_RX
PL_GPIO[85] F15 UART1_CTS
PL_GPIO[84] D17 UART1_DTR
PL_GPIO[83] E16 UART1_RI
PL_GPIO[82] E15 UART1_DCD
PL_GPIO[81] C17 UART1_DSR
PL_GPIO[80] D16 UART1_RTS
PL_GPIO[79v F14
PL_GPIO[78] D15
Config. 1 Config.
2
Config.
3
Config.
4
Extended
UART_RS485
_TX
UART_RS485
_RX
PL_GPIO[77] B17
PL_GPIO[74] C16 UART3_TX
PL_GPIO[73] A17 UART3_RX
PL_GPIO[72] B16 UART4_TX
PL_GPIO[71] D14 UART4_RX
PL_GPIO[70] C15 UART5_TX
PL_GPIO[69] A16 UART5_RX
PL_GPIO[53v D11 UART3_TX
PL_GPIO[52] B12 UART3_RX
PL_GPIO[45] B10 UART1_DCD
PL_GPIO[44] A10 - UART1_DSR
PL_GPIO[43] E9 - UART1_RTS
PL_GPIO[42] D9 UART0_DTR UART3_TX
PL_GPIO[41] C9 UART0_RI UART3_RX
PL_GPIO[40] B9 UART0_DSR UART4_TX
PL_GPIO[39] A9 UART0_DCD UART4_RX
UART_RS485
_OE
Doc ID 16862 Rev 2 9/30
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