ST AN3115 Application note

AN3115

Application note

LNB power supply based on the LNBH23L

supply and control IC with step-up and I²C interface

Introduction

This application note is intended to provide additional information and suggestions for the correct use of the LNBH23L device. All waveforms shown are based on the demonstration board order code STEVAL-CBL007V1 described in Section 3.

The LNBH23L is an integrated solution for supplying/interfacing satellite LNB modules. It gives good performance in a simple and cheap way, with minimum external components necessary. It includes all functions needed for LNB supplying and interfacing, in accordance with international standards. Moreover, it includes an I²C bus interface and, thanks to a fully integrated step-up DC-DC converter, it functions with a single input voltage supply ranging from 8 V to 15 V.

Figure 1. LNBH23L internal block diagram

ISEL TTX

ADDR

SDA SCL

BypVcc Vcc-

P-GND

Vup

VoRX

VoTX

EXTM

DSQIN

Rsense

TTX

Preregulator

Preregulator +U.V.l ockou t

+U.V.l ockou t

Controller

PWM

VSEL

Linear Post-reg

+Protections

+Protections +Diagnostics

+Diagnostics

-reg

22KHz

22KHz Oscill.

Oscill.

VSEL

TTX

VOUT Control

TEN

A-G NDA-G ND

A-G NDA-G NDA-G NDA-G ND

I² C interface

I²C OLF and OTF

I²C OLF and OTF Diagnostics

Diagnostics

Pull Down

Controller

LNBH23L

+U.V.l ockou t +P.ON reset

+P.ON reset

PDC

January 2011 Doc ID 16830 Rev 3 1/28

www.st.com

Contents AN3115

Contents

1 Block diagram and pin function description . . . . . . . . . . . . . . . . . . . . . 5

1.1 Step-up controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 Pre-regulator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 I²C interface and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3.1 Reserved I²C address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 DiSEqC™ 1.X implementation through EXTM pin . . . . . . . . . . . . . . . . . . . 6

1.5 DiSEqC 1.X Implementation through VoTX and EXTM . . . . . . . . . . . . . . . 7

1.6 PDC optional circuit for DiSEqC 1.X applications using VoTX signal on to EXTM pin and 22 kHz tone controlled by DSQIN pin 7

1.7 22 kHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.8 DiSEqC communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.9 Linear post-regulator, modulator and protection . . . . . . . . . . . . . . . . . . . . 8

1.10 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Component selection guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 DC-DC converter inductor (L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2 Output current limit selection (R2-RSEL) . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 DC-DC converter schottky diode (D1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4 TVS diode (D6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.5 DC-DC output capacitors (C3, C4, C6) and ferrite bead . . . . . . . . . . . . . 17

2.6 Input capacitors (C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.7 PDC optional external circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.8 EXTM-VOTX resistor (R9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.9 Undervoltage protection diode (D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2 PCB Thermal managing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4 Startup procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/28 Doc ID 16830 Rev 3

AN3115 List of tables

List of tables

Table 1. LNBH23L I²C addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. LNBH23L other I²C addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. LNBH23L pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 5. LNBH23L demo-board BOM list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 6. Recommended Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. Recommended Schottky diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 8. Recommended LNBTVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Doc ID 16830 Rev 3 3/28

List of figures AN3115

List of figures

Figure 1. LNBH23L internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. EXTM example of use with 22 kHz IC controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. DiSEqC 1.X tone burst with 22 kHz IC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. DiSEqC timing control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. LNBH23L pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6. LNBH23L typical application circuit with internal tone generator . . . . . . . . . . . . . . . . . . . . 11

Figure 7. Typical output current limiting vs. R

Figure 8. Example of LNBTVS diode connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9. DC-DC converter output stage with ferrite bead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10. Application circuit with PDC optional solution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11. PDC optional circuit load calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 12. PDC circuit waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 13. Tone amplitude vs. R9 value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 14. PBC top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 15. PBC bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 16. PCB components layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 17. Typical junction to ambient thermal resistance with dual layer PCB, 1oz, 9 thermal vias . 24

Figure 18. PCB connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SEL

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AN3115 Block diagram and pin function description

1 Block diagram and pin function description

The internal blocks of the LNBH23L are described in the following paragraphs:

1.1 Step-up controller

The LNBH23L features a built-in step-up DC-DC converter that, from a single supply source ranging from 8 V to 15 V, generates the voltages that allow the linear post-regulator to work with minimum power dissipation. The external components of the DC-DC converter are connected to the L

1.2 Pre-regulator block

This block includes a voltage reference connected to the BYP pin, an undervoltage lockout circuit, intended to disable the whole circuit when the supplied V threshold (6.7 V typ), and a power-on reset that sets all the I²C registers to zero when the V

is turned on and rises from zero above the “on” threshold (7.3 V typ).

and VUP pins (see Figure 6). No external power MOSFET is needed.

drops below a fixed

1.3 I²C interface and diagnostic

The main functions of the device are controlled via the I²C bus by writing 5 bits on the system register (SR bits in write mode). In the same register there are 5 bits that can be read back (SR bits in read mode) and provide 2 diagnostic functions, whereas the other 3 bits are for internal usage (TEST1, TEST2, and TEST3). Two bits report the diagnostic status of the two internal monitoring functions:

– OTF: over temperature flag. If an overheating occurs (junction temperature

exceeds 150 °C), the OTF I²C bit is set to “1”.

– OLF: overload flag. If the output current required exceeds the current limit

threshold or a short circuit occurs, the OLF I²C bit is set to “1”.

Moreover, three bits report the last output voltage register status (EN, VSEL, LLC) received by the I²C. The LNBH23L I²C interface address can be selected from two different addresses by setting the voltage level of the dedicated ADDR pin according to Tab le 1 :

Table 1. LNBH23L I²C addresses

Pin Set-up Write (HEX) Read (HEX)

ADDR=Low or floating 0x14 0x15

ADDR=High 0x16 0x17

1.3.1 Reserved I²C address

The device has another I²C address reserved only for internal usage, see Ta bl e 2 .

Table 2. LNBH23L other I²C addresses

Pin Set-up Write (HEX) Read (HEX)

ADDR=Low/High or floating 0x10 0x11

Doc ID 16830 Rev 3 5/28

Block diagram and pin function description AN3115

1.4 DiSEqC™ 1.X implementation through EXTM pin

The EXTM pin is an analog input to generate the 22 kHz tone superimposed to the V output voltage. If the EXTM pin is used, the internal 22 kHz generator must be kept OFF (TTX pin or TTX bit set LOW). A cheaper circuit must be used to couple the modulating signal source to the EXTM pin (see Figure 2).

The EXTM pin modulates the V

(AC) = V

oRX

Where:

- V

(AC) and V

oRX

EXTM pin

- G

is the voltage gain from EXTM to V

EXTM

In order to avoid the 22 kHz tone distortion, a dummy output load may be necessary, strictly dependent on the output bus capacitance.

Table 3. Output load

Output bus capacitance Output load

< 50 nF 10 mA

250 nF (EUTELSAT spec.) 30 mA

750 nF (DIRECT TV spec.) 80 mA

EXTM

voltage through the series decoupling capacitor, so that:

oRX

(AC) x G

EXTM

(AC) are, respectively, the peak to peak voltage on the V

oRX

and

For the correct DiSEqC implementation, during tone transmission, it is most important that the DiSEqC_out pin of the 22 kHz IC controller, is set in low impedance and vice versa, during no-tone transmission, it must be set in high impedance.

Figure 2 shows an example circuit as an appropriate solution with a 22 kHz IC controller to

drive the EXTM pin for the DiSEqC implementation.

Figure 2. EXTM example of use with 22 kHz IC controller

VDD 3V3

22 KHz IC

22 KHz IC controller

controller

DISEQC_OUT

Vtone signal

4K7

15 K

1µF

LNBH23L

EXTM pin

EXTM

VoRX

VoRx OUTPUT

6/28 Doc ID 16830 Rev 3

AN3115 Block diagram and pin function description

Figure 3. DiSEqC 1.X tone burst with 22 kHz IC controller

High-Z

VoRx OUTPUT

Vtone signal

High-Z STATE

STATE

Push -pull

Action

High-Z

STATE

Push -pull

1.5 DiSEqC 1.X Implementation through V

If an external 22 kHz tone source is not available, it is possible to use the internal 22 kHz tone generator signal available through the V V

22 kHz signal is superimposed to the V

oTX

kHz tone (see Figure 6). The internal 22 kHz tone generator, available through the V must be activated during the 22 kHz transmission by the DSQIN pin or by the TEN bit. The DSQIN internal circuit activates the 22 kHz tone on the V delay from the TTL signal present on the DSQIN pin, and it stops with 1 cycle ± 25 µs delay after the TTL signal is expired. The V

pin internal circuit must be preventively set ON by

oTX

the TTX function. This can be controlled both through the TTX pin and the I²C bit. As soon as the tone transmission is expired, the V The 13 / 18 V power supply is always provided to the LNB from the V

pin to drive the EXTM pin. In this way the

oTX

DC voltage to generate the LNB output 22

oRX

must be disabled by setting the TTX to LOW.

oTX

High-Z

High-Z STATE

STATE

Action

and EXTM

oTX

output with 0.5 cycles ± 25 µs

oTX

pin.

oRX

oTX

pin,

1.6 PDC optional circuit for DiSEqC 1.X applications using V signal on to EXTM pin and 22 kHz tone controlled by DSQIN pin

In some applications, at light output current (< 50 mA) having a heavy LNB output capacitive load, the 22 kHz tone can be distorted. In this case it is possible to add the “Optional” external components described on Section 2.7.

1.7 22 kHz oscillator

The internal 22 kHz tone generator is factory-trimmed in accordance with current standards and can be selected by the I²C interface TTX bit (or TTX pin) and controlled by the DSQIN pin (TTL compatible), which allows immediate DiSEqC data encoding. If the 22 kHz tone presence is requested in continuous mode, the internal oscillator can be activated by the I²C

Doc ID 16830 Rev 3 7/28

oTX

Block diagram and pin function description AN3115

interface TEN bit. The rise and fall edges are controlled to be in the 5 µs to 15 µs range, 8 µs typ for 22 kHz. The Duty cycle is 50 % typ., it modulates the DC output with a 0.650 V

(typ.) amplitude as well as the DSQIN pin.

1.8 DiSEqC communication

The following steps must be taken to ensure the correct implementation of the DiSEqC communication:

Figure 4. DiSEqC timing control

LNBout

DSQIN

> 500µs

> 200 µs

TTX

● T0: Before starting the DiSEqC transmission. The TTX function must be activated

DiSEqC Transmit Mode

DiSEqC Receive Mode

(through the TTX pin or TTX I²C bit);

● T1: After 500 µs minimum, the IC is ready to receive the DiSEqC code through the

DSQIN pin (or, alternatively, the TEN I²C bit can be set to HIGH to activate the 22 kHz burst);

● T2: When the transmission is elapsed, the TTX function is set to LOW (through the TTX

pin or TTX I²C bit) not earlier than 200 µsec after the last falling edge of the DiSEqC code.

1.9 Linear post-regulator, modulator and protection

The output voltage selection and the current selection commands join this block, which manages the LNB output function. This block gives feedback to the I²C interface from the diagnostic block, regarding the status of the thermal protection, over current protection, and output settings.

1.10 Pin description

The LNBH23L is available in an exposed pad QFN-32 package for surface mount assembly.

Figure 5 shows the device pin-out and Ta bl e 4 briefly summarizes the pin function.

8/28 Doc ID 16830 Rev 3

AN3115 Block diagram and pin function description

Figure 5. LNBH23L pin configuration

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