ST AN3100 APPLICATION NOTE

AN3100

Application note

Configuring the SPEAr3xx multi-port memory controller (MPMC) for

external DDR SDRAM

Introduction

The SPEAr3xx embedded MPU family features a multi-port memory controller for interfacing with external DDR or DDR2 memory devices.

This application note describes how to configure the MPMC to use different types of DDR and DDR2 memories and tune the parameters in accordance with JEDEC requirements and the flexibility available in the application.

March 2012 Doc ID 16606 Rev 2 1/24

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Contents AN3100

Contents

1 SPEAr3xx memory controller overview . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 DDR overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 DDR2 vs. DDR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1.1 Package differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.2 Power supply differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.3 Other feature differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 DDR mobile overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 DDR programming in SPEAr3xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Configuring SPEAr MPMC for a specific DDR memory part . . . . . . . . 11

5 DDR controller delay lines tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1 Reading from DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.2 Writing to DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.2.1 Example using these parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7 Pad descriptions and configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.1 DDR_PAD register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Appendix A Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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AN3100 SPEAr3xx memory controller overview

SRAM

74.5 KB

Cell array

(reconfigurable

array

subsystem)

300 000 gates

ARM926EJS

32 KI/32 KD

coprocessor

cache

TCM-I/D

CPU ARM subsystem

Int ctrl

GPIO

Timer

MPMC

DDR1-2

CFG

1 2

3 56

7-34

1234 3-12 7

5-23

Multilayer bus interconnection matrix

UART

SPI

I2C

JPEG

(Codec)

RAM

(8 KB)

IrDA

Low-speed subsystem

System Ctrl

Flash serial

GPIO

RTC

Timer

DMA

(8 chan.)

ROM

32 KB

WDT

Ethernet

MAC

USB2.0 Device

USB2.0

Host

USB2.0

Host

Application subsystem

Basic subsystem

HS subsystem

ABCD

Common subsystems

SRAM

74.5 KB

RI-O

Configurable cell array subsystem

SPEAr300

ADC

Misc

9-4

10-6

6-67

2-12(4) 4-12

1 SPEAr3xx memory controller overview

In the SPEAr3xx embedded MPU, different memory controllers provide interfaces between the system elements/blocks and external memory.

The MPMC multi-port memory controller is used for interfacing DDR (double data rate) synchronous dynamic RAM (SDRAM). It is also responsible for reliable read-write operations to the memory. In a powerful system like SPEAr3xx, there are several system elements which may need to communicate with external DDR memory at any time to increase system efficiency. This is possible because the memory provides data at very high speed and system elements need time to process that data, so this time can be utilized by other system elements to transfer data to/from the memory. For example, during the time that the CPU processes some data or instructions, another master interface (CPU or DMA) can read or write to the memory. This can be handled by the MPMC’s multi-port capablity.

For maximum flexibility the MPMC has one AHB slave port to configure the memory controller registers and five AHB slave ports for data. Figure 1: SPEAr3xx architecture gives an overview of the SPEAr3xx, showing the connections between the SDRAM controller AHB data ports (M0,..,M4) and the various subsystems of the design.

Figure 1. SPEAr3xx architecture

In order to understand how the various IPs interact with the external memory through the multi-port memory controller, the table below shows the driving masters present in SPEAr3xx and the corresponding memory controller AHB slave data port.

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SPEAr3xx memory controller overview AN3100

Table 1. Memory controller AHB data ports

Memory controller AHB data port Driving masters

M0 CPU

M1 RAS_L

M2 DMA master 1, RAS_H

M3 DMA master 2, Ethernet GMAC, C3, RAS_E

M4 USB subsystem, C3

Note: RAS_L, RAS_H and RAS_E are specific ports that can be used in customized SPEAr MPUs

to connect masters to the external DDR.

This memory controller supports DDR mobile and DDR2 devices, compliant with JEDEC standards, up to a clock frequency of 333 MHz (data rate 667 MT/sec). As the memory controller supports DDR mobile and DDR2 at different frequencies for almost all DDR part manufacturers, MPMC must be programmed with the right timing parameters required for the selected DDR memory part, DDR frequency, CAS latency etc.

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AN3100 DDR overview

2 DDR overview

2.1 DDR2 vs. DDR1

DDR1 and DDR2 memory modules are widely used in desktop PCs. Their full name is DDR (double data rate) SDRAM (synchronous DRAM), which is a variant of dynamic RAM. Dynamic RAM differs from static RAM because the former, constituted by both transistors and capacitors, requires constant refreshing to restore the values in the capacitors while the latter, constituted only by transistors, does not require refreshing, resulting in much higher performance. However, SRAMs are much more expensive than DRAMs.

Going back to SDRAM, this type of memory utilizes a synchronous interface: this means that it waits for a clock pulse to transfer data, and thus it is synchronized with the system bus and the processor. SDRAM transfers one bit (per data line) of data per clock cycle.

DDR SDRAM technology doubles the bandwidth of SDRAM under optimal conditions. In fact, SDRAM transfers data on every clock cycle (to be specific, on the rising edge of every clock cycle), while DDR transfers data on both the rising and the falling edge of a clock cycle. Therefore, two bits (per data line) are transferred on every clock cycle. In order to do this, two bits are accessed from the memory array (where data is actually stored) for each data line on every clock cycle, this process is called the “2-bit prefetch”. In this way, the interface’s clock speed remains constant, but the data bus effectively doubles in frequency.

The figure below shows a simple DDR1 SDRAM architecture example.

Figure 2. DDR1 SDRAM architecture

In general, a DRAM (non synchronous) address is presented in two parts: a row and a column address. The row and the column are multiplexed on the same set of address pins (DDR_MEM_ADDR [14:0] with reference to SPEAr3xx pins) to reduce package, size and cost. First, the row address is loaded, or strobed, into the row address latch via the row address strobe, or RAS, followed by the column address with the column address strobe, or CAS. The Read data propagate to the output after a specified access time. Write data are presented at the same time as the column address, because it is the column strobe that actually triggers the transaction, whether read or write. The SDRAM internal state logic operates on discrete commands that are presented to it. The signals RAS and CAS (DDR_MEM_RAS and DDR_MEM_CAS, SPEAr3xx pins) are still present, but they function as part of other control signals to form commands rather than simple strobes.

Most of the input signals to the state logic shown in Figure 2 combine to form the discrete commands listed in Table 2.

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DDR overview AN3100

Table 2. Basic SDRAM command set

Command CS RAS CAS WE Address AP/A10

Bank activate L L H H Bank, row A10

Read L H L H Bank, column L

Read with autoprecharge

Write L H L L Bank, column L

Write with autoprecharge

No operation L H H H X X

Burst terminate L H H L X X

Bank precharge L L H L X L

Precharge all banks L L H L X H

Mode register set L L L L Configuration Configuration

Auto refresh L L L H X X

Device deselect H X X X X X

LHLH Bank, column H

L H L L Bank, column H

A clock enable, CLKE (DDR_MEM_CLKEN, SPEAr3xx pin), must be high for normal operations. Interface control signals are sampled on the rising clock edge. As SDRAM devices are manufactured in multibyte data bus width, Data (DDR_MEM_DQ, SPEAr3xx pins) is a 16-bit wide bus in SPEAr3xx, the data mask DM (DDR_MEM_DM [1:0], SPEAr3xx pins) provides a convenient way to selectively mask individual bytes from being written or being driven during reads.

Some common functions include activating a row for future access, performing a read, and precharging a row (deactivating a row, often in preparation for activating a new row).

The first requirement, for example, to read an SDRAM is to activate the desired row, on the desired bank (DDR_MEM_BA [2:0], SPEAr3xx pins). To do this, you must use an activate command by asserting RAS for one cycle while presenting the desired bank and row address.

The next command issued to continue the transaction is a read. However the controller must wait a number of cycles that corresponds to the DRAM array’s row-activate to column-strobe delay time. To use the read command, you must assert CAS and present the desired bank select and column address, along with the auto precharge (AP) flag. A particular bank must be selected because the multibank SDRAM architecture enables reads from any bank. In the case of reads and writes, the assertion of AP (address line 10) tells the SDRAM to automatically precharge the activated row after the requested transaction completes. Precharging a row returns it to quiescent state and also clears the way for another row in the same bank to be activated next time. A single bank cannot have more than one row active at any given time. Once the controller issues the read command, it must wait a predetermined number of cycles before the data is returned by the SDRAM. This delay is known as CAS latency. The data interface contains the data strobe signal (DDR_MEM_DQS [1:0], SPEAr3xx pins). It is a bidirectional clock that is used to synchronize the reads and writes on the data bus.

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AN3100 DDR overview

Being a 2

generation DDR, the most important improvement found in DDR2 memory is its transfer data rate or bandwidth. As in the case of DDR SDRAM vs. SDRAM, the bandwidth of DDR2 memory can double the bandwidth of DDR. DDR already operates on both the rising and the falling edge of the clock, so DDR2 can achieve twice the bandwidth by doubling the I/O buffer frequency. DDR2 utilizes a “4-bit prefetch” architecture: this means that 4 bits of data are moved from the memory array to the I/O buffer per data line for each core clock cycle. The core clock cycle refers to the cycle time of the memory array, and the frequency of the memory array is half of the I/O buffers and ¼ of the data rates.

The table below compares the main features of DDR1 and DDR2. Section 2.1.1 and

Section 2.1.2 give more details on the package and power supply differences.

Table 3. DDR1 and DDR2 at a glance

DDR1 DDR2

Features

Frequency specifications

Data rate 200/266/333/400 Mbps 400/533/667 Mbps

Bus frequency 100/133/166/200 MHz 200/266/333 MHz

DRAM core frequency 100/133/166/200 MHz 100/133/166 MHz

Prefetch size 2 bit 4 bit

Burst length 2/4/8 4/8

Data strobe Single DQS Differential Strobe: DQS, /DQS

CAS latency 1.5, 2, 2.5 3, 4, 5

Write latency 1T Read latency-1

Power Specs

Core voltage (VDD) 2.5 V 1.8 V

I/O voltage (VDDQ) SSSTL_2(2.5 V) SSSTL_1.8(1.8 V)

Format

Packaging TSOP(II), TBGA FBGA

Compatibility with DDR1

Command Set Same as DDR1

Parameters Same as DDR1

Bus Utilization and Signal Integrity

ODT

New features

OCD calibration

Posted CAS

Additive latency

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DDR overview AN3100

2.1.1 Package differences

DDR2 memories have smaller size packages with less electrical noise, thus resulting in improved integrity at higher operating frequencies.

2.1.2 Power supply differences

DDR2 operates at 1.8 V. This is a 28% reduction compared to DDR1, which combined with power saving features such as smaller page sizes and an active power down mode results in power consumption advantages.

2.1.3 Other feature differences

DDR2 has also some other new features like on die termination (ODT). Around the memory slots on a DDR1-supporting motherboard, there can be termination resistors, which are used to eliminate excessive signal noise. For DDR2 modules, the termination resistors are built into the chip, which are far closer to the source of the noise. This ODT feature can reduce interference within the chip, thus guaranteeing the stability and reliability of DDR2 memory when working under high frequencies.

There are other features such as Posted CAS and Additive latency, which work together to prevent data collisions and utilize the data bus more efficiently, as well as the off-chip driver calibration (OCD), which increases signal integrity and system timing margin as well.

2.2 Addressing

Once configured, you do not need to to worry about the DDR protocol; you can access the DDR by directly accessing the memory address. In SPEAr3xx, DDR is mapped from 0x0000_0000 to 0x3FFF_FFFF: that means that an addressable space of 1 GB is dedicated to the external DRAM. In this way you can address, using all the 30 address bits, up to 2 x 4 Gb memory chips. Only 256 Mb x 16 cuts are possible because of the presence of only 14 address lines, DDR_MEM_ADDR [14:0]. In this case, the use of the bits is divided in the following way:

● 10 bits for column address

● 3 bits for bank address

● 15 bits for row address

In the user address, bit 0 is used to select the width of the datapath. It is fixed to ‘0’ if the datapath is 16 bit and if the datapath is 8 bit, it is fixed to ‘1’.

So in this case:

● User_address [0] = datapath;

● User_address [10:1] = column address;

● User_address [13:11] = bank address;

● User_address [28:14] = row address;

● User_address [29] = chip select;

Regardless of the memory cut selected, the CPU always sees a contiguous addressable space. For this reason, the memory controller always shifts the memory address parts (row, bank and column) in the user address according to the physical memory cut attached and its configuration.

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