ST AN3099 APPLICATION NOTE

AN3099

Application note

IBIS models for signal integrity

simulation of SPEAr3xx applications

Introduction

This application note is intended for hardware developers that are using the SPEAr3xx
embedded MPU in their target design.

IBIS models are mandatory to run signal integrity simulation in the application PCB. PCB
simulation is very important to make sure that the layout of the PCB does not introduce any
functional problems or timing marginality in high speed interfaces like DDR2.

The IBIS models provided for SPEAr3xx are organized in a model library containing several
models for each I/O pin (or for a functional group of I/Os). Each I/O pin or functional group of
I/O has a set of models; each model corresponds to a certain operating mode of the I/O
pads.

The operating modes are programmable and are defined by a proper setting of two registers
of the SPEAr3xx device (for more details please refer to the miscellaneous registers and
DDR memory controller sections of the SPEAr3xx user manual).

This document explains how to extract the correct model from the library sp300_v3.ibs after
reading the register setting or knowing the operating mode.

December 2009 Doc ID 16605 Rev 1 1/13

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PL_CLK & PL_GPIO IBIS model selection AN3099

1 PL_CLK & PL_GPIO IBIS model selection

The I/O signals of the PL_CLK & PL_GPIO interface form two main groups.

Please refer to the following table for the I/O signals and the associated model name.

Table 1. Relation between the PL_.... block signals and the used model

PL_.... block signal

name

PL_CLK[4:1]

PL_GPIO[97:95]
PL_GPIO[92:85]
PL_GPIO[82:73]
PL_GPIO[70:69]
PL_GPIO[67:58]
PL_GPIO[56:53]
PL_GPIO[50:43]
PL_GPIO[40:33]
PL_GPIO[30:25]
PL_GPIO[22:19]
PL_GPIO[16:11]
PL_GPIO[8:5]
PL_GPIO[2:1]

PL_GPIO[94:93]
PL_GPIO[84:83]
PL_GPIO[72:71]
PL_GPIO[68]
PL_GPIO[57]
PL_GPIO[52:51]
PL_GPIO[42:41]
PL_GPIO[32:31]
PL_GPIO[24:23]
PL_GPIO[18:17]
PL_GPIO[10:9]
PL_GPIO[4:3]
PL_GPIO[0]

IBIS model group name

BDPROG_2ROWS_xxxxx
xxxxx = MODEOP0 MODEOP1 DRV0 DRV1 SL

BDPROG_2ROWS_xxxxx

xxxxx = MODEOP0 MODEOP1 DRV0 DRV1 SL

BDPROG_STD_xxxxx

xxxxx = MODEOP0 MODEOP1 DRV0 DRV1 SL

Each model group name contains a set of models depending upon the value of the 5 bits
xxxx for the selected PL_GPIO [….] or PL_CLK [….] signals.

2/13 Doc ID 16605 Rev 1

AN3099 PL_CLK & PL_GPIO IBIS model selection

You must search in the user manual for the following register names:

1. PL_GPIO0_PAD_PRG (Address 0x130)

2. PL_GPIO1_PAD_PRG (Address 0x134)

3. PL_GPIO2_PAD_PRG (Address 0x138)

4. PL_GPIO3_PAD_PRG (Address 0x13C)

5. PL_GPIO4_PAD_PRG (Address 0x140)

For all the models the first two bits are the high voltage level:

MODEOP0 = 1

MODEOP1 = 1

The correlation between bits 0-2 of the model group names and the bits of each register is
given below:

● Register PL_GPIO0_PAD_PRG (Address 0xFCA80130).

PL_GPIO [23:20]:

DRV1 = PL_GPIO0_PAD_PRG [27]

DRV0 = PL_GPIO0_PAD_PRG [26]

SL = PL_GPIO0_PAD_PRG [25]

PL_GPIO [19:16]:

DRV1 = PL_GPIO0_PAD_PRG [22]

DRV0 = PL_GPIO0_PAD_PRG [21]

SL = PL_GPIO0_PAD_PRG [20]

PL_GPIO [15:12]:

DRV1 = PL_GPIO0_PAD_PRG [17]

DRV0 = PL_GPIO0_PAD_PRG [16]

SL = PL_GPIO0_PAD_PRG [15]

PL_GPIO [11:8]:

DRV1 = PL_GPIO0_PAD_PRG [12]

DRV0 = PL_GPIO0_PAD_PRG [11]

SL = PL_GPIO0_PAD_PRG [10]

PL_GPIO [7:4]:

DRV1 = PL_GPIO0_PAD_PRG [7]

DRV0 = PL_GPIO0_PAD_PRG [6]

SL = PL_GPIO0_PAD_PRG [5]

PL_GPIO [3:0]:

DRV1 = PL_GPIO0_PAD_PRG [2]

DRV0 = PL_GPIO0_PAD_PRG [1]

SL = PL_GPIO0_PAD_PRG [0]

● Register PL_GPIO1_PAD_PRG (Address 0xFCA80134).

PL_GPIO [47:44]:

DRV1 = PL_GPIO1_PAD_PRG [27]

DRV0 = PL_GPIO1_PAD_PRG [26]

SL = PL_GPIO1_PAD_PRG [25]

Doc ID 16605 Rev 1 3/13

PL_CLK & PL_GPIO IBIS model selection AN3099

PL_GPIO [43:40]:

DRV1 = PL_GPIO1_PAD_PRG [22]

DRV0 = PL_GPIO1_PAD_PRG [21]

SL = PL_GPIO1_PAD_PRG [20]

PL_GPIO [39:36]:

DRV1 = PL_GPIO1_PAD_PRG [17]

DRV0 = PL_GPIO1_PAD_PRG [16]

SL = PL_GPIO1_PAD_PRG [15]

PL_GPIO [35:32]:

DRV1 = PL_GPIO1_PAD_PRG [12]

DRV0 = PL_GPIO1_PAD_PRG [11]

SL = PL_GPIO1_PAD_PRG [10]

PL_GPIO [31:28]:

DRV1 = PL_GPIO1_PAD_PRG [7]

DRV0 = PL_GPIO1_PAD_PRG [6]

SL = PL_GPIO1_PAD_PRG [5]

PL_GPIO [27:24]:

DRV1 = PL_GPIO1_PAD_PRG [2]

DRV0 = PL_GPIO1_PAD_PRG [1]

SL = PL_GPIO1_PAD_PRG [0]

● Register PL_GPIO2_PAD_PRG (Address 0xFCA80138).

PL_GPIO [71:68]:

DRV1 = PL_GPIO2_PAD_PRG[27]

DRV0 = PL_GPIO2_PAD_PRG[26]

SL = PL_GPIO2_PAD_PRG[25]

PL_GPIO [67:64]:

DRV1 = PL_GPIO2_PAD_PRG[22]

DRV0 = PL_GPIO2_PAD_PRG[21]

SL = PL_GPIO2_PAD_PRG[20]

PL_GPIO [63:60]:

DRV1 = PL_GPIO2_PAD_PRG[17]

DRV0 = PL_GPIO2_PAD_PRG[16]

SL = PL_GPIO2_PAD_PRG[15]

PL_GPIO [59:56]:

DRV1 = PL_GPIO2_PAD_PRG[12]

DRV0 = PL_GPIO2_PAD_PRG[11]

SL = PL_GPIO2_PAD_PRG[10]

PL_GPIO [55:52]:

DRV1 = PL_GPIO2_PAD_PRG[7]

DRV0 = PL_GPIO2_PAD_PRG[6]

SL = PL_GPIO2_PAD_PRG[5]

PL_GPIO [51:48]:

4/13 Doc ID 16605 Rev 1