ST AN3029 Application note

AN3029

Application note

Getting started with STM8L

Introduction

This application note complements the information in the STM8L datasheets by describing the minimum hardware and software environment required to build an application around an STM8L 8-bit microcontroller device.

It applies to low density STM8L101x, medium and medium+ density STM8L15x, and high density STM8L15x/16x devices.

A brief description of the principal hardware components is given. The power supply, analog-to-digital converter (ADC), clock management, and reset control are described in some detail. In addition, some hardware recommendations are given. This application note also contains detailed reference design schematics with descriptions of the main components. The STM8L uses the same toolchain The STM8 development tools and software toolchain are common to STM8L, STM8S and STM8A and are presented in

Section 8, and 9. Section 10 describes how to set up the STM8 development environment.

Finally, Section 11 provides a list of relevant documentation and online support resources.

March 2011 Doc ID 16139 Rev 3 1/42

www.st.com

Contents AN3029

Contents

1 Hardware requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Main operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Power-on/power-down reset (POR/PDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Analog power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2 Analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 Clock management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 Internal clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3.2 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 Reset management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.1 Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1.2 Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2 Hardware reset implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3 Ground and power supply (V

6.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

, VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.7 User options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.8 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2/42 Doc ID 16139 Rev 3

AN3029 Contents

7 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.1 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.1 Single wire interface module (SWIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.1.1 SWIM overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.1.2 SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.1.3 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.2 STice emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.2.1 STice overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.2.2 STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.2.3 In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.3 RLink and STLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9 STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.1 Integrated development environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9.2 Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9.3 Firmware library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10 Setting up the STM8 development environment . . . . . . . . . . . . . . . . . 29

10.1 Installing the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10.2 Using the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.2.1 Project editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10.2.2 Online help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.3 Running the demonstration software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.3.1 Compiling the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.3.2 Selecting the correct debug instrument . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.3.3 Connecting the hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

10.3.4 Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10.3.5 Running the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10.3.6 Follow up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

11 Documentation and online support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Doc ID 16139 Rev 3 3/42

List of tables AN3029

List of tables

Table 1. Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 2. SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 3. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4/42 Doc ID 16139 Rev 3

AN3029 List of figures

List of figures

Figure 1. Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Typical layout of V

Figure 3. Analog input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. HSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7. Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10. Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11. Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12. Debug system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13. Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14. Connection description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 15. STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 16. In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 17. STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 18. STVD open example workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 19. STVD MCU edit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 20. STM8 firmware library online help manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 21. STVD: Building the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 22. STVD: Selecting the debug instrument. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 23. Connecting the debug instrument to the STM8L101-EVAL evaluation board . . . . . . . . . . 35

Figure 24. Connecting the debug instrument to the STM8L152x-EVAL evaluation board . . . . . . . . . 36

Figure 25. STVD: Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 26. STVD: Run the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 27. STM8 evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

DD/VSS

pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Doc ID 16139 Rev 3 5/42

Hardware requirements summary AN3029

1 Hardware requirements summary

To build an application around an STM8L device, the application board should provide the following features:

● Power supply (mandatory)

● Clock management (optional)

● Reset management (optional)

● Debugging tool support: Single wire interface module (SWIM) connector (optional)

2 Power supply

2.1 Power supply overview

The STM8L can be supplied through a 1.65 V to 3.6 V external source. For medium density STM8L15x and high density STM8L15x/STM8L16x with BOR, the power supply must be above 1.8 V at power-on and can go below 1.65 V at power-down.

An on-chip power management system provides the constant digital supply to the core logic, both in normal and low power modes. This garantees that the logic consumes a constant current over the voltage range. It is also capable of detecting voltage drops and generate reset to avoid heratic behaviour.

The STM8L device provides:

● Depending on packages, one pair of pads (V

DDx/VSSx

All V connected to V for each V

) from 1.65 V or 1.8 V to 3.6 V.

DDx

and V

DDx

must be at the same potential respectively. The V

SSx

with external decoupling capacitors: one 100 nF Ceramic capacitor

pin and one single 1 µF Tantalum or Ceramic capacitor.

DD/VSS

), or several pairs of pads

pins must be

DDx

The STM8L15x and STM8L16x devices also provide in some packages:

● One pair of pads, V

DDA/VSSA

the same potential respectively as V

converter (ADC) for more details. The V

, dedicated to analog functions. V

and VSS. Refer to Section 3: Analog-to-digital

pin must be connected to two external

DDA

and V

must be at

SSA

decoupling capacitors (one 100 nF Ceramic capacitor and one single 1 µF Tantalum or Ceramic capacitor). Additional precautions can be taken to filter analog noise: V can be connected to V

through a ferrite bead.

DDA

The STM8L152/STM8L162 device manages the supply voltage needed by the LCD in three different ways (see Figure 1):

1. If the LCD feature is not used, connect the VLCD pin to V

2. Apply to VLCD the voltage to be applied to the LCD.

3. Leave the STM8L152/STM8L162 to provide the correct voltage, via its programmable LCD booster, by connecting the VLCD pin to a 1µF capacitor.

6/42 Doc ID 16139 Rev 3

AN3029 Power supply

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Figure 1. Power supply

1. Optional: if a separate, external reference voltage is connected on V

µF) must be connected. V

2. N is the number of V

is either connected to V

REF+

and VSS inputs.

DDA

or V

REF.

, the two capacitors (100 nF and 1

REF+

Note: The capacitors must be connected as close as possible to the device supplies.

Placing a crystal/resonator on OSCIN/OSCOUT is optional. The resonator must be connected as close as possible to the OSCIN and OSCOUT pins. The loading capacitance ground must be connected as close as possible to V

2.2 Main operating voltages

STM8L devices are processed in 0.13 µm technology. The STM8L core and I/O peripherals need different power supplies. In fact, STM8L devices have an internal regulator with a nominal target output of 1.8 V.

Doc ID 16139 Rev 3 7/42

Power supply AN3029

Via to V

Cap.

VDDV

STM8

2.3 Power-on/power-down reset (POR/PDR)

The input supply to the main and low power regulators is monitored by a power-on/powerdown reset circuit. The monitoring voltage begins at 0.7 V.

During power-on, the POR/PDR keeps the device under reset until the supply voltages (V and V

) reach their specified working area. This internal reset is maintained during ~1ms

DDA

in order to wait for supply stabilization.

At power-on, a defined reset should be maintained below 0.7 V. The upper threshold for a reset release is defined in the electrical characteristics section of the product datasheets.

A hysteresis is implemented (POR > PDR) to ensure clean detection of voltage rise and fall.

The POR/PDR also generates a reset when the supply voltage drops below the V

POR/PDR

threshold (isolated and repetitive events).

For better power monitoring, the STM8L15x and STM8L16x provide a programmable power voltage detection (PVD) and a brown out reset (BOR) for an earlier detection of voltage drop.

Recommendations

All pins need to be properly connected to the power supplies. These connections, including pads, tracks and vias should have the lowest possible impedance. This is typically achieved with thick track widths and preferably dedicated power supply planes in multi-layer printed circuit boards (PCBs).

In addition, each power supply pair should be decoupled with filtering ceramic capacitors (C) at 100 nF with one chemical C (1..2 µF) in parallel on the STM8L device. The ceramic capacitors should be placed as close as possible to the appropriate pins, or below the appropriate pins, on the opposite side of the PCB. Typical values are 10 nF to 100 nF, but exact values depend on the application needs. Figure 2 shows the typical layout of such a V

DD/VSS

pair.

Figure 2. Typical layout of V

8/42 Doc ID 16139 Rev 3

DD/VSS

pair

AN3029 Analog-to-digital converter (ADC)

STM8L15x/STM8L16x

3 Analog-to-digital converter (ADC)

This section is unique for the STM8L15x and STM8L16x.

3.1 Analog power

For some packages, the ADC unit has an independent, analog supply voltage, isolated on input pin V voltage, V noise, a ferrite bead can be added between V choosen according to the frequencies to be filtered.

Some packages also provide a separate external analog reference voltage input for the ADC unit on the V

● The V

external reference voltage is applied on V connected on this pin. To compensate for peak consumption on V capacitor may be increased to 10 µF when the sampling speed is low. In all cases, V

REF+

equal to V internal V

● V

REF-

internally bonded to V

, which allows the ADC to accept a very clean voltage source. This analog

DDA

, should be identical to the digital voltage supply on pin VDD. To filter some

DDA

pin. This gives better accuracy on low voltage input as follows:

REF+

pin can be connected to the V

REF+

must be kept between 2.4 V and V

. This input is internally bonded to V

DDA

pin.

REF+

and V

external power supply. If a separate,

DDA

, a 100 nF and a 1 µF capacitor must be

REF+

. If V

DDA

. This ferrite bead should be

DDA

, the 1 µF

REF

is below 2.4, V

DDA

in the devices that have no

DDA

REF+

must be

(input, analog reference negative): The lower/negative reference voltage is

SSA

3.2 Analog input

STM8L15x and STM8L16x devices have up to 28 analog input channels (including four fast channels), each multiplexed with an I/O, which are converted by the ADC one at a time.

The external input impedance (R at maximum speed (1 MHz) if R

Please refer to Figure 3.

Figure 3. Analog input interface

) max value is 50 kΩ.The four fast channels can convert

AIN

is less than 0.5 kΩ.

AIN

Doc ID 16139 Rev 3 9/42

Analog-to-digital converter (ADC) AN3029

Please refer to the STM8L15x and STM8L16x datasheets and reference manuals for more details.

10/42 Doc ID 16139 Rev 3

AN3029 Clock management

4 Clock management

The STM8L101 has no external clock so no precautionary measures are needed.

4.1 Clock management overview

STM8L15x and STM8L16x devices offer a flexible way of selecting the core and peripheral clocks (ADC, memory, and digital peripherals). The devices have internal and external clock source inputs, both of which have a high speed and a low speed version. Any of those four clocks can be use for the CPU and most of the peripherals through a programable prescaler. An I/O can be programmed as output clock (CCO) to reflect one of the four clocks (with or without prescaling).

The signal which leaves the I/O represents an output clock (CCO) divided by a division factor.

4.2 Internal clocks

STM8L devices have two kinds of internal clock: A high speed internal clock (HSI) running at 16 MHz and a low speed internal clock (LSI) running at 38 kHz.

After reset, the CPU starts with the internal RC (HSI clock signal) divided by 8, i.e. 2 MHz.

4.3 External clock

STM8L15x and STM8L16x devices have two kinds of external clock: A high speed external clock (HSE) running at up to 16 MHz and a low speed external clock (LSE) running at

32.768 kHz.

4.3.1 HSE clock

STM8L15x and STM8L16x devices can connect to an external crystal or an external oscillator.

Note: When no external clock is used, OSCIN and OSCOUT can be used as general purpose

I/Os.

Figure 4 describes the external clock connections.

External clock

● Frequency: 0 kHz … 16 MHz

● Input hysteresis: 100 mV

Caution: Without prescaler, a duty cycle of 45/55 % maximum must be respected at high speed

Doc ID 16139 Rev 3 11/42

Clock management AN3029

OSC

OUT

External source

STM8

(I/O available)

Load capacitors

STM8

OSC

OUT

EXT

(1)

Crystal/ceramic resonator

● Frequency range: 1 to 16 MHz

● Stabilisation time: Programable from 1 to 4096 cycles

● Oscillation mode: Preferred fundamental

● Output duty cycle: Max 55/45%

● I/O’s: Standard I/O pins multiplexed with OSC

●

Cload: 10 to 20 pF

● Drive level maximum: at least 100 µW

Figure 4. HSE clock sources

Hardware configuration

External clock

and OSC

OUT

(1)

Crystal/ceramic resonators

1. The value of R

but, it is not optimal. A typical value is in the range 5 to 6 RS (resonator series resistance). To fine-tune the R

value, refer to AN2867 (Oscillator design guide for ST microcontrollers).

EXT

The values of the load capacitors C

depends on the crystal characteristics. A 0  resistor works well with most oscillators

EXT

and CL2 are heavily dependent on the crystal type and

frequency. Refer to the datasheet of the crystal manufacturer to select the capacitances. For best oscillation stability, C

and CL2 normally have the same value. Typical values are in the

range from below 20 pF up to 40 pF (cload: 10 to 20 pF). The parasitic capacitance of the board layout also needs to be considered and typically adds a few pF to the component values (refer to AN2867).

A clock security system prevents any CPU fatal error from a HSE failure, as it safely switches to HSI.

12/42 Doc ID 16139 Rev 3

AN3029 Clock management

OSC32_OUTOSC32_IN

External source

(Hi-Z)

ai15765

Microcontroller

Recommendations

In the PCB layout all connections should be as short as possible. Any additional signals, especially those that could interfere with the oscillator, should be locally separated from the PCB area around the oscillation circuit using suitable shielding.

4.3.2 LSE clock

The low-speed external clock signal (LSE) can be generated from two possible clock sources:

● LSE external crystal/ceramic resonator (see Figure 6)

● LSE user external clock (see Figure 6)

External source (LSE bypass)

In this mode, an external clock source must be provided. It must have a frequency of

32.768 kHz. The external clock signal (square, sine or triangle) with a duty cycle of about

50% has to drive the OSC32_IN pin while the OSC32_OUT pin must be left high impedance (see Figure 6 and Figure 6).

Figure 5. External clock

1. OSC32_IN and OSC32_OUT pins can be used also as GPIO but, it is recommended not to use them as

both RTC and GPIO pins in the same application.

External crystal/ceramic resonator (LSE crystal)

The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator. It has the advantage of providing a low-power, but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.

The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The load capacitance values must be adjusted according to the selected oscillator.

Doc ID 16139 Rev 3 13/42

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