ST AN3027 APPLICATION NOTE

AN3027

Application note

How to design a transition-mode PFC pre-regulator with the L6563S and L6563H

Introduction

The transition-mode (TM) technique is widely used for power factor correction in low and middle power applications such as lamp ballasts, high-end adapters, flatscreen TVs and monitors, PC power supplies and all SMPS having to meet regulations in harmonics reduction. The L6563S and L6563H are the latest devices from STMicroelectronics for these applications that may require a low-cost power factor correction.

The L6563S is a current-mode PFC controller operating in transition mode (TM). Packaged in the same SO14 pinout as its predecessor L6563, it offers improved performance and additional functions. The L6563H is the SO16 pinout version, embedding the same features as the L6563S with the addition of a high-voltage startup power source.

These functions make the L6563H especially suitable for applications that need to be compliant with energy-saving regulations and where the PFC pre-regulator works as the master stage without an auxiliary SMPS.

Figure 1. Typical system block diagram

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February 2011

Doc ID 16134 Rev 4

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www.st.com

Contents	AN3027

Contents

1	Introduction to power factor correction . . . . . . . . . . . . . . . . . . . . . . . .		. 4
2	TM PFC operation (boost topology) . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
3	Designing a TM PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
	3.1	Input specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	3.2	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	3.3	Power section design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10

3.3.1 Bridge rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.4 Boost inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.5 Power MOSFET selection and dissipation . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.6 Boost diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4 L6563S biasing circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4	L6563H: high-voltage startup transition-mode PFC . . . . . . . . . . . . . .	31
5	Design example using the L6563S-TM PFC Excel spreadsheet . . . . . 34
6	EVL6563S-100W and EVL6563H-100W demonstration boards . . . . . .	37
7	References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40

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AN3027	List of figures

List of figures

Figure 1. Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Boost converter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. Inductor current waveform and MOSFET timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Switching frequency, fixing the line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5. θ1 and θ2 dependence on input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6. Capacitive losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 7. Conduction losses and total losses in the STF7NM50N MOSFET for the L6563S TM

PFC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. L6563S internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9. Open loop tran. function bode plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10. Phase function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 11. Multiplier characteristics family for VFF = 1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 12. Multiplier characteristics family for VFF = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13. Mains detector and discharge resistor allow fast response to sudden line drops not

depending on the external RC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14. Brownout function in L6563S and L6563H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 15. Optimum MOSFET turn-on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16. Tracking boost block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 17. L6563H - SO16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 18. L6563S - SO14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 19. High-voltage startup generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 20. Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 32 Figure 21. High-voltage startup behavior during latch-off protection . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 22. High-voltage startup, managing the DC-DC output short-circuit. . . . . . . . . . . . . . . . . . . . . 33 Figure 23. Excel spreadsheet design specification input table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 24. Other design data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 25. TM PFC using the L6563S Excel spreadsheet schematic . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 26. TM PFC using the L6563H Excel spreadsheet schematic . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 27. Excel spreadsheet BOM - 100 W TM PFC based on L6563S/H . . . . . . . . . . . . . . . . . . . . 36 Figure 28. Wide-range 100 W demonstration board electrical circuit (EVL6564-100W) . . . . . . . . . . . 37 Figure 29. Wide-range 100 W demonstration board electrical circuit (EVL6563H-100W) . . . . . . . . . . 38

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Introduction to power factor correction	AN3027

1 Introduction to power factor correction

The front-end stage of conventional offline converters, typically consisting of a full-wave rectifier bridge with a capacitor filter, has an unregulated DC bus from the AC mains. The filter capacitor must be large enough to have a relatively low ripple superimposed on the DC level. This means that the instantaneous line voltage is below the voltage on the capacitor most of the time, thus the rectifiers conduct only for a small portion of each line half-cycle.

The current drawn from the mains is a series of narrow pulses whose amplitude is 5-10 times higher than the resulting DC value. Many drawbacks result, such as a much higher peak and RMS current down from the line, distortion of the AC line voltage, overcurrents in the neutral line of the three-phase systems and, consequently, a poor utilization of the power system's energy capability. This can be measured in terms of either total harmonic distortion (THD), as norms provide for, or power factor (PF), intended as the ratio between the real power (the one transferred to the output) and the apparent power (RMS line voltage multiplied by the RMS line current) drawn from the mains, which is more immediate. A traditional input stage with capacitive filter has a low PF (0.5-0.7) and a high THD (>100%).

By using switching techniques, a power factor corrector (PFC) preregulator, located between the rectifier bridge and the filter capacitor, allows drawing a quasi-sinusoidal current from the mains, in phase with the line voltage. The PF becomes very close to 1 (more than 0.99 is possible) and the previously mentioned drawbacks are eliminated. Theoretically, any switching topology can be used to achieve a high PF but, in practice, the boost topology has become the most popular thanks to the advantages it offers:

●Primarily because the circuit requires the fewest external parts (low-cost solution)

●The boost inductor located between the bridge and the switch causes the input di/dt to be low, thus minimizing the noise generated at the input and, therefore, the requirements on the input EMI filter

●The switch is source-grounded, therefore easy to drive

However, boost topology requires the DC output voltage to be higher than the maximum expected line peak voltage (400 VDC is a typical value for 230 V or wide-range mains applications). In addition, there is no insulation between the input and output, thus any line voltage surge is passed on to the output. Two methods of controlling a PFC pre-regulator are currently widely used: the fixed-frequency, average current mode PWM (FF PWM) and the transition mode (TM) PWM (fixed on-time, variable frequency). The first method needs complex control that requires a sophisticated controller IC (ST's L4981, with the variant of the frequency modulation offered by the L4981) and a considerable component count. The second one requires a simpler control (implemented by ST's L6563S), much fewer external parts and is therefore much more economical. With the first method the boost inductor works in continuous conduction mode, while TM makes the inductor work on the boundary between continuous and discontinuous mode, by definition. For a given throughput power, TM operation involves higher peak currents. This, also consistent with cost considerations, implies its use in a lower power range (typically up to 250 W), while the former is recommended for higher power levels. To conclude, FF PWM is not the only alternative when CCM operation is desired. FF PWM modulates both switch-on and switch-off times (their sum is constant by definition), and a given converter operates in either CCM or DCM depending on the input voltage and the load conditions. Exactly the same result can be achieved if the on-time only is modulated and the off-time is kept constant, in which case, however, the switching frequency is no longer fixed. This is referred to as “fixed-off-time” (FOT) control. Peak-current-mode control can still be used. In this application note transition mode is studied in depth.

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AN3027	TM PFC operation (boost topology)

2 TM PFC operation (boost topology)

The operation of the PFC transition mode controlled boost converter can be summarized in the following description.

The AC mains voltage is rectified by a bridge and the rectified voltage is delivered to the boost converter. This, using a switching technique, boosts the rectified input voltage to a regulated DC output voltage (Vo).

The boost converter consists of a boost inductor (L), a controlled power switch (Q), a catch diode (D), an output capacitor (Co) and, obviously, a control circuit (see figure below). The goal is to shape the input current in a sinusoidal fashion, in phase with the input sinusoidal voltage. To do this, the L6563S uses the transition mode technique.

Figure 2. Boost converter circuit

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The error amplifier compares a partition of the output voltage of the boost converter with an internal reference, generating an error signal proportional to the difference between them. If the bandwidth of the error amplifier is narrow enough (below 20 Hz), the error signal is a DC value over a given half-cycle.

The error signal is fed into the multiplier block and multiplied by a partition of the rectified mains voltage. The result is a rectified sinusoid whose peak amplitude depends on the mains peak voltage and the value of the error signal.

The output of the multiplier is in turn fed into the (+) input of the current comparator, thus it represents a sinusoidal reference for PWM. In fact, when the voltage on the current sense pin (instantaneous inductor current multiplied by the sense resistor) equals the value on the

(+) of the current comparator, the conduction of the MOSFET is terminated. As a

consequence, the peak inductor current is enveloped by a rectified sinusoid. As demonstrated in Section 3.3.4, TM control causes a constant on-time operation over each

line half-cycle.

After the MOSFET has been turned off, the boost inductor discharges its energy into the load until its current goes to zero. The boost inductor has now run out of energy, the drain node is floating and the inductor resonates with the total capacitance of the drain. The drain voltage drops rapidly below the instantaneous line voltage and the signal on ZCD drives the MOSFET on again and another conversion cycle starts.

This low voltage across the MOSFET at turn-on reduces both the switching losses and the total drain capacitance energy that is dissipated inside the MOSFET.

The resulting inductor current and the timing intervals of the MOSFET are shown in Figure 3, where it is also shown that, by geometric relationships, the average input current

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TM PFC operation (boost topology)	AN3027

(the one which is drawn from the mains) is just one-half of the peak inductor current waveform.

Figure 3. Inductor current waveform and MOSFET timing

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The system operates not exactly on, but very close to, the boundary between continuous and discontinuous current mode and that is why this system is called a transition mode PFC. Besides the simplicity and the few external parts required, this system minimizes the inductor size due to the low inductance value needed. On the other hand, the high current ripple on the inductor involves high RMS current and high noise on the rectified main bus, which needs a heavier EMI filter to be rejected. These drawbacks limit the use of the TM PFC to lower power range applications.

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AN3027	Designing a TM PFC

3 Designing a TM PFC

The following section describes a design flowchart of a 100 W transition mode PFC, using the L6563S. The same design procedure and formulas proposed can also be applied for dimensioning a similar 100 W transition mode PFC, using the L6563H.

3.1Input specifications

This section details the specifications of the operating conditions of the circuit that are needed for the calculations given in Section 3.2. In this example an L6563S, wide input

range mains PFC circuit has been considered. Some design criteria are also given.

● Mains voltage range (Vac rms):		VACmin = 90Vac VACmax = 265Vac	(1)
●	Minimum mains frequency	fMAINS = 47 Hz	(2)
●	Rated output power (W):	Pout = 100 W	(3)

Because the PFC is a boost topology, the regulated output voltage depends mainly on the maximum AC input voltage. In fact, for correct operation the output voltage must be always higher than the input and thus, because Vin max is 265·1.414 = 374.7 Vpk, the output has been set at 400 Vdc as typical value. If the input voltage is higher, as is typical in ballast applications, the output voltage must be set higher accordingly. As a rule of thumb, the output voltage must be set 6/7% higher than the maximum input voltage peak.

● Regulated DC output voltage (Vdc):

Vout = 400 V

(4)

The target efficiency and PF are set here at minimum input voltage and maximum load. They are used for the calculations of the operating conditions of the PFC in Section 3.2. Of

course at high input voltage, the efficiency is higher.

●	Expected efficiency (%):	η = 94%	(5)
●	Expected power factor:	PF = 0.99	(6)

Because of the narrow loop voltage bandwidth, the PFC output can face overvoltages at startup or in the case of load transients. To prevent excessive output voltage that can overstress the output components and the load, in the L6563S a pin of the device (PFC_OK, pin #7) has been dedicated to monitor the output voltage with a separate resistor divider, selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset

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Designing a TM PFC	AN3027

value (VOVP), usually larger than the maximum Vout that can be expected, also including worst-case load/line transients.

● Maximum output voltage (Vdc):

VOVP = 430 V

(7)

The mains frequency generates a 2fMAINS voltage ripple on the output voltage at full load. The ripple amplitude determines the current flowing into the output capacitor and the ESR.

Additionally, a request for a certain hold-up capability can be sent to the PFC if mains dips occur in which case the output capacitor also must be dimensioned, taking into account the required minimum voltage value (Vout min) after the hold-up time (tHold) has elapsed.

● Maximum output low-frequency ripple:		∆Vout = 20 V	(8)
●	Minimum output voltage after line drop (Vdc):	Vout min = 300 V	(9)
●	Hold-up capability (ms):	tHold = 10 ms	(10)

The PFC minimum switching frequency is the one of the main parameters used to dimension the boost inductor. Here we consider the switching frequency at low mains on the top of the sinusoid and at full load conditions. As a rule of thumb, it must be higher than the audio bandwidth in order to avoid audible noise and additionally it must not interfere with the L6563S minimum internal startup period, given in the datasheet. On the other hand, if the minimum frequency is set too high, the circuit shows excessive losses at a higher input voltage and probably skips switching cycles not only at light load. The typical minimum frequency range is 20 - 50 kHz for wide range operation.

● Minimum switching frequency (kHz):

fsw min = 40 kHz

(11)

In order to properly select the power components of the PFC and dimension the heatsinks in case they are needed, the maximum operating ambient temperature around the PFC circuitry must be known. Please note that this is not the maximum external operating temperature of the entire system, but it is the local temperature at which the PFC components are working.

● Maximum ambient temperature (°C):

Tambx = 50°C

(12)

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AN3027	Designing a TM PFC

3.2Operating conditions

The first step is to define the main parameters of the circuit, using the specifications given in

Section 3.1.

●Rated DC output current:

Equation 1

	Iout =	Pout	Iout =	100 W	= 0.25 A
		Vout		400 V

●Maximum input power:

Equation 2

	Pin	=	Pout	Pin =	100 W	100	= 106.38 W
			η		94

●RMS input current:

Equation 3

	Iin =	Pin	Iin =	106.38 W	= 1.19 A
		VACmin PF
				90Vac 0.99

●Peak inductor current:

Equation 4

ILpk = 2 2 Iin ILpk = 2 2 1.19 A = 3.38 A

As shown in Figure 3, the inductor current is a triangle shape at the switching frequency, and the peak of the triangle is twice its average value. The average value of the inductor

current is exactly the peak of the input sine wave current, and therefore it can be easily calculated as its RMS value can be obtained from Equation 3. In order to provide a complete

inductor specification for the inductor manufacturer, we must also provide the RMS and the AC current that can be calculated using Equation 5 and Equation 6.

●RMS inductor current:

Equation 5

ILrms	= 2 Iin	ILrms	= 2 1.19 A = 1.38 A
	3		3

●AC inductor current:

Equation 6

ILac = IL2rms − Iin2 ILac = (1.38)2 − (1.19 A)2 = 0.69 A

The current flowing in the inductor can be split in two parts, depending on the conduction instant. During the on-time, the current increases from zero up the peak value and circulates into the switch, while during the following off-time the current decreases from its peak down to zero and circulates into the diode. Therefore these two components have a current with a triangular wave, with the same peak value equal to that of the inductor. Thus, it is also possible to calculate the RMS current flowing into the switch and into the diode, needed to calculate the losses of these two elements.

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Designing a TM PFC	AN3027

●RMS switch current:

Equation 7

ISWrms = ILpk

1

−

4 2

VACmin

ISWrms = 3.38 A

1

−

4 2

90Vac

= 1.18 A

6

9π

Vout

6

9π

400 V

●RMS diode current:

Equation 8
IDrms = ILpk	4 2		VACmin	IDrms = 3.38 A	4	2		90Vac	= 0.72 A
	9π		Vout		9π			400 V

3.3Power section design

3.3.1Bridge rectifier

The input rectifier bridge can use standard slow recovery, low-cost devices. Typically a 600 V device is selected in order to have good margin against mains surges. An NTC resistor limiting the current at turn-on is required to avoid excessive stress to the diode bridge.

The rectifier bridge power dissipation can be calculated using Equation 9, Equation 10, Equation 11. The threshold voltage and dynamic resistance of a single diode of the bridge

can be found in the datasheet of the device.

Equation 9

I	=	2 Iin	=	2 1.19 A = 0.84 A
inrms		2		2
Equation 10
I	=	2 Iin	=	2 1.19 A = 0.54 A
in _ avg		π		π

The power dissipated on the bridge GBU4J is:

Equation 11

Pbridge = 4 Rdiode I2inrms + 4 Vth Iin _ avg

Pbridge = 4 0.04 Ω (0.84 A)2 + 4 0.7 V 0.54 A = 1.62 W

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AN3027	Designing a TM PFC

3.3.2Input capacitor

The input high-frequency filter capacitor (Cin) has to attenuate the switching noise due to the high-frequency inductor current ripple (twice the average line current, Figure 3).

The worst conditions occur on the peak of the minimum rated input voltage. The maximum high-frequency voltage ripple across Cin is usually imposed between 5% and 20% of the minimum rated input voltage. This is expressed by a coefficient r (= 0.05, 0.2) as an input design parameter:

● Ripple voltage coefficient (%):					r = 0.15	(13)
Equation 12
Cin	=	Iin	Cin	=	1.19A		= 0.359 µF
		2π fsw min r VACmin			2π 40 kHz 0.15
						90Vac

In real conditions the input capacitance is designed to take the EMI filter into account and to have a tolerance on the component of about 5% -10% (typ. for polyester capacitors).

A commercial capacitor of Cin = 0.47 µF has been selected. Of course a bigger capacitor benefits the EMI but hurts the THD, especially at high mains. Therefore a compromise must be found between these two parameters. A good quality film capacitor for this component must be selected in order to have an effective filter.

3.3.3Output capacitor

The selection of the output bulk capacitor (Co) depends on the DC output voltage (4), the allowed maximum output voltage (7) and the converter output power (3).

The 100/120 Hz (twice the mains frequency) voltage ripple (∆Vout = peak-to-peak ripple value) is a function of the capacitor impedance and the peak capacitor current:

Equation 13

∆V	= 2 I		1				+ ESR2
out	out	(2	π 2f	C		)2
					O
			l

With a low ESR capacitor the capacitive reactance is dominant, therefore:

Equation 14

	CO ≥	Iout	=	Pout	CO ≥	100W	= 42.5	µF
		2π fl ∆Vout		2π fMAINS Vout ∆Vout		2π 47 Hz 400 V 20 V

∆Vout is usually selected in the range of 1.5% of the output voltage. Although ESR usually does not affect the output ripple, it should be taken into account for calculating the power losses. The total RMS capacitor ripple current, including mains frequency and switching frequency components, is:

Equation 15

ICrms = ID2rms − Iout2

ICrms = (0.72 A)2 − (0.25 A)2 = 0.67 A

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Designing a TM PFC	AN3027

If the PFC stage has to guarantee a specified hold-up time, the selection criterion of the capacitance changes. Co has to deliver the output power for a certain time (tHold) with a specified maximum dropout voltage (Vout min) that is the minimum output voltage value (which takes load regulation and output ripple into account). It is also the minimum output operating voltage threshold before triggering the “power fail” detection and consequent stopping of the downstream system supplied by the PFC.

Equation 16

CO =		2 Pout	tHold	CO =	2 100 W 10 ms	= 36.7 µF
	(V		)2 − V2
		− ∆V			(400 V − 20 V)2 − (300 V)2
	out	out	out min

A 20% tolerance on the electrolytic capacitors has to be taken into account for the right dimensioning. As shown in Equation 14, for this application a capacitor CO = 47 µF (450 V)

has been selected in order to maintain a hold-up capability of 14 ms. The actual output voltage ripple with this capacitor is also calculated. In detail:

Equation 17

C

O

(V − ∆V

)2 − V2

47 µF

[(

)2

(

)2 ]

out

out

out min

400 V − 20V

− 300 V

thold =

= 14.78 ms

thold =

2 Pout

2 100 W

As expected the ripple variation on the output is:

Equation 18

∆Vout	=		Iout	∆Vout =	0.25A		= 18.02 V
			π fl CO		2 π 47 Hz
	2					47 µF

3.3.4Boost inductor

The boost inductor determines the operating frequency of the converter, thus it is usually calculated so that the minimum switching frequency is greater than the maximum frequency of the L6563S internal startup (150 µs typ.), to ensure correct TM operation. Assuming unity PF:

Equation 19

	ton (VAC,ϑ) =	L ILpk sin(ϑ)		=	L ILpk
		2	VAC sin(ϑ)		2	VAC

Equation 19 demonstrates that the on-time doesn't depend on the mains phase angle, but it is constant over the entire mains cycle.

Equation 20

	toff (VAC,ϑ) =	L ILpk sin(ϑ)
		− 2 VAC sin(ϑ)
	Vout

ton and toff represent respectively the on-time and the off-time of the power MOSFET. ILpk is the maximum peak inductor current in a line cycle and θ is the instantaneous line phase of

the interval [0,Π]). Note that the on-time is constant over a line cycle.

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AN3027	Designing a TM PFC

As previously stated, ILpk is twice the line-frequency peak current Equation 4, which is related to the input power and the input mains voltage. Substituting this relationship in the expressions of ton and toff, after some algebra it is possible to find the instantaneous switching frequency along a line cycle:

Equation 21

			1		1		VAC2 (V − 2 VAC sin(θ))
	fsw	(VAC,θ) =		=			out
			Ton + Toff		L Pin		Vout
				2

The switching frequency is minimum at the top of the sinusoid (θ = Π /2 ==> sin θ =1), maximum at the zero crossings of the line voltage (θ = 1 or Π ==> sin θ =0), where toff =0.

The absolute minimum frequency fswmin can occur at either the maximum VACmax or the minimum mains voltage VACmin, thus the inductor value is defined by the formula:

Equation 22

= VAC2 (Vout − 2 VAC)

L(VAC)

2 fsw min Pin Vout

After calculating the values of the inductor at low mains and at high mains L(VACmax), L(VACmin) Equation 23, the lowest value must be used. It becomes the maximum

inductance value for the PFC dimensioning.

Equation 23

L(VACmin ) = (90Vac)2 (400 V −		2 90Vac) = 0.642 mH
	2 40 kHz 106.38 W 400 V
L(VAC ) = (265Vac)2 (400 V −		2 265Vac) = 0.515 mH
max	2 40 kHz 106.38 W 400 V

For this application a 0.52 mH boost inductance has been selected.

Figure 4. Switching frequency, fixing the line voltage

	&REQUENCY MODULATION WITH THE ,INE HALF PERIOD
			3WITCHING &REQ	6!#MIN
			3WITCHING &REQ	6!#MAX
=
&REQUENCYY;K(Z
			Θ ; LINE HALF PERIOD =			!-V

The figure above shows the switching frequency versus the θ angle calculated with Equation 22, a 0.52 mH boost inductance and fixing the line voltage at minimum and maximum

Doc ID 16134 Rev 4

13/41