ST AN3024 APPLICATION NOTE
AN3024
Application note
SPC560B4x/5x, SPC560C4x/5x hardware design guideline
Introduction
This application note complements the information in the SPC560Bxx and SPC560Cxx
device datasheet (see Section Appendix A: Document management) by describing
requirements useful for a hardware implementation of the development board features such
as power supply, reset control, clock management, boot mode setting, debug management
and I/Os settings. It shows how to use the product and defines the minimum hardware
resources required to start an application development.
Sections of this document describe certain device features in brief without describing the
device blocks in detail. For a detailed description of these features, refer to the device
datasheet, the reference manual RM0017 or the SPC560Bxx and SPC560Cxx errata sheet,
or all three documents (see Section A.1: Reference documents).
This application note applies to the SPC560Bxx and SPC560Cxx devices listed in Ta b le 1 .
T a ble 1. Device summary
Reference Part number
SPC560B4x
SPC560B5x
SPC560C4x
SPC560C5x
SPC560B40L3, SPC560B40L5, SPC560B44L3
SPC560B50L3, SPC560B50L5, SPC560B50B2
SPC560C40L3, SPC560C44L3
SPC560C50L3
June 2012 Doc ID 16127 Rev 3 1/27
www.st.com
Contents AN3024
Contents
1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Current consumption and voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Power-on reset (POR) and low voltage detectors (LVDs) . . . . . . . . . . . . . 10
2.3 System reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.1 Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2 Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Reset scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 ADC performances optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 External oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Fast external crystal oscillator (4 to 16 MHz) . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Slow external crystal oscillator (32 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.1 Some recommended crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Boot pin scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 JTAG I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/27 Doc ID 16127 Rev 3
AN3024 Contents
6.3 JTAG connector scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2 I/O types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3 I/Os configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.4 Maximum output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.5 I/O characteristic in STANDBY mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.6 General consideration for I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8 EMC guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.1 SPC560Bxx/Cxx software configurations . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.2 Hardware guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9 Reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Appendix A Document management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
A.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
A.2 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Doc ID 16127 Rev 3 3/27
List of tables AN3024
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Recomanded crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. I/O supply segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4/27 Doc ID 16127 Rev 3
AN3024 List of figures
List of figures
Figure 1. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Typical layout for VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. System reset and low power circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Reference reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. ADC input scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Reference oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Low power oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Oscillator circuitry layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. JTAG connector scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15. Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 16127 Rev 3 5/27
Power supplies AN3024
1 Power supplies
1.1 Introduction
The device requires a 3.3 V or 5.0 V operating voltage supply (high voltage). An embedded
regulator is used to supply the internal 1.2 V digital power (low voltage).
Three different high voltage pin supply types are used:
● VDD_HV—high voltage external power supply for internal voltage regulators, I/O pins
and Flash
● VDD_BV—high voltage external power supply for internal voltage regulator ballast
transistors
● VDD_HV_ADC—high voltage external power supply for analog-to-digital converter
Three different independent voltage regulators provide the 1.2 V digital power supply:
● HPREG—high power internal voltage regulator used during normal operations. It can
be switched off in STOP mode and is automatically switched off in STANDBY mode.
● LPREG—low power internal voltage regulator used when HPREG is off. It can be
switched off in STOP mode and is automatically switched off in STANDBY mode.
● ULPREG—ultra low power internal voltage regulator. Always switched on and used in
STANDBY or in STOP mode when all other regulators are switched off.
External capacitors connected between the VDD_LV/VSS_LV pin pairs ensure the stability
of the internal 1.2 V HPREG and LPREG regulators.
Figure 1. Power supply overview
V
DD
VDD_BV
C
BAL
ctrl
ULPREG
V
DD
C
C
VDD_HV
DECn
VDD_LV
REGm
ctrl
LPREG
ctrl
HPREG
8-KB SRAM
WKPU
RC
24-KB SRAM
CFlash
DFlash
PLL
Power Domain 0
Power Domain 2
16-KB SRAM
Core
Power Domain 1
OSC
Peripherals
Standby
Standby
Peripherals
Main
ADC
VDD_HV_ADC
VSS_HV_ADC
V
DD
For a detailed list of supply-related pins for all packages, please refer to the voltage supply
pins section in RM0017 (see Section A.1: Reference document).
6/27 Doc ID 16127 Rev 3
AN3024 Power supplies
1.2 Power supply scheme
The circuit is powered by a stabilized power supply VDD.
● VDD_HV pins must be connected to V
● VDD_BV pin must be connected to V
● VDD_HV_ADC pin be connected to V
● VDD_LV pins must be connected with external decoupling capacitors C
close as possible to the device pins.
● VSS_HV and VSS_LV pins must all be connected together to GND.
Refer to the voltage regulator electrical characteristics section in the device datasheet (see
Section A.1: Reference document) for exact capacitor values.
Figure 2. Power supply scheme
with external decoupling capacitors C
DD
with external decoupling capacitor C
DD
with external decoupling capacitor C
DD
REGm
.
DECn
.
BAL
.
ADC
placed as
V
DD
C
BAL
V
DD
C
DECn
C
REGm
Note:
The device cannot be supplied with external 1.2 V. The on-chip regulator must always be used.
VDD_BV
VDD_HV 1/2/../n
VSS_HV 1/2/../n
VDD_LV 1/2/../m
VSS_LV 1/2/../m
SPC560B/C4/5x
VDD_HV_ADC
VSS_HV_ADC
V
DD
C
ADC
Caution: All BV and HV and ADC supplies must be powered with a voltage level in the range
V
± 0.1 V, and all grounds must be in the range V
DD
SS
± 0.1 V.
1.3 Current consumption and voltage regulator
In order to select a suitable external voltage regulator and design a supply circuit, the
designer of the application must consider:
1. The maximum consumption in steady state
2. The maximum inrush current during device start-up
The maximum consumption in steady state depends on the frequency of the CPU, the
usage of the peripheral and the current drawn by the outputs. It can be estimated by
referring to the device datasheet (see Section A.1: Reference document).
Doc ID 16127 Rev 3 7/27
Power supplies AN3024
The inrush current required by the device during power-on reset or exit from STANDBY is
clamped at 400 mA and lasts for few microseconds (maximum 20 µs
) until the C
REGm
stabilization capacitors (total value ~1 µF) are charged. This current is drawn from the
VDD_BV pin.
Note: The inrush current must be considered to dimension the decoupling capacitance of the
ballast (C_DEC1) value as during this inrush the application must ensure V
remains in
DD
the voltage range of the application (5 V or 3.3 V ±10 %). The steady current is used to
define the voltage regulator capability of the application.
1.4 Layout recommendations
All the supply connections, including pads, tracks and vias, must have impedance as low as
possible (less than 5 nH). This is typically achieved by using thick and wide Cu tracks and
preferably dedicated power supply planes in multilayer PCBs.
Moreover, it is recommended to use both low equivalent series resistance (ESR) and low
equivalent series inductance (ESL) capacitors. The capacitors must be placed as close as
possible to, or below, the appropriate pins on the underside of the PCB. Figure 3 shows the
typical layout of such a V
DD/VSS
pair.
Figure 3. Typical layout for V
Via to V
DD
DD/VSS
pair
Capacitor
V
DD
Via to V
V
SS
SS
8/27 Doc ID 16127 Rev 3
AN3024 Reset
2 Reset
2.1 Introduction
The device has an integrated POR (power-on reset) to ensure a correct power-up
sequence: The device remains in reset state as long as the V
threshold.
is below the specified
DD
The device has four low voltage detectors to monitor V
● LVDHV3—monitors V
so as to ensure that the device reset occurs for voltage values
DD
DD_HV
and V
DD_LV
:
less than minimum functional supply value
● LVDHV5—monitors V
when the application uses devices operating in the range
DD
5.0 V ± 10%. By default the LVDHV5 is disabled (to allow 3.3 V operation) and must be
activated by the application.
● LVDLVCOR—monitors the voltage provided to the main power domain (core, Flash,
PLL, JTAG and peripherals not included in the standby power domain)
● LVDLVBKP—monitors the voltage provided to the power domain in standby mode
(8 Kbyte SRAM, optionally 24 Kbyte SRAM, power control unit, reset generation
module, voltage regulator, wake-up unit, API, CAN sampler, internal RC oscillators,
etc.)
The device has a dedicated bidirectional RESET
pin (NRST) with Schmitt-Trigger
characteristics and noise filter for system reset.
For detailed information on reset sequence, please refer to the reset state machine section
in RM0017 (see Section A.1: Reference document).
Doc ID 16127 Rev 3 9/27
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