ST AN3023 Application note
AN3023
Application note
Using the analog-to-digital converter of the STM8A microcontroller
Introduction
The purpose of this application note is to explain how to use the analog-to-digital converter
implemented in the STM8A microcontroller family. The document provides useful
information on how to configure the ADC registers and microcontroller resources and use
the analog-to-digital converter in different modes.
The STM8A firmware library, containing source code of all the examples described in this
application note, can be downloaded from the STMicroelectronics website: www.st.com.
October 2009 Doc ID 16113 Rev 1 1/23
www.st.com
Contents AN3023
Contents
1 ADC hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 General properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 ADC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Summary of the features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Configuring ADC registers for conversion . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 ADC setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.2 ADC on/off control (power on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.3 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.4 Conversion on external trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.5 Conversion modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Storing converted values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 ADC interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Practical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Areas of use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Hardware connection examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 Methods for precision improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/23 Doc ID 16113 Rev 1
AN3023 ADC hardware description
1 ADC hardware description
1.1 General properties
STM8A family microcontrollers include an analog-to-digital converter which has up to 16
multiplexed inputs. The ADC resolution is 10 bits. The number of external analog inputs
depends on the package size of the particular STM8A family device.
The ADC is a successive approximation analog-to-digital converter. Conversion can be
performed in continuous mode or single mode. The digital result is then stored in registers.
Because the ADC resolution is 10 bits and the ADC data register length is 16 bits, the
analog-to-digital converter result is stored in two 8-bit registers, and the data is either right
or left aligned (this is selectable).
The event used to start conversion can be generated by software or by the STM8A
microcontroller's internal timer 1 and timer 2
(a)
(any type of timer event can be used). The
start of A/D conversion can also be triggered by an external pin.
The reference voltage for the analog-to-digital converter depends on the package. It comes
either from an external source—in this case the reference must be connected to two
external pins—or is connected internally to analog power supply pins. The value of this
reference voltage is limited to within the range from 2.75 V up to the voltage applied on the
V
input. The measured voltage must be between V
DDA
REF+
and V
. Resolution can be
REF−
increased by so-called analog zooming—using a smaller reference voltage around the
range of values to be measured.
If needed, an interrupt can be generated at the end of conversion and if an analog watchdog
event occurred.
The analog-to-digital converter is driven by a clock derived from the MCU master clock
through a programmable divider. This allows you to select the ADC clock speed according to
your application requirements.
a. Trigger feature available on selected devices
Doc ID 16113 Rev 1 3/23
ADC hardware description AN3023
Figure 1. ADC block diagram
Interrupt
AIN0
AIN1
AIN15
ADC_ETR
Genera l
Purpose
IOs
EOC AWD CH3 CH2 CH 1 CH0
4
2
Mux
TIM1
TIM2
Schmitt Trigger Enable TE[7:0]
Schmitt T rigger Enable TE [15:8]
EOCIE
DBUF OVR
2
EXT
TRIG
AWDIE
ADON
ADON
SyncE
Sync
2
Analog-to-Digital
EXT
EXT
SEL1
SEL0
- - - -
SP
SEL2SPSEL1SPSEL0
CK_ADC f
Prescaler
/2, /3 : /1 8
Converter
ALIGN - SCAN -
AWDG voltage reference low
- - CON T ADON
MASTER
AWDG Status Register chan nel [7 :0]
AWDG S tatus Register channel [15 :8]
1. Refer to STM8A reference manual for ADC registers bit description
4/23 Doc ID 16113 Rev 1
Data Re gist er
AWDG voltage refere nce high
Data Bu ffer
AWDG Enable Register ch annel [7 :0]
AWDG E nable Register channel [15:8]
AN3023 ADC hardware description
1.2 ADC operation
The analog-to-digital converter supports two basic conversion modes: single mode and
continuous mode.
Figure 2 and Figure 3 describe single and continuous mode analog-to-digital converter
operation.
In single conversion mode, the analog-to-digital converter performs only one conversion on
the selected channel.
Figure 2. Single conversion mode
CLK
ADON
EOC
Power-on ADC
ADON=1
t
STAB
conversion time (14 clocks)
1 sync clock
3 clocks sampling time
10 clocks conversion
Start conversion
ADON=1 or trigger
ADC inactive
Software clears
EOC bit
Software reads
ADC data
End of conversion
next conversion
Start conversion
ADON=1 or trigger
In continuous conversion mode, the analog-to-digital converter starts another conversion as
soon as the previous one is concluded.
Figure 3. Continuous conversion mode
CLK
ADON
EOC
t
STAB
Power-on ADC
ADON=1
conversion time (14 clocks)
Start conversion
ADON=1 or trigger
End of conversion
Next conversion
starts immediately
next conversion time (14 clocks)
Software reads
ADC data
Software clears
EOC bit
As shown in these figures, after ADC power on, the analog-to-digital converter needs a
stabilization time t
(equivalent to one conversion time t
STAB
) before it starts converting
CONV
accurately. For subsequent conversions there is no stabilization delay and ADON needs to
be set only once.
Doc ID 16113 Rev 1 5/23
ADC hardware description AN3023
The ADC conversion time takes 14 clock cycles. In addition to the basic conversion modes,
some packages have extended features for scan mode and buffered continuous mode.
Figure 4 summarizes all the possible analog-to-digital converter operating modes.
Figure 4. ADC operating modes
Start
Channel X conversion
Stop
Single channel
Single conversion
Start
Channel X conversion
Channel X conversion
Channel X conversion
Channel X conversion
Single channel
Continuous and
Buffered conversion
Start
Channel X conversion
Single channel
Continuous conversion
Start
Channel 1 conversion
...
Channel n conversion
Stop
Start
Channel 1 conversion
...
Channel n conversion
Multiple channel
Continuous and
Scan conversion (buffered)
6/23 Doc ID 16113 Rev 1
Multiple channels
Scan conversion (buffered)
AN3023 Summary of the features
2 Summary of the features
The STM8A family contains two types of analog-to-digital converter which are named ADC
and ADC2. Depending on the device, it may contain both (ADC and ADC2) or only one
(ADC).
There are two variants of the first analog-to-digital converter ADC:
1. With standard features
2. With extended features for scan mode, buffered continuous mode and analog
watchdog
The second analog-to-digital converter, ADC2, contains a features subset of the first ADC
module.
Refer to the STM8A datasheet for more information on the available features.
Table 1. ADC and ADC2 features on different devices
Features
Module
Parameter 32 KB die based
Resolution 10-bit
(1)
(2)
128 KB die based
(2)
256 KB die based
(2)
ADC
Programmable prescaler f
MASTER
divided by 2 to 18
Single or continuous mode
Operating modes
Clock speed f
ADC input range V
Conversion speed min. 3.5 µs @ 4 MHz f
Scan and buffered
continuous mode
—
= 1 to 4 MHz
ADC
= V
SSA
IN
= V
Scan and buffered
continuous mode
DDA
ADC
Number of input channels up to 10 up to 16 up to 16
Triggers
Timer 1 and external
ADC_ETR pin
External ADC_ETR
pin
Timer 1, Timer 2 and
external ADC_ETR pin
Data format left or right alignment
ADC interrupt EOC and AWD EOC EOC and AWD
Analog watchdog Yes — Yes
Schmitt trigger enable/disable Yes Yes Yes
Synchronization mechanism
between ADC and ADC2
Analog zooming —
——Yes
Through dedicated
VREF pins
Through dedicated
VREF pins
Doc ID 16113 Rev 1 7/23
Loading...