ST AN3018 Application note

AN3018

Application note

Developing self tests for SPC564Ax

Introduction

SPC564Ax devices have been designed for Powertrain applications like engine control and transmission.

As these safety applications increasingly need to conform to safety standards like IEC51608 or ISO26262, there is a focus on self tests possible on each of the components of these ECUs, including the microcontroller.

This application note shows how to define and design self tests for SPC564Ax. After an introduction to self tests, the application note is focused initially on self tests for the CPU subsystem, then on those on digital peripherals and finally on those on analog peripherals.

May 2012 Doc ID 16081 Rev 1 1/24

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Contents AN3018

Contents

1 Introduction to self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Self tests for SPC564Ax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Designing software self tests for SPC564Ax . . . . . . . . . . . . . . . . . . . . . 7

2.1 SPC564Ax CRC unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Explicit and implicit self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Self tests for SPC564Ax core subsystem . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Flash self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1.1 Flash integrity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1.2 Flash ECC logic check1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1.3 Flash ECC logic check2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1.4 Flash ECC logic check3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1.5 Flash address decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1.6 Flash margin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2 RAM self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2.1 RAM dormant fault check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2.2 RAM ECC logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2.3 RAM address decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2.4 eTPU code RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3 CPU parallel signature unit tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Self tests for SPC564Ax digital peripherals . . . . . . . . . . . . . . . . . . . . . 15

4.1 CRC unit self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1.1 CRC computing circuitry check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 DMA controller self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2.1 DMA transfer logic check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3 Crossbar self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.4 Memory protection self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.5 Peripheral bridge self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.6 Peripheral configuration self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.6.1 Peripheral configuration check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.7 Interrupt controller self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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AN3018 Contents

4.7.1 Interrupt controller logic check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.8 FlexCAN self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.8.1 FlexCAN check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.9 eSCI self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.9.1 eSCI loop back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.10 eMIOS self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.10.1 eMIOS check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.11 Decimation filter self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.11.1 Decimation filter check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.12 eQADC logic self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.12.1 eQADC effective conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.13 Summary for digital peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 Self tests for SPC564Ax analog peripherals . . . . . . . . . . . . . . . . . . . . . 20

5.1 Oscillator self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1.1 Oscillator check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2 FMPLL self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2.1 FMPLL check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3 eQADC self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3.1 eQADC internal reference check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3.2 Analog input and ADC mux check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3.3 Analog input and ADC mux check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.4 Supply monitor self tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.4.1 1.2 V monitor check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.4.2 Monitor check using eQADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.5 Summary for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Appendix A Document management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

A.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Doc ID 16081 Rev 1 3/24

List of tables AN3018

List of tables

Table 1. Self tests for digital peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 2. Self tests for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 3. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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AN3018 List of figures

List of figures

Figure 1. CRC unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. Parallel signature unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Doc ID 16081 Rev 1 5/24

Introduction to self tests AN3018

1 Introduction to self tests

Self tests can be used at two times of a safety application:

● At power on

● During run time

Power on self tests focus on latent fault detection. They usually cover all modules of a given microcontroller.

Run time self tests focus on single point of failure detection during the application safety time. Additionally, some modules may require a specific run time check (for example, ADC monitor) to be done during run time, so that the FIT rate can be guaranteed on those modules.

1.1 Self tests for SPC564Ax

The application note is focused on describing the possible self tests that can be designed for SPC564Ax. The description given is intended to provide for different uses according to application requirements, such as power on or as run time self tests.

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AN3018 Designing software self tests for SPC564Ax

2 Designing software self tests for SPC564Ax

SPC564Ax devices have been designed using the latest test techniques. Hence, they include several BISTs for logic and for memories (RAMs, Flashes).

Although those BISTs cannot be activated by software, SPC564Ax devices have several hardware features enabling the design of fast and efficient self tests.

2.1 SPC564Ax CRC unit

The CRC unit allows the design of several self tests. When combined with the use of eDMA, the self tests can be implemented without CPU load. This method is described in a specific application note. The figure below illustrates the principle of this method and shows concurrent accesses between CPU software using RAM and Flash together with the eDMA and CRC unit.

Doc ID 16081 Rev 1 7/24

Designing software self tests for SPC564Ax AN3018

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Note: The CRC unit has 3 independent contexts to allow independent CRC computing from CPU

side (for example, adding applicable CRC to data) and from eDMA.

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