ST AN2984 Application note

AN2984

Application note

Minimizing the SET-related effects

on the output of a voltage linear regulator

Introduction

This application note deals with the effects of SET (single event transient) on the
RHFL4913A low-drop linear regulator. After a short description of the phenomenon, some
solutions for coping with these effects are introduced and discussed.

The RHFL4913A voltage regulator

The RHFL4913A is an adjustable high-performance positive voltage regulator with
exceptional radiation performance. It is tested in accordance with the Mil Std 883E method

1019.6, in ELDRS conditions. The device is available in the Flat-16 and the new SMD5C
hermetic ceramic package, as shown in
designed for space and harsh radiation environments. In Figure 2 the internal block diagram
is shown.

Figure 1, and the QML-V die is specifically

Figure 1. RHFL4913A packages

FLAT-16

SMD5C

5-connection SMD

June 2010 Doc ID 15690 Rev 1 1/8

www.st.com

Figure 2. Internal block diagram

AN2984

The RHFL4913A operates with an input supply of up to 12 V. To adjust the output voltage,
the R2 resistor must be connected between the V

and ADJ pins. The R1 resistor must be

O

connected between the ADJ and ground. Resistor values can be derived from the following
formula:

The V

VO = V

is 1.23 V, controlled by the internal temperature-compensated band-gap block.

ADJ

(R1 + R2) / R1

ADJ

The minimum output voltage is therefore 1.22 V and the minimum input voltage is 3 V. The
adjustable RHFL4913A is functional as soon as the (V

- VO) voltage difference is slightly

I

above the power element saturation voltage. The ADJ pin to ground resistor value must not
be greater than 10 kΩ, in order to keep the output feedback error below 0.2 %. A minimum of

0.5 mA I
current into the divider bridge resistor. All available V

must be set to ensure perfect no-load regulation. It is advisable to dissipate this

O

pins, as well as all available VO pins,

I

should always be externally interconnected, otherwise the stability and reliability of the
device cannot be guaranteed. The inhibit function switches off the output current
electronically, and therefore very quickly.

According to Lenz's Law, external circuitry reacts with Ldi/dt terms, which can be of high
amplitude where a serial coil inductance exists. Large transient voltage would develop on
both device terminals. It is advisable to protect the device with Schottky diodes to prevent
negative voltage excursions. In the worst case, a 14 V Zener diode can protect the device
input. The device has been designed for high stability and low dropout operation. Therefore,
tantalum input and output capacitors with a minimum 1 µF are mandatory. The ESR
capacitor range is from 0.01 Ω to over 20 Ω . This range is useful when ESR increases at a
low temperature. When large transient currents are expected, larger value capacitors are
necessary. In the case of high current operation with short circuit events expected, caution
must be exercised with regard to capacitors. They must be connected as close as possible

2/8 Doc ID 15690 Rev 1

AN2984

to the device terminals. As some tantalum capacitors may permanently fail when subjected
to high charge-up surge currents, it is recommended to decouple them with 470 nF
polyester capacitors.

As the RHFL4913A adjustable voltage regulator is manufactured with very high speed
bipolar technology (6 GHz f

transistors), the PCB layout must be designed with exceptional

T

care, with very low inductance and low mutually coupling lines. Otherwise, high frequency
parasitic signals may be picked up by the device resulting in system self-oscillation. The
benefit is an SVR performance extended to far higher frequencies.

In order to replace a standard 3-terminal industry device, fixed voltage versions are
available.

A separate Kelvin voltage sensing line provides the ADJ pin with exact load “high potential”
information. But variable remote load current consumption induces variable Iq current (Iq is
roughly the I

current divided by the hFE of the internal PNP series power element) routed

OUT

through the parasitic series line RW2 resistor. To compensate for this parasitic voltage, an
RW1 resistor can be introduced to provide the necessary compensating voltage signal to
the ADJ pin, as shown in

Figure 3. Application schematic for remote load operation

Figure 3.

In the case of an FPGA power supply, as these devices are very sensitive to VDD transients
beyond a small percentage of their nominal supply voltage (usually 1.5 V), special attention
must be taken to mitigate possible heavy-ion disturbances. The worst case heavy-ion effect
can be summarized as the following: the RHFL4913A internal control loop being cut
(opened) or short-circuited for a sub-microsecond duration. During such an event, the
RHFL4913A die power element can either provide excessive current or current supply
stoppage to the output (V

) for a duration of about one microsecond, after which time the

OUT

voltage regulator smoothly recovers to nominal operation. To mitigate these “transients”, it is
recommended to firstly implement the PCB layout using the following notes:

● Minimizing series/parallel parasitic inductances of the PC path;

● Using a low ESR 47 µF tantalum V

capacitor in parallel with the former (to reduce dynamic ESR);

filtering capacitor with a 470 nF ceramic

OUT

With this implementation, the ELDO simulated worst transient case shows no more than a
90 mV deviation from the nominal line voltage value.

Doc ID 15690 Rev 1 3/8