ST AN2960 Application note

AN2960

Application note

LIS331DL: 3-axis - ±2 g /±8 g digital output ultra compact linear accelerometer

Introduction

This document is intended to provide application information for the LIS331DL low-voltage 3-axis digital output linear MEMS accelerometer housed in an LGA package.

The LIS331DL is an ultra-compact low-power 3-axis linear accelerometer that includes a sensing element and an IC interface capable taking information from the sensing element and providing the measured acceleration data to external applications via an I2C/SPI serial interface.

The sensing element used to detect acceleration is manufactured using a dedicated process developed by ST to produce inertial sensors and actuators in silicon.

The IC interface is instead manufactured using a CMOS process that allows a high level of integration to design a dedicated circuit which is factory trimmed to better match the sensing element characteristics.

The LIS331DL has a user-selectable full scale of ±2 g and ±8 g and is capable of measuring accelerations with an output data rate of 100 Hz or 400 Hz. A self-test capability allows the user to check that the system is operating correctly.

The device features two independent, highly programmable interrupt sources that can be configured either to generate an inertial wake-up interrupt signal when a programmable acceleration threshold is exceeded along one of the three axes, to detect a free-fall or to recognize single/double click events.

Two independent pins can be configured to provide interrupt signals to connected devices.

The LIS331DL is available in a plastic SMD package and is designed to operate over a temperature range extending from -40 °C to +85 °C.

The ultra small size and weight of the SMD package make it an ideal choice for handheld portable applications such as cell phones and PDAs, or any other application where reduced package size and weight are required.

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www.st.com

Contents	AN2960

Contents

1	Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
2	Electrical connection and board layout hints . . . . . . . . . . . . . . . . . . . . .		7
	2.1	Electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	2.2	Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
3	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
4	Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
	4.1	I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10

4.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1.2 I2C subsequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

	4.2.1	Read & write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	4.2.2	SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	4.2.3	SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	4.2.4	SPI Read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
5	Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17

5.1 Register address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1.1 Reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.2 Registers loaded at boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6	About control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	6.1	CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	6.2	CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	6.3	CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21

7	Data and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23
	7.1	WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	7.2	STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	7.3	OUTX (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	7.4	OUTY (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24

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	7.5	OUTZ (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 24
8	Free-fall and wake-up registers . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 25
	8.1	HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 25
	8.2	FF_WU_CFG_1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 25
	8.3	FF_WU_SRC_1 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 26
	8.4	FF_WU_THS_1 (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 27
	8.5	FF_WU_DURATION_1 (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 28
	8.6	FF_WU_CFG_2 (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 29
	8.7	FF_WU_SRC_2 (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 30
	8.8	FF_WU_THS_2 (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 30
	8.9	FF_WU_DURATION_2 (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 31
9	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 32
	9.1	Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 32
	9.2	Reading acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 32

9.2.1 Using the status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2.2 Using the DataReady signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9.3 Understanding acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.4 Interrupt generation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.5 Inertial wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.5.1 HP filter bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.5.2 Using the HP filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9.6 Free-fall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.6.1	Roll function not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
9.6.2	Roll function applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37

9.7 Output data rate selection and reading timing . . . . . . . . . . . . . . . . . . . . . 37 9.8 DataReady vs. interrupt signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

40

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List of tables	AN2960

List of tables

Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3. Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. Registers address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Output data register content vs. acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 6. Output data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 7. Timing value to avoid data loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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AN2960	List of figures

List of figures

Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. LIS331DL electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. I2C subsequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 4. Read & write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Multiple byte SPI read protocol (example using 2 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. Multiple bytes SPI write protocol (example using 2 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10. Digital processing chain block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 11. FF_WU_CFG_1,2 high and low value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 12. DCRM bit function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 13. Interrupt generation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 14. Free-fall, wake-up interrupt generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 15. Reading timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 16. Interrupt and DataReady signal generation block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 17. DataReady signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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Theory of operation	AN2960

1 Theory of operation

The LIS331DL is an ultra compact, low-power, digital output 3-axis linear accelerometer packaged in an LGA package. The complete device includes a sensing element and an IC interface capable of taking information from the sensing element and providing a signal to external applications through an I2C/SPI serial interface (Figure 1).

A proprietary process is used to create a surface micro-machined accelerometer. The technology allows the creation of suspended silicon structures which are attached to the substrate at a few points, called “anchors”, and are free to move in the direction of the sensed acceleration. To be compatible with traditional packaging techniques, a cap is placed on top of the sensing element to avoid the blockage the moving parts during the moulding phase of the plastic encapsulation.

When an acceleration is applied to the sensor, the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor.

In steady state, the nominal value of the capacitors are a few pico farads, and when an acceleration is applied the maximum variation of the capacitive load is of a few femto farads.

The complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage, and by analog-to-digital converters.

The acceleration data may be accessed through an I2C/SPI interface, making the device particularly suitable for direct interfacing with a microcontroller.

Data synchronization in a digital system employing the device is made simpler through the use of the DataReady signal (RDY), which indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system employing the device.

The LIS331DL also features two independent, fully-programmable interrupt sources which can be programmed to generate an interrupt signal when a programmable acceleration threshold is exceeded along one of the three axes, or to detect a free-fall event.

The IC interface is factory calibrated for sensitivity (So) and zero-g level (Off).

The trimming values are stored in the device by a non-volatile structure. Any time the device is turned on, the trimming parameters are loaded into the registers to be employed during normal operation. This allows the user to use the device without further calibration.

Figure 1. Device block diagram

		X+
		Y+	CHARGE			CS
		Z+
			AMPLIFIER			SCL/SPC
					I2C
	a		A/D			SDA/SDO/SDI
		MUX		CONTROL LOGIC
			CONVERTER
					SPI	SDO
		Z-
		Y-
		X-
				CLOCK	CONTROL LOGIC	INT 1
	SELF TEST	REFERENCE	TRIMMING		&
			CIRCUITS		INTERRUPT GEN.	INT 2

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AN2960	Electrical connection and board layout hints

2 Electrical connection and board layout hints

2.1Electrical connection

The typical electrical connection of the LIS331DL is shown in Figure 2.

Figure 2. LIS331DL electrical connection

Vdd
			Z
1		13
10µF
Vdd_IO
			1
			X
	TOP VIEW		INT 1
100nF
5		9	INT 2
			Y
	DO		(TOP VIEW)
			DIRECTION OF THE
SCL/SPC	SDA/SDI/S SDO/SA0
			DETECTABLE
		CS	ACCELERATIONS
GND
Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO

AM03707v1

The LIS331DL is designed to operate with a supply voltage spanning from 2.16 V up to 3.6 V, while the serial interface can function down to 1.8 V.

The device core is supplied through the Vdd line (Vdd typ=2.5 V) while the I/O pads are supplied through the Vdd_IO line. The typical current consumption in normal mode at 2.5 V is 400 µA.

Both voltage supplies must be present at the same time to ensure proper behavior of the IC. It is possible to remove Vdd, maintaining Vdd_IO, without blocking the communication bus.

Adequate power supply decoupling is required to ensure IC performance. Optimum decoupling is achieved by using two capacitors of different types that target different kinds of noise on the power supply leads. To attenuate high frequency transients, spikes, or digital hash on the line, the use of one 100 nF ceramic or polyester capacitor is recommended, which must be placed as close as possible to the device Vdd lead. For filtering lowerfrequency noise signals, a larger aluminum capacitor of 10 µF or greater should be placed near the device in parallel with the former capacitor. It is recommended to place these capacitors as near as possible to pin 14 of the device.

The functionality of the device and the measured acceleration data are selectable and accessible through the I2C/SPI interface. When using the I2C, the CS must be tied high while the SDO allows the user to select between two device addresses in cases where two

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Electrical connection and board layout hints	AN2960

sensors must be connected on the same bus. Whenever a single sensor is present on the same I2C bus, it is recommended either to connect SDO to Vdd_IO, or to leave it floating.

2.2Soldering information

The LGA-14 package is lead-free and green package qualified for soldering heat resistance according to JEDEC J-STD-020C. Land pattern and soldering recommendations are available upon request.

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AN2960	Absolute maximum ratings

3 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

	Table 1.	Absolute maximum ratings
	Symbol	Ratings	Maximum Value	Unit
	Vdd	Supply voltage(1)	-0.3 to 6	V
	Vdd_IO	I/O pin supply voltage(1)	-0.3 to 6	V
	Vin	Input voltage on any control pin	-0.3 to Vdd_IO +0.3	V
		(CS, SCL/SPC, SDA/SDI/SDO, CK)
	APOW	Acceleration (any axis, powered, Vdd=2.5V)	3000 g for 0.5 ms
			10000 g for 0.1 ms
	AUNP	Acceleration (any axis, unpowered)	3000 g for 0.5 ms
			10000 g for 0.1 ms
	TOP	Operating temperature range	-40 to +85	°C
	TSTG	Storage temperature range	-40 to +125	°C
	ESD	Electrostatic discharge protection	Class 1: 0 - 2 kV HBM

1. Supply voltage on any pin should never exceed 6.0 V

Warning:This is an ESD sensitive device. Improper handling can cause permanent damage to the part.

Warning:This is a mechanical shock-sensitive device, improper handling can cause permanent damage to the part.

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Digital interfaces	AN2960

4 Digital interfaces

The registers embedded in the LIS331DL may be accessed through I2C and SPI serial interfaces. The latter may be SW configured to operate in either 3-wire or 4-wire interface mode.

The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, the CS line must be tied high (i.e. connected to Vdd_IO).

	Table 2.	Serial interface pin description
	Pin Name		Pin description
		CS	SPI chip select (CS)
			I2C/SPI selector (1: I2C mode; 0: SPI enabled)
	SCL/SPC		SPI CK line (SCL)
			I2C clock line (SPC)
			I2C serial data (SDA)
	SDI/SDA/SDO		SPI data in (SDI)
			SPI data out (SDO) -for 3-wire SPI mode
		SDO	I2C less significant bit of device address
			SPI data out (SDO) - for 4-wire SPI mode

4.1I2C bus interface

The LIS331DL I2C is a bus slave. The I2C is employed to write/read the data to/from the registers.

Relevant I2C terminology is provided in Table 3:

	Table 3.	Terminology
		Term	Description
	Transmitter		The device which sends data to the bus
	Receiver		The device which receives data from the bus
	Master		The device which initiates a transfer, generates clock signals and terminates
			a transfer
		Slave	The device addressed by the master

There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving data to/from the interface. Both lines are connected to Vdd_IO through a pull-up resistor embedded in the LIS331DL. When the bus is free, both the lines are high.

The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as normal mode.

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AN2960	Digital interfaces

4.1.1I2C operation

The transaction on the bus is started through a START (ST) condition, which is defined as a HIGH to LOW transition on the data line, while the SCL line is held HIGH. After the START condition has been generated by the master, the bus is considered busy. The next byte of data transmitted contains the address of the slave in the first 7 bits and the 8th bit instructs whether the master is receiving data from the slave or transmitting data to the slave (SAD subsequence). When an address is sent, each device in the system compares the first seven bits after a start condition with its own address. If they match, the device considers itself addressed by the master.

The slave address (SAD) associated with the LIS331DL may be selected from the two predefined values 0011100b or 0011101b depending on the logic level present on the SDO pin. Specifically, if the SDO pin is either connected to Vdd_IO or left unconnected, the slave address is 0011101b. Otherwise, when it is connected to GND, the slave address is 0011100b. When placing two sensors on the same bus is not required, it is recommended to use slave address 0011101b by either connecting the SDO pin to Vdd_IO, or leaving it floating.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver that has been addressed is obligated to generate an acknowledge after each byte of data has been received.

The I2C embedded in the LIS331DL behaves as a slave device and the following protocol must be adhered to. After the start condition (ST), a slave address is sent. Once a slave acknowledge (SAK) has been returned, an 8-bit sub-address will be transmitted: the 7 LSb represents the actual register address, while the MSB enables address auto-increment. If the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented to allow multiple data read/write. Otherwise, if the MSB of the SUB field is ‘0’, the SUB will remain unchanged and multiple read/write on the same address can be performed.

The slave address is completed with a read/write bit. If the bit is ‘1’ (read), a repeated START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master transmits to the slave with unchanged direction.

Transfer when master is writing one byte to slave

Master	ST	SAD + W		SUB		DATA		SP
Slave			SAK		SAK		SAK

Transfer when master is writing multiple bytes to slave:

Master	ST	SAD + W		SUB		DATA		DATA		SP
Slave			SAK		SAK		SAK		SAK

Transfer when master is receiving (reading) one byte of data from slave:

Master	ST	SAD + W		SUB		SR	SAD + R			NMAK	SP
Slave			SAK		SAK			SAK	DATA

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Digital interfaces

AN2960

Transfer when master is receiving (reading) multiple bytes of data from slave

Master

ST

SAD + W

SUB

SR

SAD + R

MAK

Slave

SAK

SAK

SAK

DATA

Master

MAK

NMAK

SP

Slave

DATA

DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the transmitter into a wait state. Data transfer continues only when the receiver is ready for another byte and releases the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing some other real-time function) the data line must be left high by the slave. The master can then abort the transfer. A low to high transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.

In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of the first register to read.

In the communication format presented, MAK signifies master acknowledge and NMAK is no master acknowledge.

4.1.2I2C subsequences

In order to better define subsequences and to clarify line SCL and SDA behavior, a description containing the discrete values of SCL and SDA follow. These simple subsequences are used to implement the complex commands described in the following paragraph.

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Doc ID 15557 Rev 1

AN2960

Digital interfaces

Figure 3.

I2C subsequences

ST: START condition

SCL

1111

SDA

1100

SR: Repeated START condition

SCL

1111

SDA

1100

SAD: Slave address (binary address: abcdefgh. In LIS331DL “abcdef” = “001110”)

SCL

00110

0110

0110

0110

0110

0110

0110

0110

SDA

0aaaa

bbbb

cccc

dddd

eeee

f f f f

gggg

hhhh

Bit g=0 if SDO connected to GND, g=1 if SDO pad connected to Vdd

Bit h=0 => write, h=1 => read

SAK: Slave acknowledge (Z means high impedance)

SCL

0011

SDA (force)

ZZZZ

Check that SDA is 0 after SCL=1

SDA (read)

XX00

SUB: Sub address (binary address: a0cdefgh)

SCL

00110

0110

0110

0110

0110

0110

0110

0110

SDA

0aaaa

0000

cccc

dddd

eeee

f f f f

gggg

hhhh

Bit a=0 => do not increment address in multiple mode

a=1 => increment address in multiple mode

DATA (Master): send DATA byte (binary number: abcdefgh)

SCL

00110

0110

0110

0110

0110

0110

0110

0110

S

aaaa

bbbb

cccc

dddd

eeee

f f f f

gggg

hhhh

DATA (Slave): read DATA byte (binary number: abcdefgh)

SCL

00110

0110

0110

0110

0110

0110

0110

0110

SDA (force)

ZZZZ

ZZZZ

ZZZZ

ZZZZ

ZZZZ

ZZZZ

ZZZZ

ZZZZ

SDA (read)

a

b

c

d

e

f

g

h

SP: STOP condition

SCL

1111

SDA

0011

MAK: Master Acknowledge

SCL

0011

SDA

0000

NMAK: No Master Acknowledge

SCL

0011

SDA

ZZZZ or 1111

Doc ID 15557 Rev 1

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