ST AN2898 Application note

AN2798

Application note

Complete DDR2/3 memory power supply controller based on the PM6670AS

Introduction

The PM6670AS device is a complete DDR2/3 power supply regulator for portable applications designed to meet JEDEC specifications. It integrates a constant on-time (COT) buck controller, a 2 A peak sink/source low dropout regulator and a 15 mA low-noise buffered reference.

The COT architecture assures fast transient response supporting both polymeric and ceramic output capacitors. An embedded integrator control loop compensates the DC voltage error due to the output ripple. The 2 A peak sink/source linear regulator provides the memory termination voltage with fast load transient response.

The device is fully compliant with system sleep states S3 and S4/S5, setting the LDO output to high impedance in suspend-to-RAM state and performing the tracking discharge of all outputs in suspend-to-disk state.

Figure 1. PM6670AS demonstration board

November 2008

Rev 1

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www.st.com

Contents	AN2798

Contents

1	Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
	1.1	Switching section (VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	1.2	Reference and termination voltages (VTTREF and VTT) . . . . . . . . . . . . .	5
2	Demonstration kit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
	2.1	Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
3	Component assembly and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
4	I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
	4.1	Recommended equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
5	Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13

5.1 JP3 fixed or adjustable output voltage (MODE pin) . . . . . . . . . . . . . . . . . 13 5.2 JP1 DDR2/DDR3 or power-saving mode (DDRSEL pin) . . . . . . . . . . . . . 13 5.3 JP2 output discharge (DSCG pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 JP5 compensation network (COMP pin) . . . . . . . . . . . . . . . . . . . . . . . . . 15

6	Test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
7	Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	7.1	Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	7.2	Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
8	PM6670AS evaluation tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
	8.1	VDDQ, VTT and VTTREF turn-on (soft-start) . . . . . . . . . . . . . . . . . . . . .	18
	8.2	VDDQ working modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19

8.2.1 VDDQ forced PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2.2 VDDQ pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2.3 VDDQ non-audible pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.3 VDDQ, VTT and VTTREF load regulation . . . . . . . . . . . . . . . . . . . . . . . . 20 8.4 VDDQ and VTT load transient responses . . . . . . . . . . . . . . . . . . . . . . . . 22 8.5 VDDQ efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.6 VDDQ gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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AN2798			Contents
	8.7	VDDQ, VTT and VTTREF turnoff (soft-end) . . . . . . . . . . . . . . . . .	. . . . . 24
	8.8	UV, OV and thermal protections . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 26
	8.9	VDDQ current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 28
	8.10	VTT current limit (foldback) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 30
	8.11	Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 31
	8.12	Thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 33
9	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 37

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List of figures	AN2798

List of figures

Figure 1.	PM6670AS demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 1
Figure 2.	PM6670AS demonstration board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
Figure 3.	Topside component placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 9
Figure 4.	Topside view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 9
Figure 5.	Layer 2 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
Figure 6.	Layer 3 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
Figure 7.	Bottomside view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
Figure 8.	Bottomside component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
Figure 9.	JP3 (MODE) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
Figure 10.	JP1 (DDRSEL) setting (change to “non-audible” in graphic) . . . . . . . . . . . . . . . . . . . . . . .	14
Figure 11.	JP2 (DSCG) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
Figure 12.	JP5 (COMP) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
Figure 13.	PM6670AS test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 14.	VDDQ soft-start at 180 mW load, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
Figure 15.	VTT turn-on (S0), pulse-skip mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
Figure 16.	VDDQ = 1.8 V, VIN = 24 V, IVDDQ = 0 A, forced PWM mode. . . . . . . . . . . . . . . . . . . . . .	19
Figure 17.	VDDQ = 1.8 V, VIN = 24 V, IVDDQ = 0 A, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . .	19
Figure 18.	VDDQ = 1.8 V, VIN = 24 V, no load, non-audible pulse-skip mode (33 kHz) . . . . . . . . . . .	20
Figure 19.	VDDQ load regulation - VIN = 24 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
Figure 20.	VTT load regulation - LDOIN = VDDQ (VDDQ in forced PWM mode) . . . . . . . . . . . . . . . .	21
Figure 21.	VTTREF load regulation (VDDQ in forced PWM mode). . . . . . . . . . . . . . . . . . . . . . . . . . .	21
Figure 22.	VDDQ load transient (VIN = 24 V, LOAD = 0 A to 8 A at 2.5 A/µs) (pulse-skip mode). . . .	22
Figure 23.	VTT load transient (VIN = 24 V, LOAD = – 2 A to 2 A at 2.5 A/µs) (pulse-skip mode) . . . .	22
Figure 24.	Forced PWM (blue), non-audible pulse-skip (green), pulse-skip (red) VDDQ efficiency vs. .
	output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
Figure 25.	External MOS gate signals (VIN = 24 V, LOAD = 0 A) (pulse-skip mode) . . . . . . . . . . . . .	23
Figure 26.	External MOS gate signals (VIN = 24 V, LOAD = 8 A) (pulse-skip mode) . . . . . . . . . . . . .	24
Figure 27.	VDDQ, VTTREF, VTT output voltages and LDO input current, tracking discharge,
	no load on any rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
Figure 28.	VDDQ, VTTREF and VTT, non-tracking discharge, no load on any output . . . . . . . . . . . .	25
Figure 29.	UV protection, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 30.	OV protection, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Figure 31.	VDDQ, VTT, VTTREF and inductor current, thermal shutdown, pulse-skip mode . . . . . . .	28
Figure 32.	VDDQ current limit protection during a load transient (0 A to 10 A at 2.5 A/µs) . . . . . . . . .	29
Figure 33.	VTT current limit during an output short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
Figure 34.	Switching frequency vs. input voltage, VDDQ = 1.8 V, IVDDQ = 4 A, forced PWM mode . 31
Figure 35.	Forced PWM (blue), non-audible pulse-skip (green) and pulse-skip (red), switching
	frequency vs. output current, VDDQ = 1.8 V, VIN = 24 V. . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 36.	IVTT = 0 A, average IC temperature = 37.5 °C, max internal IC temperature = 40.1 °C . .	33
Figure 37.	IVTT = 0.5 A, average IC temperature = 48.8 °C, max internal IC temperature = 54.3 °C. 34
Figure 38.	IVTT = 1 A, average IC temperature = 60.5 °C, max internal IC temperature = 72.7 °C . .	35
Figure 39.	IVTT = 1.5 A, average IC temperature = 73.8 °C, max internal IC temperature = 95.6 °C. 36

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AN2798	Main features

1 Main features

1.1Switching section (VDDQ)

■4.5 V to 36 V input voltage range

■0.9 V, ± 1 % voltage reference

■1.8 V (DDR2) or 1.5 V (DDR3) fixed output voltages

■0.9 V to 2.6 V adjustable output voltage

■1.237 V ± 1 % reference voltage available

■Very fast load transient response constant on-time loop control

■No-RSENSE current sensing using low-side MOSFETs' RDSON

■Negative current limit

■Latched OVP, UVP and thermal shutdown

■Fixed 3 ms soft-start

■Selectable pulse-skipping at light load

■Selectable non-audible (33 kHz) pulse-skip mode

■All ceramic output capacitor applications supported

■Output voltage ripple compensation

1.2Reference and termination voltages (VTTREF and VTT)

■2 A peak LDO with foldback for VTT

■Remote VTT output sensing

■High-Z VTT output in S3

■All ceramic output capacitor applications supported

■±15 mA low-noise buffered reference for VTTREF

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Demonstration kit schematic	AN2798

2 Demonstration kit schematic

Figure 2. PM6670AS demonstration board schematic

J1		VIN						J2			VDDQ																		J3	PGND	J4	PG
1									1			D3			STPS1L60A															1		1
												1				2
											C4			220u
												1			2
											C3			220u
												1			2
						R6 0
												6.8k						2		47n
			C2 10u					1u	2			R15						1		C15
						0
		1			2			L1				7.5k
									1											C18
		1			2	0						R14				R16	4R7				1n							GND TP					INT CER
			C1	10u																1		2					TP1					JP5
															D2			STPS1L60A
														1					2
						8						8																			0	2	680p
						7		3				7					3
						6		2				6					2	STS7NF60L														1	C16
						5		1				5					1
					Q1	STS5NF60L		2 4						4		Q2																	1		2
2	330k												0																				C17	0	0
1	R1						R4 3R3						R17
			100n					1
		C14									100n									VCC 100k							1			2
						0				C13											2		2
		1			2							0										100k						R13	100k
		1	18k		2	0				1 2										R11	1	R12	1				SW1
		R2																												2		0
																											3
																											4			1
																										C22	100p
																						C21	100p		2		1
																												0
								2	1k5													2		1
									R3	VCC													DSCG			JP2	6			5
				BAT41J									18	17	16	15	14	13									4			3
							100n																				2			1
			D1
VCC		2			1	1		2				CSNS	VCC LGATE PGND PG S3						S5	DSCG
						C12		1														12
						R10 0				19		PHASE					PM6670AS			COMP
										20												11
												HGATE								MODE
										21												10
												BOOT								VSNS										MODE
										22												9
												LDOIN								VOSC							JP3
										23												8
												VTT								VREF
	C11	10u								24			VTTGND VTTSNS DDRSEL VTTREF SGND									7
						0				U1		THPD							AVCC								R9 18k			R8 27k
	1		2									25	1	2 3 4 5 6																		0
								C20		10u
								1		2		0											1
								C19		10u
																						100n				C9
			R7	3R9				1		2										C10			2
VCC		1				2														1		2								DDRSEL		0
								C7		10u																JP1
								1		2		0															6			5
										10u
								C6
																											4			3
								1		2																	2			1
			C5 1u
						0
		1			2
																							C8	33n									0
																												0
																						1			2
	1				1		1	1												1										1		1
J5					J9	J6		J7											J8											J10		J11
	VCC				VCCGND		LDOIN	VTT												VTTREF										AGND		AGND
																																	AM00655v1

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AN2798	Demonstration kit schematic

2.1Component list

Table 1.		PM6670AS demonstration board bill of materials
Qty	Component		Description	Package	Part number	MFR	Value
2		C1, C2	Ceramic, 50 V, X5R, 20%	SMD 1210	UMK325BJ106KM-T	Taiyo Yuden	10 µ
2		C3, C4	POSCAP, 4 V, 15 m, 20%	SMD 7343 (D)	4TPE220MF	Sanyo	220 µ
1		C5	Ceramic, 6.3 V, X5R, 10%	SMD 3216-12		Standard	1 µ
3	C6, C7, C11		Ceramic, 6.3 V, X5R, 10%	SMD 0805	JMK212BJ106KG-T	Taiyo Yuden	10 µ
1		C8	Ceramic, 50 V,X7R, 20%	SMD 0603		Standard	33 n
4	C9, C10,		Ceramic, 50 V, X7R, 20%	SMD 0603		Standard	100 n
	C13, C14
1		C12	Ceramic, 50 V, X7R, 10%	SMD 0805		Standard	100 n
1		C15	Ceramic, 50 V, X7R, 10%	SMD 0603		Standard	6n8
1		C16	Ceramic, 50 V, X7R, 10%	SMD 0603		Standard	680 p
1		C17	Ceramic, 20%	SMD 0603		Standard	N.M.
1		C18	Ceramic, 50 V, X7R, 10%	SMD 0805		Standard	1 n
2	C19, C20		Ceramic, 6.3 V, X5R, 10%	SMD 0805	JMK212BJ106KG-T	Taiyo Yuden	N.M.
1		R1	Chip Resistor, 0.1 W, 1%	SMD 0603		Standard	330 k
1		R2	Chip Resistor, 0.1 W, 1%	SMD 0603		Standard	18 k
1		R3	Chip Resistor, 0.1 W, 1%	SMD 0603		Standard	1.5 k
1		R4	Chip Resistor, 0.1 W, 1%	SMD 0603		Standard	3R3
1		R6	Chip Resistor, 0.1 W, 1%	SMD 0805		Standard	0
1		R7	Chip Resistor, 0.1 W, 1%	SMD 0603		Standard	3R9
1		R8	Chip Resistor, 0.1 W, 1%	SMD 0603		Standard	39 k
1		R9	Chip Resistor, 0.1 W, 1%	SMD 0603		Standard	39 k
1		R10	Chip Resistor, 0.1 W, 1%	SMD 0603		Standard	0
3	R11, R12,		Chip Resistor, 0.1 W, 1%	SMD 0603		Standard	100 k
		R13
1		R14	Chip Resistor, 0.1 W, 1%	SMD 0805		Standard	7k5
1		R15	Chip Resistor, 0.1 W, 1%	SMD 0603		Standard	6k8
1		R16	Chip Resistor, 0.1 W, 1%	SMD 0805		Standard	4R7
1		R17	Chip Resistor, 0.1 W, 1%	SMD 0603		Standard	0
1		L1	SMT, 10.6 Arms, 4.36 mΩ	13.8 x 13.2 mm	MLC1538-152ML	Coilcraft	1.5 µ
1		Q1	N-Channel, 60 V	SO-8	STS7NF60L	ST
1		Q2	N-Channel, 60 V	SO-8	STS7NF60L	ST
1		D1	Schottky, 100 V, 0.2 A	SOD-323	BAT41J	ST
1		D2	Schottky, 60 V, 1 A	DO214-AC	STPS1L60A	ST
1		D3					N.M.
1		U1	Controller	VFQFPN-24	PM6670AS	ST

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Demonstration kit schematic							AN2798
Table 1.		PM6670AS demonstration board bill of materials (continued)
Qty	Component		Description	Package	Part number	MFR	Value
	J1, J2, J3,
11	J4, J5, J6,		Header, single pin
	J7, J8, J9,
		J10,J11
3	JP1, JP2,		Jumper, 2 x 3, 100 mils
		JP3
1		JP5	PCB pads selector
1		TP6	Test point
1		SW1	Dip switch 2	DIP-2		Standard

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AN2798	Component assembly and layout

3 Component assembly and layout

Figure 3. Topside component placement

Figure 4. Topside view

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Component assembly and layout	AN2798
Figure 5. Layer 2 view

Figure 6. Layer 3 view

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AN2798	Component assembly and layout
Figure 7.	Bottomside view

Figure 8. Bottomside component placement

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I/O interface		AN2798
4	I/O interface
	The PM6670AS demonstration board has the following test points as given in Table 2.
Table 2.	PM6670AS demonstration board input and output interface
Test point		Description
	VIN	Battery input voltage positive terminal
	PGND	Battery input and VDDQ output common return
	VDDQ	VDDQ output
	LDOIN	LDO linear regulator input
	VTT	VTT output (LDO)
	AGND	VTT and VTTREF outputs common return
	VTTREF	VTTREF output
	VCC	+ 5 V supply, positive terminal
	VCCGND	Signal ground and VCC supply return
	PG	VDDQ output Power Good signal
	TP1	Connection point between power and signal grounds

4.1Recommended equipment

4 V to 36 V, 30 W power supply

Active loads

Digital multimeters

200 MHz four-trace oscilloscope

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