This document describes the characteristics and performance of a 90 W wide range input
AC-DC adapter based on asymmetrical half-bridge topology (AHB).
The converter comprises a two-stage approach: a PFC fr ont-en d stage using the L6563 TM
PFC controller and a DC-DC stage that implements the asymmetrical half-bridge (AHB)
topology driven by the L6591, the new PWM controller dedicated to this architecture.
Thanks to the AHB topology, the system offers good electrical performance (EPA 2.0
compliant) with a low-voltage and high-current output (12 V - 7.5 A).
The order code for this de monstration board is EVL6591-90WADP.
The adapter implements a two-stage solution. The front-end PFC uses a boost topology
working in transition mode (TM). The IC used is the L6563, advanced TM PFC controller,
which integrates all the functions an d protection needed to control the stage and an
interface with the downstream DC-DC converter.
The power stage of the PFC comprises inductor L2, MOSFET Q1, diode D4 and capacitor
C9. The PFC circuit is quite standard and already well described in previous ST application
notes. Therefore this note will f ocus on the AHB stage and its controller, the L6591. This DCDC converter comprises a half-bridge (MOSFET Q3 and Q4) connected to the output
voltage of the PFC stage that driv es the se ries connection of a DC blocking capacitor (C44)
and the primary of the transformer (T1). The tran sf ormer has two secondary windings with a
center tap connection tied to ground. The other ends are connected to the output diodes
D12 and D13. The output inductor is betw ee n th e co mmo n cathod e of diod es D1 2 and D1 3
and the output. The L6591 includes a current mode PWM control ler (fixed-frequency
solution), gate drivers for both low and high-side MOSFETs with integrated bootstrap diode
and all the functions and protections tailored for this topology. The device is housed in an
SO-16 narrow package.
This adapter uses the magnetizing current and the output inductor current ripple to obtain
the correct primary current direction to achieve zero-voltage switching (ZVS) at turn-on of
both MOSFETs. The transformer construction is quite simple as it is a layer type with the
primary winding split in two parts (sandwich configuration) and two secondary windings.
The primary leakage inductance is about 3% of the magnetizing inductance. The h alf-bridge
is operated at fixed frequency with complementary duty cycles on the two MOSFETs. The
high-side FET is on during the D time and the low-side FET is on for the 1-D time. C44 is
calculated in order to have a resonance frequency due to Lm and C44 well below the
switching frequency (t hat, in this applicat ion, has bee n set at abou t 100 kHz). In this way the
voltage on C44 is nearly constant and equal to Vin x D where Vin is the high-voltage input
4/35
AN2852Main characteristics and circuit description
bus and D is the duty cycle. For stability reasons related to the topology, the IC limits the
maximum duty cycle at 50%. The current in the primary tank circuit is read by the controller
thanks to the sense resistors R81 and R82. The self supply is basically obtained thanks to
an auxiliary winding on the AHB transformer. A small charge pump on the auxiliary windings
of the PFC inductor helps during the startup phase. A pin dedicated to startup sequencing, a
spare latched protection (dedicated here to out put overvoltage protecti on), the soft-start
function, the overload protection, an interface with the PFC controller and the integrated
high-voltage startup generator complete the features of the L6591. All the functions and
protections are detailed in the following sections.
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Main characteristics and circuit descriptionAN2852
As mentioned before, this application note f ocuses on the AHB stage . This DC-DC conv erter
has the 400 V PFC bus as input and delivers 12 V at the output.
In Figure 3 the primary side key waveforms with full load applied are shown. Figure 4 shows
the detail of the two transition s during one s witching cycle. Wh en the LVG signal goes do wn,
the current is negative and so the half- bridge node (that has a certain capacitance value due
to the Coss of the MOSFETs and the stra y ca pacitance of the circuit) is cha rged up to 400 V.
After the deadtime has elapsed the high-side driver is turned on with zero volts across the
high-side MOSFET drain-source pins. The driver activation is visible on the HVG signal
when there is the small voltage step on the high part of the waveform.
When the high-side driver is turned off, the primary current is positive, so the half-bridge
node is discharged down to zero volts and the body diode of Q4 is activated. After the
deadtime the LVG turns on in ZVS condition.
Figure 3.AHB primary side key waveforms at full load
Ch1: LVG pin voltage (yellow)
Ch3: HVG pin voltage (purple)
Ch4: primary winding current (green)
Typically, in the AHB topology, the most critical transition is the one between LVG turn-off
and HVG turn-on. In f act it is visibl e that the current a v ailable to mov e the half-bridge point is
less with respect to the other transition. This is due to the magnetizing current that is not
symmetrical with an average value of zero amps but has a certain offset due to the
asymmetrical driving of the tank circuit.
The fast current variation during transitions is due to the reversal of the current direction in
the secondary windings. The effort in this design was to maintain a negative current after
AM01818v1
7/35
Operating waveformsAN2852
the positive variation at LVG turn-off. This was done by a correct design of the magnetizing
current, output inductor current ripple and choice of turns ratio.
Figure 4.Detailed AHB zero-voltage switching at full load
Ch1: LVG pin voltage (yellow)
Ch3: HVG pin voltage (purple)
Ch4: primary winding current (green)
AM01819v1
The ZVS condition is harder to meet as the load increases , so full load is the w orst condition
to have for a correct ZVS operation. In Figure 5 the same waveforms are shown with half
load. Since the output current is reduced, the fast primary side current variations are also
reduced and so the magnetizing current (that remains basically the same if the load
changes) becomes proportionally higher. The result is that there is more current available
for moving the half-bridge node.
8/35
AN2852Operating waveforms
Figure 5.Detailed AHB zero-voltage switching at half load
Ch1: LVG pin voltage (yellow)
Ch3: HVG pin voltage (purple)
Ch4: primary winding current (green)
AM01820v1
The key w av ef orms at the secondary side are shown in Figure 6. It is interesting to note that,
while the current is swapped between the two diodes, the voltage at their cathode is nearly
zero.
Figure 6.AHB secondary side key waveforms at full load
Ch1: D12 and D13 common cathode voltage (yellow)
Ch2: diode D12 current (blue)
Ch3: FGND pin voltage (purple)
Ch4: diode D13 current (green)
AM01821v1
9/35
Operating waveformsAN2852
Another peculiarity of this topology is that, since it is asymmetrical, the diode D13 has to
carry higher average and RMS current and sustain higher reverse voltage with respect to
diode D12. This implies that D13 dissipates a lot mor e t han D12 an d ma kes sense, in order
to improve efficiency and save money, to have a synchronous rectification only on D13.
2.2 Low-load operation
At light loads (and no-load) conditions the system enters a controlled burst mode operation,
allowing input power reduction. The burst mode is activated according to the COMP pin
level.
In Figure 7 and Figure 8 the burst mode operation with no load is shown. Under a certain
load also the PFC stage works in burst mode operat ion (sp ecifically t he PFC enters in b ur st
mode for a load value higher than the one for the AHB). Using the PFC_STOP pin of the
L6591 and the PFC_OK pin of the L6563, a simple interface is built in order to keep the
burst modes of the two ICs synchronized. This operation allows fast response to a heavy
load transition since the PFC is already on when the power is needed. This avoids output
voltage dips. The load transition from 0 to 100% and vice versa can be seen in Figure 9.
Ch3:PFC output voltage
Ch4: L6563 PFC_OK pin voltage (green)
AM01823v1
Figure 9.Load transitions
Ch2: output voltage (blue)
Ch4: output current (green)
AM01824v1
11/35
Operating waveformsAN2852
2.3 Short-circuit protection
A short-circuit at the output activates the overload protection (OLP). Figure 10 shows the
pins involved in this function. When the short-circuit is applied, the COMP pin saturates
high. The IC detects this condition and starts charging the SS capacitor. When the SS
voltage reaches 5 V, the system shuts down. Diode D29 allows the SS voltage to be
clamped at about 5.4 V and the protection has an auto-restart behavior. If the short circuit is
not removed, the IC enters the HICCUP mode (Figure 11). When the IC is stopped by the
OLP, the high-voltage startup generator is invoked only when Vcc falls to 5 V (V
CCrestart
Thanks to this approach, the period between tw o restart trials is quite long which reduces
the stress on power components.
Figure 10. Detailed short-circuit behavior
).
Ch1: SS pin voltage (yellow)
Ch2: COMP pin voltage (blue)
Ch3: FGND pin voltage (purple)
Ch4: PFC_STOP pin voltage (green)
12/35
AM01825v1
AN2852Operating waveforms
Figure 11. HICCUP mode
Ch1: SS pin voltage (yellow)
Ch2: COMP pin voltage (blue)
Ch3: FGND pin voltage (purple)
Ch4: PFC_STOP pin voltage (green)
AM01826v1
2.4 Overvoltage protection
Since it is impossible to sense the output v oltage fr om the primary side in all load conditions,
the OVP senses such voltage directly on the output. A Zener diode (D25 ) is used as the
threshold to activate the protection. The information is passed to the controller using
optocoupler U5 that increases the di sable pin voltage over the intervention threshold of
4.5 V. In Figure 12 a loop failure is simulated by shorting R93. The overvoltage protection is
invoked and the output voltage reache s a maximum voltage of 14.8 V.
Since this protection uses the disab le pin, it is la tched. Hence, after PWM is stop ped, the HV
generator is invoked to keep Vcc voltage between 14 V and 13.5 V. Diode D27 brings the
PFC_OK pin voltage over 2.5 V, so the L6563 is also shut down and its consumption goes
almost to the startup level. The PWM_LATCH goes high which also keeps the disable pin
high. The latched operation is shown in Figure 13.
13/35
Operating waveformsAN2852
Figure 12. Detailed OVP intervention
Ch1: output voltage (yellow)
Ch2: Vcc pin voltage (blue)
Ch3: FGND pin voltage (purple)
Ch4: DISABLE pin voltage (green)
AM01827v1
Figure 13. OVP intervention: system is latched
Ch2: Vcc pin voltage (blue)
Ch4: DISABLE pin voltage (green)
AM01828v1
14/35
AN2852Operating waveforms
2.5 Startup sequence
In this converter the startup sequence is quite particular and merits a detailed explanation.
When the mains is plugged in, the rectified input voltage is present on bulk capacitor C9.
Since this value is greater than 80 V , the HV sta rtup generator of the L6591 is turned on and
Vcc capacitors are charged with a constant current of about 0.75 mA. This charge time is
therefore independent of input voltage level. The L6563 has a turn-on threshold lower than
that of L6591, so the PFC controller starts first. The HV startup current is insufficient to
power the L6563, so a small charge pump (R70, C40, D21 and D22) is connected to the
PFC inductor auxiliary winding. With this circuit, when the L6563 starts, both Vcc voltage
and PFC output voltage increase.
Once Vcc > 14 V and line pin voltage is greater than 1.25 V , the L6591 also turns on. At this
point the charge pump is insufficient to sustain Vcc current of both ICs and so an auxiliary
winding on the AHB transformer is used to provide, together with the charge pump, the
power requested by the devices. The complete sequence is shown in Figure 14, while the
details of the turn-on of both ICs ar e sh own in Figure 15. Both figures show the startup at
115V ac mains inpu t. The startup at 230Vac is very similar, the only difference is that the Vcc
voltage during steady state operation is a little higher since the charge pump delivers more
current.
Figure 14. Complete startup sequen ce at 115Vac and full load
Ch1: LVG voltage (yellow)
Ch2: Vcc pin voltage (blue)
Ch3: PFC output voltage (purple)
Ch4: output voltage (green)
AM01829v1
15/35
Operating waveformsAN2852
Figure 15. Detailed startup sequence at 115Vac and full load
Ch1: LVG voltage (yellow)
Ch2: Vcc pin voltage (blue)
Ch3: PFC output voltage (purple)
Ch4: output voltage (green)
AM01830v1
16/35
AN2852Electrical performance
3 Electrical performance
3.1 Efficiency measurement and no-load consumption
Table 1 and 2 give the efficiency measurements taken at the two nominal voltages.
Measurements @ 100Vac 75W in JEIDA-MITI class D limits
3.2 Harmonic content measurement
The front-end PFC stage provides the reduction of the mains harmonic, allowing meeting
European EN61000-3-2 and Japanese JEIDA-MITI standards for class D equipment.
Figure 18 and 19 show the harmonic contents of the mains current at full load.
A measure has been done also with 75 W input power which is the lower limit for using
harmonic reduction techniques.
To evaluate the performance of the PFC stage also, the PF and THD vs. input voltage
graphs are shown in Figure 22 and 23 at full load and 75 W input power.
Figure 22. PF vs. input voltage
AM01837v1
Figure 23. THD vs. input voltage
80120160200240280
AM01838v1
21/35
Thermal measurementsAN2852
4 Thermal measurements
A thermal analysis of the board was performed using an IR camera, refer to Figure 24 and
Figure 26 and 27 show the conducted noise measurements performed at the two nominal
voltages with peak detect ion and considering only the w or st phase. Both measures are well
below the average limit (taken from EN55022 CLASS B norm).
Figure 26. CE peak measure at 115Vac and full load
Figure 27. CE peak measure at 230Vac and full load
U2L6591PWM controller for ZVS half-bridgeSTMicroelectronics
U3PC817Optocoupler - PC817X1J000FSharp
U4TS3431AILTSMD voltage reference - 1%STMicroelectronics
ΩSMD film resistor - 1% - 100 ppm/°C - 0805Vishay
U5PC817Optocoupler - PC817X1J000FSharp
28/35
AN2852PFC coil specifications
8
10
7 PFC coil specifications
●Application type: consumer, IT
●Transformer type: open
●Coil former: vertical type, 6+6 pins
●Max. temp. rise: 45°C
●Max. operating ambient temp.: 60°C
●Mains insulation: N.A.
7.1 Electrical characteristics
●Converter topology: boost, transition mode
●Core type: RM14 - N87 or equivalent
●Min. operating frequency: 20 kHz
●Primary inductance: 700 µH 10% at 1 kHz - 0.25 V (see Note 1)
●Peak primary current: 3.5 A
●
RMS primary curre n t: 1. 25 A
Note:1measured between pins 3-5
pk
RMS
.
Figure 28. Electrical diagram
3
AUXPRIM
5
Table 9.Winding characteristics
PinsWindingRMS currentNr. of turnsWire type
3 – 5Primary1.25 A
8 – 10AUX
1. Auxiliary winding is wound on top of primary winding
(1)
0.05 A
RMS
RMS
53Stranded 7 x Ø 0.28 mm – G2
4 spacedØ 0.28 mm – G2
AM01843v1
29/35
PFC coil specificationsAN2852
7.2 Mechanical aspect and pin numbering
●Maximum height from PCB: 22 mm
●Coil former type: vertical, 6+6 pins
●Pin distance: 5.08 mm
●Row distance: 35.56 mm
●Pins removed: # 1, 4, 6, 7, 9, 11, 12
●External copper shield: bare, wound around the ferrite core including the windings a nd
coil former. Height is 7 mm. Connected by a solid wire soldered to pin 10
●Manufacturer: Magnetica
●P/N: 1825.0001.
Figure 29. Bottom view
6
1
7
12
AM01844v1
30/35
AN2852AHB transformer specifications
8 AHB transformer specifications
●Application type: consumer, IT
●Transformer type: open
●Coil former: horizontal type, 7+7 pins
●Max. temp. rise: 45°C
●Max. operating ambient temp.: 60°C
●Mains insulation: compliance with EN60950.
8.1 Electrical characteristics
●Converter topology: asymmetrical half-bridge
●Core type: ETD34 - N87 or equivalent
●Operating frequency: 100 kHz
●Primary inductance: 400 µH 10% at 1 kHz - 0.25 V (see Note 1)
●Air gap: 2.32 mm on central leg
●Leakage inductance: 10 µH max. at 100 kHz - 0.25 V (see Note 2)
●Primary capacitance: 6 pF typ. (see Note 3)
●Max. peak primary current: 1.93 A
●
RMS primary curre n t: 0. 75 A
Note:1measured between pins 2-4
2measured between pins 2-4 with secondaries and auxiliary windings shorted
3calculated considering primary inductance and resonance frequency
pk
RMS
Figure 30. Electrical diagram
PRIM.
AUX
2
4
5
6
9
10
12
14
SEC.
SEC.
AM01845v1
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AHB transformer specificationsAN2852
Table 10.Winding characteristics
PinsWindingRMS currentNr. of turnsWire type
2 – 3Primary A0.75 A
9 – 10Secondary 13.81 A
12 – 14Secondary 26.57 A
3 – 4Primary B0.75 A
5 – 6Auxiliary0.0 5 A
Note:Primaries A and B are in series
Cover wires ends with silicon sleeve
Figure 31. Windings position
3mm
COIL FORMER
RMS
RMS
RMS
RMS
RMS
AUX
PRIMARY - B
SECONDARY 2
SECONDARY 1
PRIMARY - A
35Ø 0.355 mm – G2
4Stranded 90 x Ø 0.1 mm – G1
7Stranded 135 x Ø 0.1 mm – G1
35Ø 0.355 mm – G2
3 spacedØ 0.355 mm – G2
3mm
INSULATING
TAPE
AM01846v1
8.2 Mechanical aspect and pin numbering
●Maximum height from PCB: 30 mm
●Coil former type: vertical, low profile, 7+7 pins, NORWE ETD34lr/h14/-1/rtg
●Pin distance: 5.08 mm
●Row distance: 25.4 mm
●Pin removed: # 7
●Manufacturer: Magnetica
●P/N: 1754.0004
Figure 32. Top view
1
7
14
8
AM01847v1
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AN2852PCB layout
9 PCB layout
Figure 33. Topside silk screen
AM01848v1
Figure 34. Bottomside silk screen
Figure 35. Copper traces (bottomside)
AM01849v1
AM01850v1
33/35
Revision historyAN2852
10 Revision history
Table 11.Document revision history
DateRevisionChanges
28-Jan-20091Initial release
34/35
AN2852
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