ST AN2852 APPLICATION NOTE

AN2852

Application note

EVL6591-90WADP: 90 W AC-DC asymmetrical

half-bridge adapter using L6591 and L6563

Introduction

This document describes the characteristics and performance of a 90 W wide range input
AC-DC adapter based on asymmetrical half-bridge topology (AHB).

The converter comprises a two-stage approach: a PFC fr ont-en d stage using the L6563 TM
PFC controller and a DC-DC stage that implements the asymmetrical half-bridge (AHB)
topology driven by the L6591, the new PWM controller dedicated to this architecture.

Thanks to the AHB topology, the system offers good electrical performance (EPA 2.0
compliant) with a low-voltage and high-current output (12 V - 7.5 A).

The order code for this de monstration board is EVL6591-90WADP.

Figure 1. EVL6591-90WADP demonstration board

AM01816v1

January 2009 Rev 1 1/35

www.st.com

Contents AN2852

Contents

1 Main characteristics and circuit description . . . . . . . . . . . . . . . . . . . . . 4

2 Operating waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Asymmetrical half-bridge (AHB) typical waveforms . . . . . . . . . . . . . . . . . . 7

2.2 Low-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Efficiency measurement and no-load consumption . . . . . . . . . . . . . . . . . 17

3.2 Harmonic content measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 Thermal measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 Conducted noise measurements (pre-compliance test) . . . . . . . . . . . 24

6 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7 PFC coil specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.2 Mechanical aspect and pin numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8 AHB transformer specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.2 Mechanical aspect and pin numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2/35

AN2852 List of figures

List of figures

Figure 1. EVL6591-90WADP demonstration board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. EVL6591-90WADP schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. AHB primary side key waveforms at full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Detailed AHB zero-voltage switching at full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. Detailed AHB zero-voltage switching at half load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6. AHB secondary side key waveforms at full load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. Burst mode at no load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 8. Detailed burst mode at no load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 9. Load transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 10. Detailed short-circuit behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 11. HICCUP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 12. Detailed OVP intervention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 13. OVP intervention: system is latched. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 14. Complete startup sequence at 115Vac and full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 15. Detailed startup sequence at 115Vac and full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 16. Efficiency vs. O/P power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 17. No-load consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 18. EN61000-3-2 measurements at full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 19. JEIDA-MITI measurements at full load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 20. EN61000-3-2 measurements at 75 W input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 21. JEIDA-MITI measurements at 75 W input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 22. PF vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 23. THD vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 24. Thermal map at 115Vac - full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 25. Thermal map at 230Vac - full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 26. CE peak measure at 115Vac and full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 27. CE peak measure at 230Vac and full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 28. Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 29. Bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 30. Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 31. Windings position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 32. Top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 33. Topside silk screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 34. Bottomside silk screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 35. Copper traces (bottomside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3/35

Main characteristics and circuit description AN2852

1 Main characteristics and circuit description

The main characteristics of the SMPS adapter are as follows:

● Input mains range

–Vin: 88 ~ 264 Vrms
– f: 45 ~ 66 Hz

● Output: 12Vdc ± 2% - 7.5 A

● No-load: Pin below 0.35 W

● Protections

– Short-circuit
–Overload
– Ouput overvoltage
– Brownout

● PCB type and size

–CEM-1
– Single-side 70 µm
– 174 x 78 mm

● Safety: according to EN60065

● EMI: according to EN50022 - class B

The adapter implements a two-stage solution. The front-end PFC uses a boost topology
working in transition mode (TM). The IC used is the L6563, advanced TM PFC controller,
which integrates all the functions an d protection needed to control the stage and an
interface with the downstream DC-DC converter.

The power stage of the PFC comprises inductor L2, MOSFET Q1, diode D4 and capacitor
C9. The PFC circuit is quite standard and already well described in previous ST application
notes. Therefore this note will f ocus on the AHB stage and its controller, the L6591. This DC­DC converter comprises a half-bridge (MOSFET Q3 and Q4) connected to the output
voltage of the PFC stage that driv es the se ries connection of a DC blocking capacitor (C44)
and the primary of the transformer (T1). The tran sf ormer has two secondary windings with a
center tap connection tied to ground. The other ends are connected to the output diodes
D12 and D13. The output inductor is betw ee n th e co mmo n cathod e of diod es D1 2 and D1 3
and the output. The L6591 includes a current mode PWM control ler (fixed-frequency
solution), gate drivers for both low and high-side MOSFETs with integrated bootstrap diode
and all the functions and protections tailored for this topology. The device is housed in an
SO-16 narrow package.

This adapter uses the magnetizing current and the output inductor current ripple to obtain
the correct primary current direction to achieve zero-voltage switching (ZVS) at turn-on of
both MOSFETs. The transformer construction is quite simple as it is a layer type with the
primary winding split in two parts (sandwich configuration) and two secondary windings.
The primary leakage inductance is about 3% of the magnetizing inductance. The h alf-bridge
is operated at fixed frequency with complementary duty cycles on the two MOSFETs. The
high-side FET is on during the D time and the low-side FET is on for the 1-D time. C44 is
calculated in order to have a resonance frequency due to Lm and C44 well below the
switching frequency (t hat, in this applicat ion, has bee n set at abou t 100 kHz). In this way the
voltage on C44 is nearly constant and equal to Vin x D where Vin is the high-voltage input

4/35

AN2852 Main characteristics and circuit description

bus and D is the duty cycle. For stability reasons related to the topology, the IC limits the
maximum duty cycle at 50%. The current in the primary tank circuit is read by the controller
thanks to the sense resistors R81 and R82. The self supply is basically obtained thanks to
an auxiliary winding on the AHB transformer. A small charge pump on the auxiliary windings
of the PFC inductor helps during the startup phase. A pin dedicated to startup sequencing, a
spare latched protection (dedicated here to out put overvoltage protecti on), the soft-start
function, the overload protection, an interface with the PFC controller and the integrated
high-voltage startup generator complete the features of the L6591. All the functions and
protections are detailed in the following sections.

5/35

Main characteristics and circuit description AN2852

Figure 2. EVL6591-90WADP schematic

R30

J2

1

2

Output connector

12V-7.5A

C56

100NF

R97

N.M.

C46

25V

1000uF

+

L3

3.3uH

D12

STPS16L40CT

C58

1N8

9

R94

C21

C20

2N2

2N2

12R

T1

AHB Trafo

2

+

+

C62

N.M.

N.M.

C61

JP9

N.M.

10

12

4

5

C59

470PF

D13

STPS30100ST

14

R95

47R

6

R29

100K

BZV55-B11

D28

BZV55-B13

U5A

PC817

12

D25

R87

N.M.

R86

33K

C53

N.M.

R85

220K

R88

2K2

R83

6K8

12

U3A

2K2

BC847C

2 3

1 Q11

Q10

BC847C

2 3

R24

1.8K

1

R25

4.7K

R96

470

C55

N.M.

R93

3K3

C54

1uF

1

R91

U4

75K

TS3431

3 2

PC817

D3

1N4005

D1

F1

T4A

J1

R11

R7

2R5

R6

D4

STTH2L 06

L2

GBU6J

-+

C4

470NF

L1

86A-5163

4 8

1 5

C2

2N2

C1

470nF

1

2

3

Input connector

STP12NM50FP

C44

220NF

250V

Q3

R53

3M0

680K

+

C9

47uF

10 3

8 5

700uH

C5

470NF

400V

C3

2N2

88 - 264Vac

0R0

R12

3M0

680K

R8

450V

R70

33R

R13

8.2K

R28

24K9

10R

R72

D23

100NF

C14

LL4148

16

HVSTAR T

U2

L6591

LINE1DIS2ISEN3SS4OSC

R71

10R

C41

4N7

D27

LL4148

R19

56K

R100

0R0

14

VCC

INV

U1

1

R18

56K

C13

1uF

C42

100NF

15

BOOT

13

GD

COMP

2

R10

15K

R3

680K

R9

82K

C17

N.M.

D21

+

1N4148

D22

C40

10NF

LL4148

R98

220K

+

C15

22uF

0R0

R54

100NF

C39

R1

1M0

R2

R55

1M2

0R0

Q4

R73

100K

STP12N M50FP

R74

R75

14

HVG

C45 220PF

12

GND

MULT3CS4VFF5TBO6PFC_OK

10R

56R

D24

LL4148

11

12

13

N.C.

GND

FGND

VREF

6

5

C43 10NF

R78 19K6

LL4148
D29

2.2NF

U5B

C47

PC817

STP12NM50FP

Q1

R46

100K

R21

27R

10

11

9

ZCD

RUN

PWM_STOP

R15

C11

10NF

R14

18K

4

3

150K

10

LVG

COMP7PFC_STOP

8

PWM_LATCH

7

R82

0R82

R81

0R82

R79

100K

R77

56R

C51

22uF

+

C50

100NF

9

Vcc

8

C52

100NF

C48

6.8NF

C49

330PF

R23

0R47

R22

0R47

R20

0R0

C16

1N0

R80

1K0

R27

470

L6563

R26

240K

C12

470NF

R17

0R0

D26

R90

0R0

R84

220R

U3B

PC817

43

R99

15K

C10

1N0

C22

220PF

C57

STPS1L60A

R89

100uF

+

R69

N.M.

1

2 3

D20

N.M.

NM

Q9

R101

0R0

100K

AM01817v1

6/35

AN2852 Operating waveforms

2 Operating waveforms

2.1 Asymmetrical half-bridge (AHB) typical waveforms

As mentioned before, this application note f ocuses on the AHB stage . This DC-DC conv erter
has the 400 V PFC bus as input and delivers 12 V at the output.

In Figure 3 the primary side key waveforms with full load applied are shown. Figure 4 shows
the detail of the two transition s during one s witching cycle. Wh en the LVG signal goes do wn,
the current is negative and so the half- bridge node (that has a certain capacitance value due
to the Coss of the MOSFETs and the stra y ca pacitance of the circuit) is cha rged up to 400 V.
After the deadtime has elapsed the high-side driver is turned on with zero volts across the
high-side MOSFET drain-source pins. The driver activation is visible on the HVG signal
when there is the small voltage step on the high part of the waveform.

When the high-side driver is turned off, the primary current is positive, so the half-bridge
node is discharged down to zero volts and the body diode of Q4 is activated. After the
deadtime the LVG turns on in ZVS condition.

Figure 3. AHB primary side key waveforms at full load

Ch1: LVG pin voltage (yellow)

Ch3: HVG pin voltage (purple)

Ch4: primary winding current (green)

Typically, in the AHB topology, the most critical transition is the one between LVG turn-off
and HVG turn-on. In f act it is visibl e that the current a v ailable to mov e the half-bridge point is
less with respect to the other transition. This is due to the magnetizing current that is not
symmetrical with an average value of zero amps but has a certain offset due to the
asymmetrical driving of the tank circuit.

The fast current variation during transitions is due to the reversal of the current direction in
the secondary windings. The effort in this design was to maintain a negative current after

AM01818v1

7/35

Operating waveforms AN2852

the positive variation at LVG turn-off. This was done by a correct design of the magnetizing
current, output inductor current ripple and choice of turns ratio.

Figure 4. Detailed AHB zero-voltage switching at full load

Ch1: LVG pin voltage (yellow)

Ch3: HVG pin voltage (purple)

Ch4: primary winding current (green)

AM01819v1

The ZVS condition is harder to meet as the load increases , so full load is the w orst condition
to have for a correct ZVS operation. In Figure 5 the same waveforms are shown with half
load. Since the output current is reduced, the fast primary side current variations are also
reduced and so the magnetizing current (that remains basically the same if the load
changes) becomes proportionally higher. The result is that there is more current available
for moving the half-bridge node.

8/35

AN2852 Operating waveforms

Figure 5. Detailed AHB zero-voltage switching at half load

Ch1: LVG pin voltage (yellow)
Ch3: HVG pin voltage (purple)

Ch4: primary winding current (green)

AM01820v1

The key w av ef orms at the secondary side are shown in Figure 6. It is interesting to note that,
while the current is swapped between the two diodes, the voltage at their cathode is nearly
zero.

Figure 6. AHB secondary side key waveforms at full load

Ch1: D12 and D13 common cathode voltage (yellow)
Ch2: diode D12 current (blue)

Ch3: FGND pin voltage (purple)

Ch4: diode D13 current (green)

AM01821v1

9/35

Operating waveforms AN2852

Another peculiarity of this topology is that, since it is asymmetrical, the diode D13 has to
carry higher average and RMS current and sustain higher reverse voltage with respect to
diode D12. This implies that D13 dissipates a lot mor e t han D12 an d ma kes sense, in order
to improve efficiency and save money, to have a synchronous rectification only on D13.

2.2 Low-load operation

At light loads (and no-load) conditions the system enters a controlled burst mode operation,
allowing input power reduction. The burst mode is activated according to the COMP pin
level.

In Figure 7 and Figure 8 the burst mode operation with no load is shown. Under a certain
load also the PFC stage works in burst mode operat ion (sp ecifically t he PFC enters in b ur st
mode for a load value higher than the one for the AHB). Using the PFC_STOP pin of the
L6591 and the PFC_OK pin of the L6563, a simple interface is built in order to keep the
burst modes of the two ICs synchronized. This operation allows fast response to a heavy
load transition since the PFC is already on when the power is needed. This avoids output
voltage dips. The load transition from 0 to 100% and vice versa can be seen in Figure 9.

Figure 7. Burst mode at no load

Ch1: LVG pin voltage (yellow)
Ch2: Q1 (PFC MOSFET) gate (blue)

Ch3:PFC output voltage
Ch4: COMP pin voltage (green)

10/35

AM01822v1

AN2852 Operating waveforms

Figure 8. Detailed burst mode at no load

Ch1: LVG pin voltage (yellow)
Ch2: Q1 (PFC MOSFET) gate (blue)

Ch3:PFC output voltage
Ch4: L6563 PFC_OK pin voltage (green)

AM01823v1

Figure 9. Load transitions

Ch2: output voltage (blue)
Ch4: output current (green)

AM01824v1

11/35