ST AN2847 Application note

AN2847

Application note

LIS331DLH: ±2 g /±4 g /±8 g digital output

high performance ultra low-power 3-axis accelerometer

Introduction

This document provides application information for the low-voltage 3-axis digital output
linear MEMS accelerometer provided in the LGA package.

The LIS331DLH is a high performance ultra low-power 3-axis linear accelerometer, which
belongs to the “nano” family of MEMS accelerometers, with digital I
standard output.

The device features ultra low-power operational modes that allow advanced power saving
and smart Sleep to Wakeup functions.

The LIS331DLH has dynamically user-selectable full scales of ±2 g /±4 g /±8 g and is
capable of measuring acceleration with output data rates from 0.5 Hz to 1 kHz.

The self-test capability allows the user to check the functioning of the sensor in the final
application.

The device can be configured to generate interrupt signals in response to inertial wake­up/free-fall events, or based on the position of the device itself.

The thresholds and timing of interrupt generators are programmable by the end user while
fully operational. The LIS331DLH is available in a small, thin plastic land grid array (LGA)
package, and is guaranteed to operate over a wide temperature range of -40 °C to +85 °C.

2

C/SPI serial interface

September 2010 Doc ID 15136 Rev 2 1/31

www.st.com

Contents AN2847

Contents

1 Register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Reading acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.1 Using the status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.2 Using the data-ready signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.3 Using the block data update feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Output data rate selection and reading timing . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Data ready vs. interrupt signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Understanding acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4.1 Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4.2 Big-little endian selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4.3 Example of acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Sleep to wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4.1 Entering the sleep to wake mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4.2 Exiting the sleep to wake mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 High pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 Filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1.2 Reference mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2 Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.3 Free-fall and wake-up interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.4 Inertial wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4.1 HP filter bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2/31 Doc ID 15136 Rev 2

AN2847 Contents

5.4.2 Using the HP filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.5 Free-fall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.6 6D direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Doc ID 15136 Rev 2 3/31

List of tables AN2847

List of tables

Table 1. Register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Output data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Timing value to prevent data loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Data signal on INT 1 and INT 2 pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Output data register content vs. acceleration (FS = 2 g) . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. CTRL_REG1 - data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. CTRL_REG5 - sleep to wake configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Power consumption - normal mode (µA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. Power consumption - low power mode (µA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 11. Turn on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. High-pass filter cut-off frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 14. Reference mode LSB value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 15. Interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 16. Duration LSB value in normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 17. Duration LSB value in low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 18. Threshold LSB value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 19. INTx_SRC register in 6D position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4/31 Doc ID 15136 Rev 2

AN2847 List of figures

List of figures

Figure 1. Reading timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2. Interrupt and DataReady signal generation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. Data-ready signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Sleep to wake mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. High pass filter connections block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. HP_FILTER_RESET readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Reference mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Free-fall, wake-up interrupt generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9. FF_WU_CFG high and low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. Inertial wake-up interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Free-fall interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12. ZH, ZL, YH, YL, XH, XL behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13. 6D movement vs. 6D position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14. 6D recognized positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Doc ID 15136 Rev 2 5/31

Register table AN2847

1 Register table

Table 1. Register table

Register name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

WHO_AM_I 0Fh 0 0 1 1 0 0 1 0

CTRL_REG1 20h PM2 PM1 PM0 DR1 DR0 Zen Yen Xen

CTRL_REG2 21h BOOT HPM1 HPM0 FDS HPen2 HPen1 HPCF1 HPCF0

CTRL_REG3 22h IHL PP_OD LIR2 I2_CF1 I2_CF0 LIR1 I1_CF1 I1_CF0

CTRL_REG4 23h BDU BLE FS1 FS0 STsign 0 ST SIM

CTRL_REG5 24h - - - - - - TurnOn1 TurnOn0

HP_FILTER_RESET 25h - - - - - - - -

REFERENCE 26h REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0

STATUS_REG 27h ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA

OUTX_L 28h XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0

OUTX_H 29h XD15 XD14 XD13 XD12 XD11 XD10 XD9 XD8

OUTY_L 2Ah YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0

OUTY_H 2Bh YD15 YD14 YD13 YD12 YD11 YD10 YD9 YD8

OUTZ_L 2Ch ZD7 ZD6 ZD5 ZD4 ZD3 ZD2 ZD1 ZD0

OUTZ_H 2Dh ZD15 ZD14 ZD13 ZD12 ZD11 ZD10 ZD9 ZD8

INT1_CFG 30h AOI 6D ZHIE ZLIE YHIE YLIE XHIE XLIE

INT1_SRC 31h - IA ZH ZL YH YL XH XL

INT1_THS 32h 0 THS6 THS5 THS4 THS3 THS2 THS1 THS0

INT1_DURATION 33h 0 D6 D5 D4 D3 D2 D1 D0

INT2_CFG 34h AOI 6D ZHIE ZLIE YHIE YLIE XHIE XLIE

INT2_SRC 35h - IA ZH ZL YH YL XH XL

INT2_THS 36h 0 THS6 THS5 THS4 THS3 THS2 THS1 THS0

INT2_DURATION 37h 0 D6 D5 D4 D3 D2 D1 D0

6/31 Doc ID 15136 Rev 2

AN2847 Start-up sequence

2 Start-up sequence

Once the device is powered up it automatically downloads the calibration coefficients from
the embedded Flash memory to the internal registers. When the boot procedure is complete
(i.e. after about 5 milliseconds), the device automatically enters power-down mode.

To turn on the device and gather acceleration data, it is necessary to select one of the
operating modes through the CTRL_REG1 register, and to enable at least one of the axes.
The following general-purpose sequence can be used to configure the device:

1. write CTRL_REG1

2. write CTRL_REG2

3. write CTRL_REG3

4. write CTRL_REG4

5. write Reference

6. write INT1_THS

7. write INT1_DUR

8. write INT2_THS

9. write INT2_DUR

10. read HP_FILTER_RESET (if filter is enabled)

11. write INT1_CFG

12. write INT2_CFG

13. write CTRL_REG5

Register values can be changed at any time, and with the device in any operating mode.
Modifications take effect immediately.

Note that in case of changes in full scale, ODR or enabling/disabling of self-test, the output
of the device will require 1 ms + 1/ODR to settle (see Table 11). If the HP filter cut-off
frequency is changed, the filter can be reset by reading the HP_FILTER_RESET register.

Doc ID 15136 Rev 2 7/31

Start-up sequence AN2847

2.1 Reading acceleration data

2.1.1 Using the status register

The device features a STATUS_REG register which should be polled to check when a new
set of data is available. The reading procedure is the following:

1 read STATUS_REG

2 if STATUS_REG(3) = 0 then goto 1

3 if STATUS_REG(7) = 1 then some data have been overwritten

4 read OUTX_L

5 read OUTX_H

6 read OUTY_L

7 read OUTY_H

8 read OUTZ_L

9 read OUTZ_H

10 data processing

11 goto 1

The check performed at step 3 determines whether the reading rate is adequate compared
to the data production rate. In cases where one or more acceleration samples have been
overwritten by new data due to an excessively slow reading rate, the ZYXOR bit of the
STATUS_REG register is set to 1.

The overrun bits are automatically cleared when all the data present inside the device have
been read and new data have not been produced in the meantime.

2.1.2 Using the data-ready signal

The device may be configured to have one HW signal to determine when a new set of
measurement data is available for reading. This signal is represented by the XYZDA bit of
the STATUS_REG register. The signal can be driven to the INT1 or INT2 pins and its polarity
set to active-low or active-high through the CTRL_REG3 register. The interrupt is reset
when the higher part of the data of all the enabled channels has been read.

2.1.3 Using the block data update feature

If the reading of the acceleration data is particularly slow and cannot be (or does not need to
be) synchronized with either the XYZDA bit within the STATUS_REG or with the RDY signal,
it is strongly recommended to set the BDU (block data update) bit in CTRL_REG4 to 1.

This feature prevents the need to read the values (most significant and least significant parts
of the acceleration data) related to different samples. In particular, when the BDU is
activated, the data registers related to each channel always contain the most recent
acceleration data produced by the device. But if the reading of a given pair (i.e. OUTX_H
and OUTX_L, OUTY_H and OUTY_L, OUTZ_H and OUTZ_L) is initiated, the refresh for
that pair is blocked until both the MSB and LSB parts of the data are read.

8/31 Doc ID 15136 Rev 2

AN2847 Start-up sequence

Note: BDU only guarantees that OUTX(Y, Z)_L and OUTX(X,Z)_H have been sampled at the

same moment. If the reading speed is too low, it is possible, for example, to read X and Y
sampled at T1 and Z sampled at T2.

2.2 Output data rate selection and reading timing

The output data rate is user selectable through the DRx bits of the CTRL_REG1 (20h)
register. At power-on-reset, the DRx are reset to 0, thus providing a default output data rate
of 50 Hz.

The analog signal coming from the mechanical sensor is filtered by a low pass filter before
being converted by the internal ADC. The frequency at -3 dB of the low pass filter
determines the effective system resolution. The cut-off frequency depends on the DR<1:0>
bits in the CTRL_REG1 (20h) register (Table 2).

Table 2. Output data rate

DR1, DR0 Output data rate

00 50 Hz 37 Hz

01 100 Hz 74 Hz

10 400 Hz 292 Hz

11 1000 Hz 780 Hz

Analog filter

cut-off frequency (-3 dB)

Note: The output data rate precision is related to the internal oscillator; an error of +/- 10% should

be taken into account.

A typical reading period is defined which is 616 µs shorter than the output data rate period,
in order to prevent the loss of any data produced. During this time period the reading of the
data must be performed and the DataReady signal can be used as a trigger to begin the
reading sequence. At the end of the complete sequence, the DataReady signal goes down
and the rising edge that follows signals that new data are available. If this minimum reading
frequency is not observed, some data loss is possible and the DataReady signal is no
longer considered a trigger signal. The status register can be used to infer the occurrence of
an overrun.

Figure 1. Reading timing

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Table 3. Timing value to prevent data loss

Time Description Typ

T0 Data rate 1/ODR

Doc ID 15136 Rev 2 9/31

".W

Start-up sequence AN2847

Table 3. Timing value to prevent data loss

Time Description Typ

T1 Reading period T0-T2

T2 New data generation 616 µs

2.3 Data ready vs. interrupt signal

The device has two pins which can be activated to generate either the data-ready signal or
the interrupt signal. The functionality of the pins is selected acting on bit I1(2)_CFGx bits of
the CTRL_REG3 register, according to Table 4 and the block diagram shown in Figure 2.

Table 4. Data signal on INT 1 and INT 2 pads

I1(2)_CFG1 I1(2)_CFG0 INT 1(2) Pin

0 0 Interrupt 1 (2) source

0 1 Interrupt 1 source OR Interrupt 2 source

1 0 Data ready

1 1 Boot running

Figure 2. Interrupt and DataReady signal generation block diagram

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In particular, the data-ready (DR) signal rises to 1 when a new set of acceleration data has
been generated and is available for reading. The signal is reset after all the enabled
channels are read through the serial interface.

10/31 Doc ID 15136 Rev 2