ST AN2846 APPLICATION NOTE

AN2846

Application note

SCLT3-8 - guidelines for use in industrial automation applications

Introduction

The serial current limited termination device SCLT3-8 provides 8 inputs and supports the
data transfer of the input states through a limited opto-transistor count thanks to the digital
SPI (serial peripheral interface).

The purpose of this document is to:

■ Help designers to use the SCLT3-8 in basic operations and to allow them to use it easily

in their own applications by describing the SCLT3-8 behavior in detail (Refer also to the
SCLT3-8 device datasheet and to the User guide for the evaluation board
STEVAL-IFP000V1.)

■ Provide basic schematic diagrams

■ Provide information on the thermal behavior of the SCLT3-8 device

■ Offer recommendations to achieve robust SCLT3-8 designs to optimize EMI protection in

accordance with industry standards (IEC 61000-4-2, 4-4, 4-5 and 4-6)

February 2010 Doc ID 15130 Rev 1 1/35

www.st.com

Contents AN2846

Contents

1 Application guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Features of the SCLT3-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Current-limited inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2.1 Maximum input current setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2.2 Input characteristics (IEC 61131-2 standard) . . . . . . . . . . . . . . . . . . . . . 6

1.2.3 Digital input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2.4 Input signal frequency limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.2.5 Input state monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3 Monitoring functions and regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3.1 VCC monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3.2 Power loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.3.3 Overtemperature detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.3.4 Internal voltage regulator 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.4 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.4.1 Input state register and parity bit generator . . . . . . . . . . . . . . . . . . . . . 14

1.4.2 Data shift register and control shift register . . . . . . . . . . . . . . . . . . . . . . 15

1.4.3 Digital inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.4.4 SPI functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.4.5 SPI timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2 Thermal dissipation calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1 Forward inputs polarity case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.2 Reverse polarity on a single input case . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3 Temperature gradient on the SCLT3 and on the board . . . . . . . . . . . . . . 20

3 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1 Basic SCLT3-8 board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2 Component definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2.1 Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4 Isolation management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1 Opto-coupler isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 Magnetic digital isolator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/35 Doc ID 15130 Rev 1

AN2846 Contents

5 SCLT3-8 link configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6 Electromagnetic compatibility (EMC) requirements . . . . . . . . . . . . . . 29

6.1 IEC 61000 4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2 IEC 61000 4-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.3 IEC 61000 4-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3.1 Results on input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3.2 Results on VC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.4 IEC 61000 4-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Doc ID 15130 Rev 1 3/35

Application guidelines AN2846

V

CS

V

DD

Input
state
register

Data

Transfer

logic

shift
register

Parity
bits
gen.

4 lines

8 lines

8

lines

8 lines

Prog.
digital
filters

8 Lines

Current

reference

Oscillator

Undervoltage

alarm

Power

reset

Power
supply

/CS

SPM

SCK

MOSI

/MISO

COM

S

MISO

V

C

DVR

OSC

REF

IN

1

LD

1

IN

8

LD

8

COM

P

V

DD

Overtemperature

alarm

Write

V

DD

Shift

Ctrl
shift
register

8/16

Bits

Shift

Input

protection

and

input current

limiters

MOSI

1 Application guidelines

1.1 Features of the SCLT3-8

The SCLT is an octal input active termination device designed for 24 V DC high density input
modules used in industrial automation. Each channel circuit terminates the connection
between a high side proximity sensor and the I/O module.

The advanced features of the SCLT3-8 compared to the basic CLT3-4BT6 device are:

● SPI for digital output count reduction

● Doubling of input terminations: 8 inputs compared to 4

● Input state monitoring by LEDs from the process section

● Undervoltage alarm detection of the power bus

● Power bus loss detection

● 5 V supply source available for external driving circuits like opto-couplers or magnetic

isolators

● Overtemperature detection

● Checksum data transmission through SPI for better data transfer integrity

The SCLT3-8 also features an input overvoltage protection. This input protection makes this
device robust against electromagnetic interference as defined in IEC 61000-4-x standards:
ESD, fast transient bursts, and voltage surges.

It is housed in a very low R

exposed pad, surface mount, HTSS0P38 package to reduce

TH

the circuit board size and the cooling pad.

Figure 1 shows the schematic block diagram for the device.

Figure 1. Schematic block diagram

Transfer

logic

Bits

4/35 Doc ID 15130 Rev 1

AN2846 Application guidelines

The SCLT3-8 has been designed to run with SPI protocol C
format is 16 bits or 8 bits long according to SPM pin level. When SPM is grounded, 16 bits
are transmitted - 8 input data bits and 8 control bits. When SPM is connected to V
the 8 input data bits are transmitted.

Ta bl e 1 defines the significance of the16 bits. Bit 15 is the most significant bit. Detailed SPI

functionality is described in Section 1.4.

Table 1. 16-bit frame definition

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit09 Bit08

Data bits

IN

8

IN

7

Bit07 Bit06 Bit05 Bit04 Bit03 Bit02 Bit01 Bit00

Control Bits

/UVA /OTA PC1 PC2 PC3 PC4 0 1

1.2 Current-limited inputs

1.2.1 Maximum input current setting

All internal bias currents sources and particularly the input current limiter are defined by the
reference resistor connected to pin REF. A 15 kΩ resistor will assure a typical input limited
current of 2.35 mA (see Figure 2). The typical limited input current I
formula:

V

REF

BG

kR

5.1

+

I

LIM

30

·=

()

IN

= 0 and C

PHA

BG

IN

5

25.1Vcalwith typi

=

6

IN

4

IN

3

LIM

V

= 0. The frame

POL

DD

IN

2

is given by the

only

IN

1

Figure 2. Current limiter diagram

I

LIM

1 : 20

1 : 1

LED

VBG=1.25V

1.5k

REF

R

=15k

REF

2 : 3

LED_ON

COMs

The technology used allows a very low current dispersion according to the different
channels (less than 10%). The reference voltage V

is also compensated over the junction

BG

temperature range from -25 °C to 150 °C enabling a good stability of the limited current (see

Figure 3).

Doc ID 15130 Rev 1 5/35

Application guidelines AN2846

Figure 3. Limited current versus junction temperature

I (mA)

lim

2.6

2.5

2.4

2.3

2.2

2.1

-25°C 25°C 125°C 150°C

Vcc = 24 V, Vi = 11 V

Junction temp (°C)

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

Figure 4 shows the I

trend versus R

LIM

. according to the input current setting and

REF

therefore the dissipated power, the SCLT3-8 should be cooled with a sufficient copper heat
sink area (see Section 2)

Figure 4. Typical limiting input current versus R

I (mA)

lim

8.0

7.0

6.0

5.0

4.0

3.0

2.0

3 5 7 9 11 13 15

9.13.9

REF

Test conditions:

I versus R

LIM REF

V = 24 V, V = 24 V

CC I

R (k)

REF

15

1.2.2 Input characteristics (IEC 61131-2 standard)

According to the IEC 61131-2 standard and referring to type 3, when the input current is less
than 1.5 mA the output circuit passes all the input current, keeping the monitoring LED off
and transmits a low level state to the input state register.

When the module input voltage V
than 11 V (that is, the SCLT3-8 input voltage V
on and the circuit transmits a high level state to the input state register.

Figure 5 gives the input characteristics and operating regions of type 3, defined in the

IEC 61131-2 standard, and the typical SCLT3-8 input characteristic.

6/35 Doc ID 15130 Rev 1

, taking into account the 2.2 kΩ input resistor, is higher

I

is higher than 5 V) the monitoring LED is

IN

AN2846 Application guidelines

INPUT STATUS

Figure 5. Input characteristic according to IEC 61131-2 type 3

(V)

IN

V

11V

OFF Region

5V

0.1

Transition Region

OFF

OFF

ON Region

ON

ON

11V

SCLT3-8 (including RIN)

input characteristic

5V

OFF

I

2.01.5

I

LIMIT

(mA)

IN

Current limited inputs allow reduced power dissipation into the device as well as reduced
power needed by the external supplies. A typical application circuit schematic is shown in

Figure 31 in the application section.

Figure 6 displays the SCLT3-8 input stage configuration and its typical input threshold

voltages. Low frequency triangular waveform as the input voltage has been used to better
highlight the voltage thresholds. Input current (I
displayed in Figure 6. The V

wave shape shows clearly the on-off states of the SCLT3-8.

LED

) and voltage across the LEDs are also

IN

Figure 6. Input stage

VIN:

2V/div

VI: 2V/div

V

IN_ON

= 9.5 V

I

LIM

= 2.35 mA

V

IN_OFF

IIN: 1mA/div

=8.0 V

R

IN

V

I

IN

V

I

IN

V

LED

TH

2.35 mA

DIGITAL
FILTER

V

LED

Input stage configuration Typical input voltage thresholds

With R

= 2.2 kΩ, the typical V

IN

I_ON

and V

threshold voltages are respectively 9.5 V

I_OFF

and 8.5 V, consistent with the 11 V min. and 5 V max specified in the IEC 61131-2 standard.
The hysteresis (1 V) improves the input noise immunity.

The module input thresholds are the results of drop voltage across the input resistor R
into which flows the input current I
V

TH_OFF

.

The input current limiter is activated typically when V

, and the SCLT3-8 input thresholds V

IN

= 3.7 V, before the V

IN

TH_ON

TH_ON

and

threshold

,

IN

is reached.

In all cases the following formula can be applied:

VIRV+×=

INININI

When the input current limiter is activated, the formula becomes:

VIRV+×=

The typical module input threshold voltage can be calculated as follow:

VIRV

Math Composer 1.1.5

+×=

ONVTHILIMINONIN

__

Doc ID 15130 Rev 1 7/35

Application guidelines AN2846

The proposed RIN value of 2.2 kΩ has been calculated to meet the IEC 61131-2 threshold
requirements. Users can set their own particular application threshold voltages by applying,
in the formula given above, the V
value. Take note, the higher the R

they want to achieve and find the corresponding RIN

IN

, the better will be the immunity against voltage surges.

IN

A particular useful application is when an input type 2 is needed. Figure 7 shows the
solution of connecting R
R

= 9.1 kΩ to get 3.5 mA (see Figure 4) in each input branch. Of course corresponding

REF

and input R

IN7

= 1.5 kΩ in parallel and tuning the I

IN8

LIM

with

bits (B14, B15) will be set together at the right state according to the level applied at the
common input. Unused LED outputs must be grounded to maintain the flow of the

current in its corresponding chanel.

Figure 7. IN

The different threshold voltages and the I

and IN8 parallel wired for type 2

7

RIN= 1.5k Ω

Type 3 inputs

Type 2 inputs

R

IN

1

IN

2

IN

3

IN

4

IN

5

IN

6

IN

7

IN

8

= 7.0 mA are shown in Figure 8 below.

LIMIT

R

REF

LED

LED

LED

LED

LED

LED

LED

LED

1

2

3

4

5

6

7

8

REF

= 9.1kΩ

Figure 8. Threshold voltages - type 2 configuration using two inputs in parallel

VI(2V/div)

V

= 9.9 V

I_ON

V

(2V/div)

(5mA/div)

I

IN

V

IN

LED

I

LIMIT

8/35 Doc ID 15130 Rev 1

= 7.0mA

V

I_OFF

= 8.4 V

AN2846 Application guidelines

1.2.3 Digital input filter

Input parasitic disturbances can be removed by the programmable input digital filter. It is
based on an RC oscillator, a divider and a two step filter (see Figure 9).

Figure 9. Digital input filter.

CKF

IN<1:8>

OUT<1:8>

OSC period = 1.2 µ s

POR

REF1V

R

OSC

Oscillator

= 51 k

OSC

OSCR DVR

Divider filter_2step

The internal capacitor value is typically 10 pF. The oscillator resistor is connected externally
on pin R
when it is connected to V
least three rising edges as shown in Figure 9. The delay time is between 2 · t
3·t

OSC

. The clock divider is set at 8 when the pin DVR is connected to GND or at 64

OSC

. A wide filter time range, tFT, can be set by using the couple R

. The two step filter validates the input voltage when it sees at

DD

OSC

and DVR as

OSC

and

shown in below in Figure 10.

Figure 10. Minimum t

t (µS)

FT

600

500

400

300

200

100

0

0 500 1000 1500

FT

DVR=8

versus R

OSC

Rosc(k )Ω

t (µS)

FT

4000

3000

2000

1000

0

0 500 1000 1500

DVR=64

Rosc

(K )Ω

The user can also choose a particular typical filter time, tFT, by calculating the corresponding
R

value from the formula:

OSC

Math Composer 1.1.5

t

R

OSC

FT

2

××=

DVR

11

-

12

105.23

×

Doc ID 15130 Rev 1 9/35

Application guidelines AN2846

1.2.4 Input signal frequency limitation

The maximum frequency transmitted trough the current limited inputs is limited by 3 factors:

1. The input digital filter, which cuts undesirable frequencies. R
DVR connected to GND ensures that the input signal has to be at a stable level for
more than 20 µs to be taken into account. This allows a maximum input frequency of
25 kHz. It can be reduced to 130 Hz using the combination of R
connected to V

2. The input capacitors C
signal. R

= 2.2 kΩ and CIN = 22 nF ensures a 3.2 kHz low pass filter.

IN

DD

.

are used to increase the EMI immunity filter of the input

IN

3. The SPI sampling effect - the input states are taken into account at each /CS fall (see

Section 1.4.4). This achieves a sampling of inputs at the /CS frequency, as shown in
Figure 11. The input states will be correctly transmitted if the sampling mode meets the

Shannon equation:

F2F

•=

InputCS/

Fwith

/CS

Input

1

=

t

/CS

=

/CS

frequencyinputmaxFwith

/CSthetwith:

periodsignal

Figure 11. Sampling effect

t

INPUT

set to 51 kΩ and

OSC

= 1.5 MΩ and DVR

OSC

Low level capture

missed

Current limited Input signal

/CS

High level capture

missed

t

/CS

As the /CS period is dependant on the frame length, Tab le 2 below gives some useful
combinations of SCK frequency signal, frame length and current limited input frequency.

Table 2. Input frequency versus SCK and length frame

F

SCK

Frame length 8 16 32 64 8 16 32 64 8 16 32 64 bits

t

/CS

F

current limited input

0.1 1.0 2.0 MHz

80 160 320 640 8 16 32 64 4 8 16 32 µs

6.25 3.125 1.56 0.78 62.5 31.25 15.6 7.8 125 62.5 31.25 15.6 kHz

10/35 Doc ID 15130 Rev 1

AN2846 Application guidelines

1.2.5 Input state monitoring

The state of each of the 8 monitoring LEDs is an image of the 8 filtered input states. All the
monitoring LED cathodes have to be connected to ground. In the on state a current of I
reduced by 0.15 mA is available for each LED. In case of a LED not being used, the LED
output pin must be connected to the ground COM

to allow the input current to flow back to

P

the ground.

LIM

The LEDs must be chosen with a V

voltage less then 2.7 V (at minimum operating

F

temperature -25 °C).

1.3 Monitoring functions and regulator

1.3.1 VCC monitoring

The power bus voltage connected to VCC is sensed by the VCS pin through a resistor bridge.
The V
easily set their own alarm detection voltage by an appropriate resistor bridge (see

Figure 12) using the formula:

Figure 12. UVA comparator

threshold voltage is typically 1.25 V with a hysteresis of 100 mV. Designers can

CS

R

VV+=

min_

CSCC

S

)1(

R

PD

V

CC

R

S

V

CS

V

DD

UVA

R

PD

VBG=1.25V

For example, the resistor bridge consisting of R
activation when V

drops below 17 V. The UVA activation has no effect on SCLT3-8

CC

COM

= 1.5 MΩ and R

S

1ms delay

= 120 kΩ produces UVA

PD

behavior but the information is transmitted trough the SPI bus by setting bit 7 to low state in
the control bits register (see Figure 13 and Figure 14).

To eliminate any short voltage disturbances that could trigger the UVA, a 1 ms delay circuit
has been inserted in the output line of the UVA comparator.

Doc ID 15130 Rev 1 11/35