ST AN2839 APPLICATION NOTE

AN2839

Application note

L6228 fully-integrated two-phase stepper motor driver

Introduction

Modern motion control applications need more flexibility, which can only be addressed with specialized IC products. The L6228 is a fully-integrated stepper motor driver IC specifically developed to drive a wide range of two-phase (bipolar) stepper motors. This IC is a onechip, cost-effective solution that includes several unique circuit design features. These features, including a decoding logic that can generate three different stepping sequences, allow the device to be used in many applications, including microstepping. The principal aim of this development project was to produce an easy-to-use, fully-protected power IC. In addition, several key functions, such as protection circuitry and PWM current control, drastically reduce the number of external components to meet requirements for many different applications.

The L6228 is a highly-integrated, mixed-signal power IC that allows the user to easily design a complete motor control system for two-phase bipolar stepper motors. Figure 1 shows the L6228 block diagram. The IC integrates eight Power DMOS’s, a centralized logic circuit that implements the phase generation and a constant tOFF PWM current control technique (quasi-synchronous mode) for each of the two phases of the motor, plus other added features for safe operation and flexibility.

Figure 1. L6228 block diagram

9%227	9%227							96$
				9%227		9%227
	&+$5*(		7+(50$/
9&3
	3803		3527(&7,21
			2&'$	29(5
				&855(17
			2&'%	'(7(&7,21				287$
								287$
				9		9
(1				*$7(
&21752/				/2*,&
								6(16($
+$/) )8//					3:0
&/2&.	67(33,1*			21( 6+27	0$6.,1*
5(6(7	6(48(1&(			021267$%/(	7,0(	6(16(		95()
	*(1(5$7,21							$
&: &&:						&203$5$725
						%5,'*($		5&$
	92/7$*(			29(5				96%
	5(*8/$725							287%
*1'				&855(17
*1'				'(7(&7,21				287%
*1'	9	9		*$7(				6(16(%
*1'				/2*,&				95()%
	/					%5,'*( %		5&%
								!-V

September 2009

Doc ID 15104 Rev 1

1/40

www.st.com

Contents	AN2839

Contents

1	Designing an application with L6228 . . . . . . . . . . . . . . . . . . . . . . . . . .		. 4
	1.1	Current ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4
	1.2	Voltage ratings and operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4
	1.3	Choosing the bulk capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	1.4	Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	1.5	Sensing resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	1.6	External components for the charge pump . . . . . . . . . . . . . . . . . . . . . . .	10
	1.7	Sharing the charge pump circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	1.8	Reference voltage for PWM current control . . . . . . . . . . . . . . . . . . . . . . .	12
	1.9	Input logic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	1.10	EN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	1.11	Programmable off time monostable . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14

1.11.1 Off time selection and minimum on time . . . . . . . . . . . . . . . . . . . . . . . . 16 1.11.2 Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.12 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.13 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.13.1 Maximum output current versus selectable devices . . . . . . . . . . . . . . .

23

1.13.2Power dissipation and thermal analysis with PractiSPINTM software . . 23

1.14 Choosing the decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.15 Choosing the stepping sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.16 Microstepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2	Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		29
Appendix A		Demonstration board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
	A.1	PractiSPINTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
	A.2	L6228N evaluation with EVAL6208N. . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32

A.2.1 Important notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

A.3 EVAL6228QR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2/40	Doc ID 15104 Rev 1

AN2839	List of figures

List of figures

Figure 1.	L6228 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 1
Figure 2.	Supply voltage of high-side gate drivers versus supply voltage . . . . . . . . . . . . . . . . . . . . .	. 4
Figure 3.	Currents and voltages during the dead time at the beginning of the off time . . . . . . . . . . .	. 5
Figure 4.	Voltage at the two outputs at the beginning of the off-time. . . . . . . . . . . . . . . . . . . . . . . . . .	6
Figure 5.	Typical application and layout suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
Figure 6.	Two situations that must be avoided . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
Figure 7.	Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
Figure 8.	Sharing the charge-pump circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
Figure 9.	Obtaining a variable voltage through a PWM output of a µC . . . . . . . . . . . . . . . . . . . . . .	12
Figure 10.	Logic input pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
Figure 11.	EN input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
Figure 12.	Simplified schematic of the PWM current controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
Figure 13.	Output current regulation waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
Figure 14.	Typical off time vs. COFF for several values of ROFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 15.	Minimum on time vs. COFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 16.	Fast decay mode output stage configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
Figure 17.	Slow decay mode output stage configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
Figure 18.	PWM controller loses the current regulation due to minimum on time . . . . . . . . . . . . . . . .	18
Figure 19.	PWM controller loses the current regulation due to minimum on time - detail . . . . . . . . . .	18
Figure 20.	Simplified circuitry of the overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
Figure 21.	Overcurrent operation: timing 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
Figure 22.	Overcurrent operation: timing 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
Figure 23.	Typical disable time vs. CEN for several values of REN . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
Figure 24.	Typical delay time vs. CEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
Figure 25.	IC dissipated power versus output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
Figure 26.	Maximum output current vs. selectable devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
Figure 27.	Power dissipation and thermal analysis with PractiSPINTM software . . . . . . . . . . . . . . . . .	24
Figure 28.	Torque instability in full-step mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
Figure 29.	Balanced half step for low torque ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 30.	Realizing half-step current shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 31.	Microstepping application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Figure 32.	Microstepping reference voltages, output currents and CLOCK signal . . . . . . . . . . . . . .	27
Figure 33.	Using fast decay during a high, negative current slope . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Figure 34.	Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
Figure 35.	PractiSPINTM PC software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 36.	PractiSPINTM ST7 demonstration board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 37.	EVAL6208N electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
Figure 38.	EVAL6228QR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
Figure 39. EVAL6228QR component placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		35
Figure 40.	EVAL6228QR top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
Figure 41.	EVAL6228QR bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
Figure 42.	EVAL6228QR electrical schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37

Doc ID 15104 Rev 1

3/40

Designing an application with L6228	AN2839

1 Designing an application with L6228

1.1Current ratings

With MOSFET (DMOS) devices, unlike bipolar transistors, the current under short-circuit

conditions is, at a first approximation, limited by the RDS(on) of the DMOS themselves and can reach very high values. The L6228’s OUT pins and the two VSA and VSB pins are rated

for a maximum of 1.4 Arms and 2.8 A peak (typical values), corresponding to a total of 2.8 Arms (5.6 A peak) for the whole IC. These values are meant to avoid damaging the metal structures, including the metallization on the die and bond wires. In practical applications, however, the maximum-allowable current is less than these values, due to power dissipation limits (see Section 1.13). The device has a built-in overcurrent detection (OCD) that provides protection against short-circuits between the outputs and between an output and ground (see Section 1.12).

1.2Voltage ratings and operating range

The L6228 requires a single supply voltage (VS) for the motor supply. Internal voltage regulators provide the 5 and 10 volts required for the internal circuitry. The operating range for VS is 8 to 52 V. To prevent the device from operating at an insufficient supply voltage, an undervoltage lockout (UVLO) circuit shuts down the device when the supply voltage falls below 5.5 V; to resume normal operating conditions, VS must then exceed 6.3 V. The hysteresis is provided to avoid false intervention of the UVLO function during fast VS

ringings. It should be noted, however, that the DMOS' RDS(on) is a function of the VS supply voltage. In fact, when VS is less than 10 V, RDS(on) is adversely affected, and this is particularly true for the high-side DMOS’s that are driven from the VBOOT supply. This supply is obtained through a charge pump from the internal 10 V supply, which will tend to reduce

its output voltage when VS goes below 10 V. Figure 2 shows the supply voltage of the highside gate drivers (VBOOT - VS) versus the supply voltage (VS).

Figure 2. Supply voltage of high-side gate drivers versus supply voltage

!-V

Note that VS must be connected to both VSA and VSB since the bootstrap voltage (at the

VBOOT pin) is the same for the two H-bridges. The integrated DMOS’s have a rated drainsource breakdown voltage of 60 V. However, VS should be kept below 52 V, since in normal

working conditions the DMOS’s see a Vds voltage that will exceed the VS supply. In particular, when using the fast-decay mode, at the beginning of the off time (when all the DMOS’s are off during dead time) the SENSE pin sees a negative spike due to a nonnegligible parasitic inductance of the PCB path from the pin to GND.

4/40	Doc ID 15104 Rev 1

AN2839	Designing an application with L6228

This spike is followed by a stable negative voltage due to the drop on RSENSE. One of the two OUT pins of the bridge sees a similar behavior, but with a slightly larger voltage due to

the forward recovery time of the integrated freewheeling diode and the forward voltage drop across it (see Figure 3). The typical duration of this spike is 30 ns. At the same time, the other OUT pin of the same bridge sees a voltage above VS, due to the PCB inductance and voltage drop across the high-side (integrated) freewheeling diode, as the current reverses direction and flows into the bulk capacitor. It turns out that, in fast decay mode, the highest differential voltage is observed between the two OUT pins of the same bridge, at the beginning of the off time, and this must always be kept below 60 V(a). The same highvoltage condition exists when a step is made and the direction of the current flow reverses in the bridge.

Figure 3. Currents and voltages during the dead time at the beginning of the off time

	3&% 3DUDVLWLF	96
(65	,QGXFWDQFH
(6/

%XON &DSDFLWRU

(TXLYDOHQW &LUFXLW

287

56(16(, 9) 'LRGH 287

		'DQJHURXV	969) 'LRGH
	56(16(,	+LJK 'LIIHUHQWLDO 9ROWDJH
		6(16(
		3&% 3DUDVLWLF
		56(16( ,QGXFWDQFH
			!-V

Figure 4 on page 6 shows the voltage waveforms at the two OUT pins referring to a possible

practical situation, with a peak output current of 1.4 A, VS = 52 V, RSENSE = 0.33 Ω, TJ = 25 °C (approximately) and a good PCB layout. The below-ground spike amplitude is -2.65 V for

one output; the other OUT pin is at about 57 V. In these conditions, the total differential voltage reaches almost 60 V, which is the absolute maximum rating for the DMOS. It is extremely important to keep the differential voltage between two output pins belonging to the same full bridge within rated values. This can be accomplished by correctly selecting the value of the bulk capacitor and equivalent series resistance (ESR), according to the current peaks and chopping style, and by adopting good layout practices to minimize PCB parasitic inductances(a).

a. Refer to [3] in References.

Doc ID 15104 Rev 1

5/40

Designing an application with L6228	AN2839

Figure 4. Voltage at the two outputs at the beginning of the off-time

2XW

2XW

!-V

1.3Choosing the bulk capacitor

Since the bulk capacitor, placed between the VS and GND pins, is charged and discharged during IC operation, its AC current capability must be greater than the RMS value of the charge/discharge current. This current flows from the capacitor to the IC during the on time (tON) and from the IC (in fast decay; from the power supply in slow decay) to the capacitor during the off time (tOFF). The RMS value of the current flowing into the bulk capacitor depends on the peak output current, output current ripple, switching frequency, duty cycle and chopping style. It also depends on the characteristics of the power supply. A power supply with poor high-frequency performances (or long, inductive connections to the IC) will cause the bulk capacitor to be recharged slowly: the higher the current control switching frequency, the higher the current ripple in the capacitor; RMS current in the capacitor, however, does not exceed the RMS output current. The bulk capacitor value (C) and the ESR determine the amount of voltage ripple on the capacitor itself and on the IC. In slow decay, neglecting the dead-time and output current ripple, and assuming that during the on time the capacitor is not recharged by the power supply, the voltage at the end of the on time is:

Equation 1

							tON
	V		– I				ESR + ----------
		S		OUT
							C

so the supply voltage ripple is:

Equation 2

					tON
	I				ESR + ----------
		OUT
					C

where IOUT is the output current. In fast decay, instead, the recirculating current recharges the capacitor, causing the supply voltage to exceed the nominal voltage. This can be very dangerous if the nominal supply voltage is close to the maximum recommended supply voltage (52 V).

In fast decay the supply voltage ripple is about:

6/40	Doc ID 15104 Rev 1

AN2839					Designing an application with L6228
Equation 3
				tON
I					+ tOFF
	OUT			2 ESR + -------------------------------	C

always assuming that the power supply does not recharge the capacitor, and neglecting the output current ripple and the dead-time. Usually (if C > 100 µF) the capacitance role is much less than the ESR, in which case the supply voltage ripple can be estimated as:

Equation 4

IOUT ESR

Equation 5

2 IOUT ESR

For example, if a maximum ripple of 500 mV is allowed and IOUT = 1 A, the capacitor ESR should be lower than:

Equation 6

ESR <	0.5V	=	500mΩ	in slow decay
	------------
	1A
Equation 7
1	0.5V		= 250mΩ	in fast decay
ESR < --	------------
2	1A

In fact, current sunk by the VSA and VSB pins of the device is subject to higher peaks due to the reverse recovery charge of the internal freewheeling diodes. The duration of these peaks is very short and can be filtered using a small value (100÷200 nF), good-quality ceramic capacitor connected as close as possible to the VSA, VSB and GND pins of the IC. The bulk capacitor should be chosen with a maximum operating voltage 25% greater than the maximum supply voltage, considering also the power supply tolerances. For example, with a 48 V nominal power supply with 5% tolerance, the maximum voltage will be 50.4 V, and the operating voltage for the capacitor should be at least 63 V.

1.4Layout considerations

Working with devices that combine high-power switches and control logic in the same IC, special attention has to be paid to the layout of the PCB. In extreme cases, Power DMOS commutation can induce noise that may cause improper operation in the logic section of the device. Noise can be radiated by high dV/dt nodes or high dI/dt paths, or conducted through GND or supply connections. Logic connections, especially high-impedance nodes (actually all logic inputs, see Section 1.9), must be kept far from switching nodes and paths. With the L6228 in particular, the external components for the charge-pump circuitry should be connected together through short paths, since these components are subject to voltage and current switching at a relatively high frequency (600 kHz). The primary means of minimizing conducted noise is to work on a good GND layout (see Figure 5 on page 8).

Doc ID 15104 Rev 1

7/40

Designing an application with L6228	AN2839

Figure 5. Typical application and layout suggestions

3KDVH

6WHSSHU 0RWRU

'

'

&

&

5

287 $ 287 $287% 287%

9%227

&3

96$ 96%

6(16($

&

&: &&:

6(16(%

5

5

&21752/

/RJLF 6XSSO\

RU

/

&

&

96

· 9

· 9

&XVWRP /RJLF

5(6(7

+$/) )8//

&/2&.

(1

5

9UHI$

9UHI%

5&$

5&%

*1' *1' *1' *1'

&

&

&

&

5

5

9UHI · 9

!-V

The high current GND tracks (the tracks connected to the sensing resistors) must be connected directly to the negative terminal of the bulk capacitor. A good quality, highfrequency bypass capacitor is also required (typically a 100÷200 nF ceramic would suffice), since electrolytic capacitors show a poor high-frequency performance. Both bulk electrolytic and high-frequency bypass capacitors have to be connected with short tracks to VSA, VSB and GND. On the L6228 the GND pins are the logic GND since only the quiescent current flows through them. The logic GND and power GND should be connected together in a single point, the bulk capacitor, to keep noise in the power GND from affecting the logic GND. Specific care should be paid layouting the path from the SENSE pins through the sensing resistors to the negative terminal of the bulk capacitor (power ground). These tracks must be as short as possible to minimize parasitic inductances that can cause dangerous voltage spikes on the SENSE and OUT pins (see Section 1.2); for the same reason the capacitors on VSA, VSB and GND should be very close to the GND and supply pins. Refer to Section 1.5 for information on selecting the sense resistors. The traces connected to VSA, VSB, SENSEA, SENSEB, and the four OUT pins must be designed with adequate width, since high currents flow through these traces, and layer changes should be avoided. Should a layer change prove necessary, multiple and large via holes have to be used. A wide GND copper area can be used to improve heat removal, thus reducing thermal resistance.

Figure 6 on page 9 shows two typical situations that must be avoided. An important consideration regarding the location of the bulk capacitors is the ability to absorb the inductive energy from the load, without allowing the supply voltage to exceed the maximum rating. The diode shown in Figure 6 prevents the recirculation current from reaching the capacitors and will result in a high voltage on the IC pins that can damage the device. Having a switch or a power connection that can disconnect the capacitors from the IC, while there is still current in the motor, will also result in a high voltage transient since there is no capacitance to sink the recirculating current.

8/40	Doc ID 15104 Rev 1

AN2839	Designing an application with L6228

Figure 6. Two situations that must be avoided

					$/.{4.PUT4A DIODETHERE
					2ECIRCULATINGUCURRENTICANNOT FLOWWINTOTHE
	96$	96%			BULKLCAPACITORPANDCCAUSES A HIGHVOLTAGE
					SPIKEETHAT CAN DAMAGEATHE )#
			6(1 6($
,			6(1 6(%
				5
				&	&	· 9
*1'	*1'	*1'	*1'		96

$/.{T.CONNECTCTHENLOGICC'.$ HERE

6OLTAGE DROPEDUEDTO CURRENT INESENSE PATH CAN DISTURB LOGIC '.$

!-V

1.5Sensing resistors

Each motor winding current flows through the corresponding sensing resistor, causing a voltage drop that is used, by the logic, to control the peak value of the load current. Two important points must be taken into account when choosing the RSENSE value.

●The sensing resistor dissipates energy and provides dangerous negative voltages on the SENSE pin during the current recirculation. For this reason, the resistance of this component should be kept low.

●The voltage drop across RSENSE is compared with the reference voltage (on the Vref pin) by the internal comparator. The lower the RSENSE value, the higher the peak current error due to noise on the Vref pin and to the input offset of the current sense comparator: RSENSE values that are too small must be avoided.

A good compromise is to calculate the sensing resistor value so that the voltage drop, corresponding to the peak current in the load (Ipeak), is about 0.5 V: RSENSE = 0.5 V/Ipeak.

The sensing resistor must be of a non-inductive type in order to avoid dangerous negative spikes on the SENSE pins. Wire-wound resistors cannot be used here, while metallic film resistors are recommended for their high peak current capability and low inductance. For the same reason, the connections between the SENSE pins, C6, C7, VSA, VSB and GND pins (see Figure 5 on page 8) must be as short as possible (also see Section 1.4).

The average power dissipated by the sensing resistor is:

●Fast decay recirculation: PR ≈ Irms2 · RSENSE

●Slow decay recirculation: PR ≈ Irms2 · RSENSE · D

where D is the duty-cycle of the PWM current control and Irms is the RMS value of the load current. Nevertheless, the peak value of the dissipated power should be taken into account

when choosing the power rating of the sensing resistor.

Equation 8

PR ≈ Ipk2 RSENSE

Doc ID 15104 Rev 1

9/40

Designing an application with L6228	AN2839

where Ipk is the peak value of the load current.

Using multiple resistors in parallel will help obtain the required power rating with standard resistors and reduce the inductance.

The RSENSE tolerance reflects on the peak current error: 1% resistors should be preferred.

Table 1 shows the recommended values for RSENSE (to obtain a 0.5-V drop) and power ratings for typical examples of current peak values.

Table 1.	RSENSE recommended values
Ipk		RSENSE value [Ω]	RSENSE power rating [W]	Alternatives
0.25		2	0.125
0.5		1	0.25
1		0.5	0.5	2 X 1 Ω, 0.25 W paralleled

1.6External components for the charge pump

An internal oscillator, with its output at the CP pin, switches from GND to 10 V with a typical frequency of 600 kHz (Figure 7).

Figure 7. Charge pump

						96 9 9'
96 9 9' 9'				I		96 9'
					N+]
	'		'		&
	&
	9%2 27	&3	96$ 96%
	7R +LJK 6LGH		9			&KDUJH3X PS
	*DWH'ULYHUV		5'6 21	RKP		2VFLOODWRU
						9
						9
9
			5'6 21	RKP
I	N+]
						,
						!-V

When the oscillator output is at ground, C5 is charged by VS through D2. When it rises to

10 V, D2 is reverse-biased and the charge flows from C5 to C8 through D1, so the VBOOT pin, after a few cycles, reaches the maximum voltage of VS + 10 V - VD1 - VD2, which supplies

the high-side gate drivers.

With a differential voltage between VS and VBOOT of about 9 V and both bridges switching at 50 kHz, the typical current drawn by the VBOOT pin is 1.85 mA.

10/40

Doc ID 15104 Rev 1

AN2839	Designing an application with L6228

To minimize interferences with the rest of the circuit, care must be taken in realizing the PCB layout of the C5, D1 and D2 connections (also see Section 1.4). The recommended values for the charge pump circuitry are:

●D1, D2: 1N4148

●C5: 10 nF, 100 V ceramic

●C8: 20 nF, 25 V ceramic

Due to the high charge-pump frequency, fast diodes are required. When connecting the cold side of the bulk capacitor (C8) to VS instead of GND, the average current in the external diodes during operation is less than 10 mA; at startup (when VS is provided to the IC) it is less than 200 mA while the reverse voltage is about 10 V in all conditions. IN4148 diodes withstand about 200 mA of DC current (1 A peak), and the maximum reverse voltage is 75 V, so they should fit for the majority of applications.

1.7Sharing the charge pump circuitry

If more than one device is used in the application, the charge pump from one L6228 can be

used to supply the VBOOT pins of several ICs. The unused CP pins on the slaved devices are left unconnected, as shown in Figure 8. A 100 nF capacitor (C8) should be connected to the

VBOOT pin of each device.

The supply voltage pins VS of the devices sharing the charge pump must be connected together.

The higher the number of devices sharing the same charge pump, the lower the differential

voltage available for the gate drive (VBOOT - VS), causing a higher RDS(on) for the high-side DMOS, and as such a higher dissipating power.

Better performance can also be obtained using a 33 nF capacitor for C5 and Schottky diodes (BAT47 are recommended).

Having more than three or four devices sharing the same charge-pump circuitry is not

recommended since this will reduce the VBOOT voltage and increase the high-side MOSFET’s on-resistance, and therefore the power dissipation.

Figure 8. Sharing the charge-pump circuitry

7RRWKHU GHYLFHV

& Q)

' %$7

' %$7

& Q)

&

Q)

9%227

&3

96$

96%

9%227

&3

96$

96%

7R +LJK 6LGH

7R +LJK 6LGH

*DWH 'ULYHUV

*DWH 'ULYHUV

/

/

!-V

Doc ID 15104 Rev 1

11/40

Designing an application with L6228	AN2839

1.8Reference voltage for PWM current control

The device has two analog inputs, VrefA and VrefB, connected to the internal sense comparators, to control the peak value of the motor current through the integrated PWM

circuitry. In typical applications, these pins are connected together to obtain the same current in the two motor windings (one exception is the microstepping operation; see Section 1.16). A fixed reference voltage can be easily obtained through a resistive divider from an available 5 V voltage rail (maybe the one supplying the µC or the rest of the application) and GND.

A very simple way to obtain a variable voltage without using a DAC is to low-pass filter a PWM output of a µC (see Figure 9).

Assuming that the PWM output swings from 0 to 5 V, the resulting voltage will be:

Equation 9

Vref	5V DμC RDIV
	= --------------------------------------------
	RLP + RDIV

where DµC is the duty-cycle of the PWM output of the µC.

Assuming that the output impedance of the µC is lower than 1 kΩ, with RLP = 56 kΩ,

RDIV = 15 kΩ, CLP = 10 nF and a µC PWM switching from 0 to 5 V at 100 kHz, the low-pass filter’s time constant is about 0.12 ms and the remaining ripple on the Vref voltage will be

about 20 mV. Using higher values for RLP, RDIV and CLP will reduce the ripple, but the reference voltage will take more time to vary after changing the duty-cycle of the µC PWM,

and too-high values of RLP will also increase the impedance of the Vref net at low frequencies, causing a poor noise immunity.

As sensing resistor values are typically kept small, a small noise on the Vref input pins might cause a considerable error in the output current. It is recommended to decouple these pins with ceramic capacitors of some tens of nF, placed very close to the Vref and GND pins.

Note that the Vref pins cannot be left unconnected, while, if connected to GND, zero current is not guaranteed due to voltage offset in the sense comparator. The best way to cut down the IC’s power consumption and clear the load current is by pulling down the EN pin. In slow decay, with a very small reference voltage, the PWM’s integrated circuitry can lose control of the current due to the minimum-allowed duration of tON (see Section 1.11).

Figure 9. Obtaining a variable voltage through a PWM output of a µC

3:0 2XWSXW

RI D & 5/3

9UHI

5',9

&/3

*1'

!-V

12/40

Doc ID 15104 Rev 1