AN2808
Application note
Complete DDR2/3 memory power supply controller
Introduction
The PM6670S device is a complete DDR2/3 power supply regulator for portable
applications designed to meet JEDEC specifications. It integrates a constant on-time (COT)
buck controller, a 2 Apk sink/source low dropout regulator (LDO) and a 15 mA low noise
buffered reference.
The COT architecture ensures a fast transient response supporting both polymeric and
ceramic output capacitors. An embedded integrator control loop compensates the DC
voltage error caused by the output ripple. The 2 Apk sink/source linear regulator provides
the memory termination voltage with a fast load transient response.
The device is fully compliant with system sleep states S3, S4 and S5, setting the LDO
output to high-impedance in the suspend-to-RAM state, and performing the tracking
discharge of all outputs in the suspend-to-disk state.
Figure 1. PM6670S demonstration board
November 2008 Rev 1 1/40
www.st.com
Contents AN2808
Contents
1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Switching section (VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Reference and termination voltages (VTTREF and VTT) . . . . . . . . . . . . . 5
2 Demonstration kit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Component assembly and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 Recommended equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 JP3 fixed or adjustable output voltage (mode pin) . . . . . . . . . . . . . . . . . . 13
7.2 JP1 DDR2/DDR3 or power-saving mode (DDRSEL pin) . . . . . . . . . . . . . 13
7.3 JP2 output discharge (DSCG pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.4 JP5 compensation network (COMP pin) . . . . . . . . . . . . . . . . . . . . . . . . . 14
8 Test set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9 Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.1 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.2 Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10 PM6670S evaluation tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10.1 VDDQ, VTT and VTTREF turn on (Soft Start) . . . . . . . . . . . . . . . . . . . . . 17
10.2 VDDQ working mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.2.1 VDDQ forced PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.2.2 VDDQ pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.2.3 VDDQ no-audible pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10.3 VDDQ, VTT and VTTREF load regulation . . . . . . . . . . . . . . . . . . . . . . . . 19
10.4 VDDQ and VTT load transient responses . . . . . . . . . . . . . . . . . . . . . . . . 21
2/40
AN2808 Contents
10.5 VDDQ efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10.6 VDDQ gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.7 VDDQ, VTT and VTTREF turn off (soft end) . . . . . . . . . . . . . . . . . . . . . . 23
10.7.1 Tracking discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.7.2 Non-traking discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10.8 UV, OV and thermal protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.8.1 Latched UV protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.8.2 Latched OV protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.9 VTT current limit (foldback) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.10 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.10.1 Switching frequency vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.10.2 Switching frequency vs output current . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.11 Thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.12 DDR memories (VDDQ = 2.5 V) characterization . . . . . . . . . . . . . . . . . . 32
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3/40
List of figures AN2808
List of figures
Figure 1. PM6670S demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Demonstration schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Top slide component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Top slide view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Layer 2 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Layer 3 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Bottom side view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Bottom side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. JP3 (mode) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. JP1 options when JP3 is in the lower position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. JP1 options when JP3 is in the upper position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. JP2 (DSCG) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. JP5 (COMP) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 14. PM6670S test set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 15. VDDQ Soft Start @150mW load, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. VDDQ turn on (S5), pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. VTT turn on (S0), pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 18. VDDQ=1.8V , VIN=12V, IVDDQ=0A, forced-PWM mode. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 19. VDDQ=1.8V, VIN=12V, IVDDQ=0.5A, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 20. VDDQ=1.8V, VIN=12V, no load, no-audible pulse-skip mode (33kHz) . . . . . . . . . . . . . . . 18
Figure 21. VDDQ load regulation - VIN=12V, pulse-skip mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. VTT load regulation - LDOIN=VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. VTT load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. VDDQ load transient (VIN=12V, LOAD=0A->8A @2.5A/ms). Pulse-skip mode. . . . . . . . . 20
Figure 25. VTT load transient (VIN=12V, LOAD=-2A->2A @2.5A/ms). Pulse-skip mode. . . . . . . . . . 21
Figure 26. VDDQ efficiency vs. load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 27. External MOSFET gate signal (VIN=12 V, load= 0 A). Pulse-skip mode . . . . . . . . . . . . . . 22
Figure 28. External MOSFET gate signal (VIN=12 V, load= 8 A). Pulse-skip mode . . . . . . . . . . . . . . 22
Figure 29. VDDQ, VTTREF, VTT output voltages anl LDO input current. Tracking discharge. No load on
any rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 30. VDDQ, VTTREF, VTT. No-tracking discharge. No load on any output. . . . . . . . . . . . . . . . 23
Figure 31. UV protection, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. OV protection, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 33. VTT current limit during an output short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 34. fsw vs input voltage, DDR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 35. fsw vs iload, Vin = 12V voltage, DDR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 36. VTT current vs temperature , IVTT= 0 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 37. VTT current vs temperature, IVTT= 0.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 38. VTT current vs temperature, IVTT= 1 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 39. VTT current vs temperature, IVTT= 1.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 40. VDDQ load regulation, Vin = 12 V and switching frequency 400 kHz . . . . . . . . . . . . . . . . 32
Figure 41. VDDQ load regulation, Vin = 5 V and switching frequency 400 kHz . . . . . . . . . . . . . . . . . 32
Figure 42. VTT load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 43. VTTREF load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 44. Efficiency vs load - VDDQ = 2.5 V, Vin = 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 45. Efficiency vs load - VDDQ = 2.5 V, Vin = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 46. SW efficiency vs load - VDDQ = 2.5 V, Vin = 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 47. SW efficiency vs load - VDDQ = 2.5 V, Vin = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 48. VDDQ load transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 49. VTT load transient response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4/40
AN2808 Main features
1 Main features
1.1 Switching section (VDDQ)
● 4.5 to 28-V input voltage range
● 0.9 V, ±1% voltage reference
● 1.8 V (DDR2) or 1.5 V (DDR3) fixed output voltages
● 0.9 to 2.6 V adjustable output voltage
● 1.237 V ± 1% reference voltage available
● Very fast load transient response constant on-time control loop
● No-RSENSE current sensing using low-side MOSFETs' R
●
Negative current limit
● Latched OVP, UVP and thermal shutdown
● Fixed 3 ms Soft-Start
● Selectable pulse-skipping at light loads
● Selectable non-audible (33 kHz) pulse-skip mode
● All ceramic output capacitor applications supported
● Output voltage ripple compensation
DS(on)
1.2 Reference and termination voltages (VTTREF and VTT)
● 2 A peak LDO with foldback for VTT
● Remote VTT output sensing
● High-Z VTT output in S3
● Ceramic output capacitors supported
● ±15 mA low-noise buffered reference for VTTREF
5/40
Demonstration kit schematic AN2808
DD
11
66
0S
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
AV
DD
SE
25
10
BA
54J
30k
18k
1u
0u
0u
220u
0u
10
100n
0n
10u
10
10
00p
5k
8k
47n
68
0u
0u
22
00p
33n
0n
13
00k
DD
SE
PS
30A
39k
39k
10
18
2 Demonstration kit schematic
Figure 2. Kit schematic
Q
1L30A
VDD
STPS
1
D3
2 1
220u
C4
12
C3
220u
12
2
R15 6. 8k
1 2
C15 47n
1
R14 7.5k
8
7
6
5
Q2
4
R17 0
C1313100n
0
1 2
R3 1k2
VCC
18
17
VCC
CSNS
19
PHASASE
20
HGATE
21
BOOT
22
LDOIN
23
VTT
24
U1
VTTGND1THPD
2
25
0
10u
0
10u
1n
R16
4R7
12
STPSPS1L3L30M
D2
2 1
3
2
1
S12NH3LL
VCC
0k
0k
R12 10
R11 10
1 2
1 2
12
12
C2121100p
16
14
15
PG
PGND
LGATE
70S
PM66
L
RSE
VTTREF4DD
VTTSNS
5
3
DSCG
13
S3
S5
DSCG
12
COMP
11
MODE
10
VSVSNS
9
VOSC
8
VREF
7
CC
AV
SGND
6
12
100n
C10
12
C8
12
1 C18
J8
VTTREF
R6
0 0
8
7
6
5
Q1
0
0
12
R10100 C12
0
J6
J2
0
L1 1u
S12NH3LL
3
2
1
4
R4 3R3
1 2
1 2
0n
10
0
C202010u
12
C191910u
12
C7
12
C6
12
1
1
J7
VTT
LDOIN
J1
VIN
1
C2
10u
12
12
C1
10u
R1 330k
1 2
C1414100n
12
12
R2
18k
T54J
D1
BA
21
VCC
C111110u
12
R7
3R9
12
VCC
C5
1u
12
1
1
J5
J9
VCC
VCCGND
J3
PGND
J4
1
GND_TP
TP1
12
100k
R13
SW1
2
3
1
4
C22
100p
0
JP2
5 6
3 4
1 2
JP3
MODE
R9
39k
R8
C9
L
RSE
JP1
DD
5 6
3 4
1 2
33n
0
J10
AGND 1
PG
1
JP5
INT_CER
0p
0
1 2
C16 68
0
12
0
C17
0
39k
0
0
0
J11
AGND 1
6/40
AM00646v1
AN2808 Component list
3 Component list
Table 1. BOM list
Qty. Component Description Package P/n Manufacturer Value
2C1, C2
2C3, C4
1C5
3 C6, C7, C11
1C8
4
1C12
1C15
1C16
C9, C10,
C13, C14
Ceramic, 50V,
X5R, 20%
POSCAP, 4V,
15mΩ, 20%
Ceramic, 6.3V,
X5R, 10%
Ceramic, 6.3V,
X5R, 10%
Ceramic, 50V,X7R,
20%
Ceramic, 50V,
X7R, 20%
Ceramic, 50V,
X7R, 10%
Ceramic, 50V,
X7R, 10%
Ceramic, 50V,
X7R, 10%
SMD 1210 UMK325BJ106KM-T Taiyo Yuden 10 µF
SMD 7343
(D)
SMD 1206 Standard 1 µF
SMD 0805 JMK212BJ106KG-T Taiyo Yuden 10 µF
SMD 0603 Standard 33 nF
SMD 0603 Standard 100 nF
SMD 0805 Standard 100 nF
SMD 0603 Standard 6n8
SMD 0603 Standard 680 pF
4TPE220MF Sanyo 220 µF
1 C17 Ceramic, 20% SMD 0603 Standard N.M.
1C18
2C19, C20
2C21, C22
1R1
1R2
1R3
1R4
1R6
1R7
Ceramic, 50V,
X7R, 10%
Ceramic, 6.3V,
X5R, 10%
Ceramic, 50V,
X7R, 10%
Chip resistor,
0.1W, 1%
Chip resistor,
0.1W, 1%
Chip resistor,
0.1W, 1%
Chip resistor,
0.1W, 1%
Chip resistor,
0.1W, 1%
Chip resistor,
0.1W, 1%
SMD 0603 Standard 1 nF
SMD 0805 JMK212BJ106KG-T Taiyo Yuden N.M.
SMD 0603 Standard 100 pF
SMD 0603 Standard 330 kΩ
SMD 0603 Standard 18 kΩ
SMD 0603 Standard 1k2
SMD 0603 Standard 3R3
SMD 0805 Standard 0
SMD 0603 Standard 3R9
7/40
Component list AN2808
Table 1. BOM list (continued)
Qty. Component Description Package P/n Manufacturer Value
1R8
1R9
1R10
R11, R12,
3
1R14
1R15
1R16
1R17
1L1
1 Q1 N-channel, 30V SO-8 STS12NH3LL STMicroelectronics STS12NH3LL
1 Q2 N-channel, 30V SO-8 STS12NH3LL STMicroelectronics STS12NH3LL
R13
Chip resistor,
0.1W, 1%
Chip resistor,
0.1W, 1%
Chip resistor,
0.1W, 1%
Chip resistor,
0.1W, 1%
Chip resistor,
0.1W, 1%
Chip resistor,
0.1W, 1%
Chip resistor,
0.1W, 1%
Chip resistor,
0.1W, 1%
SMT, 12.4Arms,
3.46mΩ
SMD 0603 Standard 39 kΩ
SMD 0603 Standard 39 kΩ
SMD 0603 Standard 0
SMD 0603 Standard 100 kΩ
SMD 0805 Standard 7k5
SMD 0603 Standard 6k8
SMD 0603 Standard 4R7
SMD 0603 Standard 0
15.0x13.2mm MLC1538-102MX Coilcraft 1 µH
1 D1 Schottky, 30V, 0.3A SOD-323 BAT54J STMicroelectronics BAT54J
1 D2 Schottky, 30V, 1A
1 D3 Schottky, 30V, 1A
1 U1 Controller VFQFPN-24 PM6670S STMicroelectronics PM6670S
J1, J2, J3,
J4, J5, J6,
11
J7, J8, J9,
J10,J11
JP1, JP2,
5
1 JP5 PCB pads selector
1 TP6 Test point
1 SW1 Dip switch 2 DIP-2 Standard
JP3
Header, single pin
Jumper, 2x3,
100mils
Stmite
(DO216-AA)
Stmite
(DO216-AA)
STPS1L30M STMicroelectronics STPS1L30M
STPS1L30M STMicroelectronics N.M.
8/40
AN2808 Component assembly and layout
4 Component assembly and layout
Figure 3. Top side component placement
Figure 4. Top side view
9/40
Component assembly and layout AN2808
Figure 5. Layer 2 view
Figure 6. Layer 3 view
10/40
AN2808 Component assembly and layout
Figure 7. Bottom side view
Figure 8. Bottom side component placement
11/40
I/O interface AN2808
5 I/O interface
The PM6670S demonstration board has the following test points.
Table 2. PM6670S demonstration board input and output interface
Test point Description
VIN Battery input voltage positive terminal
PGND Battery input and VDDQ output common return
VDDQ VDDQ output
LDOIN LDO linear regulator input
VTT VTT output (LDO)
AGND VTT and VTTREF outputs common return
VTTREF VTTREF output
VCC +5 V supply, positive terminal
VCCGND Signal ground and VCC supply return
PG VDDQ output Power-Good signal
TP1 Connection point between power and signal grounds
6 Recommended equipment
● 4 to 28-V, 30 W power supply
● Active loads
● Digital mutimeters
● 200 MHz four-trace oscilloscope
12/40
AN2808 Configuration
7 Configuration
The PM6670S board includes four jumpers (JP1, JP2, JP3 and JP5) and two resistors,
which can be configured to select the desired mode of operation.
7.1 JP3 fixed or adjustable output voltage (mode pin)
The JP3 jumper is used to choose between a fixed output voltage (1.5 or 1.8 V) and a
user-defined output voltage in the range of 0.9 to 2.6 V. When connected in the lower
position, the fixed output voltage is selected and the voltage depends on the setting of the
DDRSEL pin (Section 7.2).
If JP3 is in the upper position, the output voltage is given by:
Equation 1
R8 R9+
VDDQ
ADJ
0.9
--------------------- -
⋅=
R8
Figure 9. JP3 (mode) setting
Both the R8 and R9 resistors are set to 39 kΩ (1.8 V by default) and can be changed by the
user.
13/40
Configuration AN2808
Non - Tracking Discharge
7.2 JP1 DDR2/DDR3 or power-saving mode (DDRSEL pin)
The JP1 jumper provides different options depending on the configuration of JP3. If the fixed
output voltage is selected (JP3 in the lower position), the user can choose between 1.8 V
(DDR2) or 1.5 V (DDR3), connecting JP1 as shown in Figure 10, and the pulse-skip mode is
set by default.
When the adjustable output voltage is selected (JP3 in the upper position), the same jumper
allows choosing between forced pulse width modulation (PWM), pulse-skip and non-audible
pulse-skip modes.
Figure 10. JP1 options when JP3 is in
the lower position
Figure 11. JP1 options when JP3 is in
1.8V output voltage
(default position)
1.5V output voltage
1.5V output voltage
AM00647v1
7.3 JP2 output discharge (DSCG pin)
The JP2 jumper is used to select the desired output discharge when both the S3 and S5
signals are tied low. In the upper position the outputs are not discharged at all, while in the
lower position the outputs are independently discharged using the internal MOSFETs (22 Ω
for VDDQ and VTT, 1.5 kΩ for VTTREF). When JP2 is in the central position, the trackingdischarge is programmed. This discharge mode relies on the LDOIN pin being connected to
the VDDQ output. See Section 10.7: VDDQ, VTT and VTTREF turn-off (soft end). If an
external rail is used to supply the LDO, the tracking discharge cannot be used as the device
can be damaged while attempting to sink 1 A from the LDO input.
the upper position
Forced PWM
(default position)
No Audible Pulse-Skip
Pulse-Skip
AM00648v1
14/40
Figure 12. JP2 (DSCG) setting
No Discharge
(default position)
AM00649v1
AN2808 Test setup
Virtual ESR Network
Integrative Compensation
(default position)
7.4 JP5 compensation network (COMP pin)
The JP5 jumper is located on the bottom side of the PM6670S board and is used to connect
the integrator input (COMP pin) to the output through a simple capacitor (integrative
compensation) or using the so-called "virtual ESR" network for very low-ESR output
capacitor applications (for example, all-ceramic output capacitor applications). The
integrative compensation is set by default.
Refer to the PM6670S datasheet for details on all-ceramic output capacitor applications and
the virtual-ESR design.
Figure 13. JP5 (COMP) setting
AM00650V1
8 Test setup
Figure 14 shows the suggested setup connections between the PM6670S board, the loads
and the external supply. The LDO input (LDOIN) is connected to VDDQ by default
(R6 = 0 Ω).
15/40
Test setup AN2808
Figure 14. PM6670S test setup
AM00651v1
16/40
AN2808 Getting started
9 Getting started
The following step-by-step power-up and power-down sequences are provided in order to
correctly evaluate the performance of the PM6670S board.
9.1 Power-up sequence
Working in an ESD-protected environment is highly recommended. Check all wrist straps
and mat earth connections before handling the PM6670S board. Connect the power
supplies as shown in the PM6670S test setup (Figure 14) and insert the meters in order to
perform the desired performance evaluation. Connect the scope probes as desired.
1. Set the JP1, JP2, JP3 and JP5 jumpers in order to properly configure the PM6670S
board.
2. Set the S3-S5 switches to the ON (upper) position. Do not change the jumper settings
when the board is powered.
3. Set the VCC supply to 5 V ± 5% and the current limit to 100 mA.
4. Set the VIN supply to a voltage in the range of 4.5 to 28 V. An initial test at 12 V and 3 A
current limit is suggested.
5. Set all the loads to 0 A.
6. Turn on the VIN supply.
7. Turn on the VCC supply.
8. Vary the VDDQ load from 0 A to 10 A.
9. Vary the VTT load from 0 A to 2 A to test the source capability. To test the sink
capability use the dashed VTT load shown in Figure 14.
10. Vary the VTTREF load to test the source capability.
11. Vary the VIN supply from 4.5 to 28 V.
9.2 Power-down sequence
1. Decrease the VTTREF and VTT loads to 0 A.
2. Reduce the VDDQ load to 5 A.
3. Decrease the VCC supply from 5 to 3.8 V in order to test the UVLO.
4. Increase the VCC supply from 3.8 to 5 V to restart the device.
5. Use the S3-S5 switches to enter/exit the S0-S3-S5 states.
6. Turn off the VDDQ load.
7. Turn off the VCC supply.
8. Turn off the VIN supply.
17/40
PM6670S evaluation tests AN2808
10 PM6670S evaluation tests
10.1 Turning on VDDQ, VTT and VTTREF (soft-start)
The VDDQ soft-start is divided into four steps. In each step, the current limit is increased by
¼ of the nominal value, as shown in Figure 15. VTT and VTTREF soft-starts are performed
at their maximum available current.
Figure 15. VDDQ soft-start at 150 mΩ load, pulse-skip mode
Figure 16. VDDQ turn-on (S5), pulse-skip mode
18/40
AN2808 PM6670S evaluation tests
Figure 17. VTT turn-on (S0), pulse-skip mode
10.2 VDDQ working mode
10.2.1 VDDQ forced pulse width mode
When the forced PWM working mode is selected (JP3 and JP1 in the upper position) the
inductor current is allowed to become negative and the following waveform can be captured.
Figure 18. VDDQ = 1.8 V, VIN = 12 V, IVDDQ = 0 A, forced PWM mode
10.2.2 VDDQ pulse-skip mode
The default working mode is the pulse-skip mode, in which the low-side MOSFET is turned
off when the inductor current becomes equal to zero. This configuration guarantees
maximum efficiency.
19/40
PM6670S evaluation tests AN2808
Figure 19. VDDQ = 1.8 V, VIN = 12 V, IVDDQ = 0.5 A, pulse-skip mode
10.2.3 VDDQ non-audible pulse-skip mode
To avoid a too low switching frequency, the non-audible pulse-skip mode can be selected
(JP3 in the upper position and JP1 in the middle). The minimum switching frequency
allowed is 33 kHz, as shown in Figure 20.
Figure 20. VDDQ = 1.8 V, VIN = 12 V, no load, no-audible pulse-skip mode (33 kHz)
20/40
AN2808 PM6670S evaluation tests
10.3 VDDQ, VTT and VTTREF load regulation
The following figures show the VDDQ, VTT and VTTREF output voltages against the load
currents. The switching section works in pulse-skip mode and directly feeds VTT LDO.
Figure 21. VDDQ load regulation, VIN = 12 V, pulse-skip mode
1,816
1,814
1,812
1,810
1,808
VDDQ [V]
1,806
1,804
1,802
1,800
0123 45678
Cur re nt [A]
Figure 22. VTT load regulation, LDOIN = VDDQ
0,930
0,920
0,910
0,900
VTT [V]
0,890
0,880
VD DQ
AM00652v1
VTT
0,870
-2,0 -1,5 -1,0 -0,5 0,0 0,5 1,0 1,5 2,0
Curre nt [A]
21/40
AM00653v1
PM6670S evaluation tests AN2808
Figure 23. VTT load regulation
0,907
0,906
0,905
0,904
0,903
VTTREF [V]
0,902
0,901
0,9
-30 -20 -10 0 10 20 30
Current [mA]
10.4 VDDQ and VTT load transient responses
Transient load responses are evaluated by loading the VDDQ and VTT output rails with a
current slew rate of 2.5 A/µs.
Figure 24. VDDQ load transient (VIN = 12 V, LOAD = 0 A -> 8 A at 2.5 A/µs),
pulse-skip mode
VTTREF
AM00654v1
22/40
AN2808 PM6670S evaluation tests
Figure 25. VTT load transient (VIN = 12 V, LOAD = -2 A -> 2 A at 2.5 A/µs),
pulse-skip mode
10.5 VDDQ efficiency
The three working modes lead to different power efficiencies. The test should be setup so
that VIN = 12 V, FSW = 400 kHz and VDDQ = 1.8 V. The following chart sums up the
results.
Figure 26. VDDQ efficiency vs. load
100%
90%
80%
70%
60%
50%
40%
Efficiency [%]
30%
20%
10%
0%
0,001 0,010 0,100 1,000 10,000
(a)
Forced PWM
No-Audible Pulse Skip
Pulse Skip
Output Curre nt [A]
a. Forced PWM (yellow), no-audible pulse-skip (green), pulse-skip (blue).
23/40
AM00656v1
PM6670S evaluation tests AN2808
10.6 VDDQ gate drivers
The PM6670S internal MOSFET driver turns on and off the high-side and low-side external
MOSFET, avoiding cross-conduction. In Figure 27 and Figure 28, the gate signals are
depicted in two different load conditions: without load and with load.
Figure 27. External MOSFET gate signal (VIN = 12 V, load = 0 A),
pulse-skip mode
Figure 28. External MOSFET gate signal (VIN = 12 V, load = 8 A),
pulse-skip mode
24/40
AN2808 PM6670S evaluation tests
10.7 VDDQ, VTT and VTTREF turn-off (soft end)
10.7.1 Tracking discharge
The JP2 jumper, if placed in the middle, allows the output tracking to be discharged. When
S3 and S5 are pulled down, VTT discharges VDDQ by sinking 1 A and, at the same time,
tracks the VDDQ half. When VDDQ reaches approximately 400 mV, the output discharge
MOSFETs are all closed and each rail is finally discharged.
Figure 29. VDDQ, VTTREF, VTT output voltages and LDO input current,
tracking discharge, no load on any rail
10.7.2 Non-tracking discharge
When the non-tracking discharge is programmed (JP2 in the lower position) and S3-S5 are
both tied to GND, each output rail is discharged through its discharge MOSFET, as depicted
in Figure 30.
25/40
PM6670S evaluation tests AN2808
Figure 30. VDDQ, VTTREF, VTT – no-tracking discharge, no load on any output
Table 3. Measured discharge resistance in soft-discharge mode
VDDQ output VTTREF output VTT output
Measured N.T.D. discharge
MOSFET’s R
DS(on)
25Ω 1.5kΩ 23Ω
10.8 UV, OV and thermal protections
10.8.1 Latched UV protection
If the output voltage is lower than the 70% nominal value, the under-voltage state is entered
and the discharge MOSFETs are turned on (as in the non-tracking soft end).
26/40
AN2808 PM6670S evaluation tests
Figure 31. UV protection, pulse-skip mode
10.8.2 Latched OV protection
If the output voltage is higher than the 115% nominal value, the over-voltage state is entered
and the low-side MOSFET is turned on. VTT and VTTREF are discharged through their
discharge MOSFETs.
Figure 32. OV protection, pulse-skip mode
10.9 VTT current limit (foldback)
VTT LDO has a foldback protection feature which reduces the current limit to 1 A when the
VTT output voltage is outside the ±10% optimum power window. The current limit is restored
to 2 A when the output voltage re-enters the optimum power window.
27/40
PM6670S evaluation tests AN2808
Input voltage (V)
Switching frequency (kHz)
Figure 33. VTT current limit during an output short
10.10 Switching frequency
10.10.1 Switching frequency vs input voltage
The constant on-time controller leads to a quasi-constant switching frequency, that more or
less follows the input voltage.
Figure 34. fsw vs input voltage, DDR2
480
460
440
420
400
380
360
340
320
300
0 5 10 15 20 25 30
(b)
AM00659v1
28/40
b. Forced PWM (blue), no-audible pulse-skip (purple) and pulse-skip (yellow). Switching frequency vs input
voltage, VDDQ = 1.8 V, IVDDQ = 7 A.
AN2808 PM6670S evaluation tests
500
Output current (A)
10.10.2 Switching frequency vs output current
The switching frequency can decrease to very low values in pulse-skip mode, whereas in
non-audible pulse-skip there is a lower limit (about 33 kHz). With increasing loads, however,
the switching frequency increases slightly as a consequence of conduction and switching
losses.
Figure 35. fsw vs iload, Vin = 12 V voltage, DDR2
450
400
350
300
250
200
150
100
Switching frequency (kHz)
50
0
0.001
10.11 Thermal behavior
The IC’s internal maximum and average temperature can be monitored by an IR camera.
For the following measures the test setup is:
● V
● F
● Pulse skip mode
● I
● VTT rail powered by VDDQ
● T
When the VTT current is increased, the IC temperature changes as shown in the following
charts.
=12 V
IN
SW
VDDQ
AMB
= 360 kHz
= 8 A
= 26° C
0.01
(c)
0.1
1
AM00660v1
c. Forced PWM (blue), no-audible pulse-skip (purple) and pulse-skip (yellow). Switching frequency vs output
current, VDDQ = 1.8 V, no load.
29/40
PM6670S evaluation tests AN2808
Figure 36. VTT current vs temperature, I
VTT
= 0 A
(d)
d. Average IC temperature = 37.5° C. Maximum internal IC temperature = 38.8° C.
30/40
AN2808 PM6670S evaluation tests
Figure 37. VTT current vs temperature, I
VTT
= 0.5 A
(e)
e. Average IC temperature = 46.2° C. Maximum internal IC temperature = 51.4° C.
31/40
PM6670S evaluation tests AN2808
Figure 38. VTT current vs temperature, I
VTT
= 1 A
(f)
f. Average IC temperature = 57.4° C. Maximum internal IC temperature = 67.8° C.
32/40
AN2808 PM6670S evaluation tests
Figure 39. VTT current vs temperature, I
VTT
= 1.5 A
(g)
10.12 DDR memories (VDDQ = 2.5 V) characterization
The PM6670S is also suitable for DDR memories with a VDDQ rail equal to 2.5 V. The VTT
linear regulator is always tracking VTTREF, a buffered replica of the VDDQ half, so the
termination rail is equal to 1.25 V as required by the DDR JEDEC standards (JESD79 and
JESD8-9 specifications).
The following graphs show each rail load regulation.
g. Average IC temperature = 67.9° C. Maximum internal IC temperature = 86.9° C.
33/40
PM6670S evaluation tests AN2808
Figure 40. VDDQ load regulation, Vin = 12 V and switching frequency 400 kHz
2.550
2.540
2.530
2.520
2.510
2.500
Voltage [V]
2.490
2.480
2.470
2.460
0.001
Forced PWM
Pulse Skip
NO AUD. PS
0.010
0.100 1.000
Current [A]
10.000
AM00661v1
Figure 41. VDDQ load regulation, Vin = 5 V and switching frequency 400 kHz
2.540
2.530
2.520
2.510
Forced PWM
Pulse Skip
NO AUD. PS
2.500
Voltage [V]
2.490
2.480
2.470
2.460
0.001 0.010 0.100 1.000 10.000
Current [A]
AM00662v1
34/40
AN2808 PM6670S evaluation tests
Figure 42. VTT load regulation
(h)
1.290
1.280
1.270
1.260
1.250
1.240
Vol tage [V]
1.230
1.220
1.210
1.200
-2.0 -1.5 -1.0 -0.5 0.0 0. 5 1.0 1.5 2.0
Figure 43. VTTREF load regulation
1.257
Current [A]
AM00664v1
(h)
1.256
1.255
1.254
1.253
1.252
1.251
Vol tage [V]
1.250
1.249
1.248
1.247
-30-20-10 0 10 20 30
Current [mA]
AM00665v1
The efficiency of the switching section is still very high, as shown by the following graphs in
which the VDDQ efficiency is computed against the load, with 12 and 5 V input voltages.
All of the three working modes (forced PWM, pulse skip and non-audible pulse skip) have
been tested.
h. LDOIN = VDDQ, input voltage 5 V, switching frequency 400 kHz, forced PWM mode.
35/40
PM6670S evaluation tests AN2808
Figure 44. Efficiency vs load – VDDQ = 2.5 V, Vin = 12 V
100
90
80
70
60
50
40
Efficiency [%]
30
20
10
0
0.001 0.010 0.100 1.000 10.000
Current [A]
Figure 45. Efficiency vs load – VDDQ = 2.5 V, Vin = 5 V
100
90
80
70
60
50
40
Efficiency [%]
30
Forced PWM
Pulse Skip
NO AUD. PS
AM00666v1
Forced PWM
Pulse Skip
NO AUD. PS
20
10
0
0.001 0.010 0.100 1.000 10. 000
When the input voltage is equal to 5 V the VDDQ rail efficiency is higher than 90%, with a
load greater than 4 mA. This can also be achieved with a very low load when the pulse skip
or non-audible pulse skip working mode is selected. The following two graphs show how the
switching frequency can change with the load: by decreasing the switching frequency the
regulator can greatly increase the efficiency.
36/40
Current [A]
AM00667v1
AN2808 PM6670S evaluation tests
Figure 46. SW efficiency vs load – VDDQ = 2.5 V, Vin = 12 V
5.00E+05
4.50E+05
4.00E+05
3.50E+05
3.00E+05
2.50E+05
2.00E+05
Frequency [Hz]
1.50E+05
1.00E+05
5.00E+04
0.00E+00
0.010 0.100 1.000 10.000
Current [A]
Figure 47. SW efficiency vs load – VDDQ = 2.5 V, Vin = 5 V
5.00E+ 05
4.50E+ 05
4.00E+ 05
3.50E+05
3.00E+05
2.50E+ 05
2.00E+ 05
Frequency [Hz]
1.50E+ 05
Forced PWM
Pulse Skip
NO AUD. PS
Forced PWM
Pulse Skip
NO AUD. PS
AM00668v1
1.00E+ 05
5.00E+ 04
0.00E+ 00
0.010 0.100 1.000 10.000
Current [A]
AM00669v1
The dynamic behavior of the PM6670S can be seen in the following figures, which show the
VDDQ and VTT load transient response with 5 V input voltage.
37/40
PM6670S evaluation tests AN2808
Figure 48. VDDQ load transient response
Figure 49. VTT load transient response
(j)
(i)
i. The load changes from 0 to 8 A at 2.5 A/µs, input voltage 5 V, switching frequency 400 kHz, pulse skip mode.
j. The load changes from -1.5 to 1.5 A at 2.5 A/µs, input voltage 5 V, switching frequency 400 kHz,
LDOIN = VDDQ pulse skip mode.
38/40
AN2808 Revision history
Revision history
Table 4. Document revision history
Date Revision Changes
14-Nov-2008 1 Initial release
39/40
AN2808
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