ST AN2808 Application note

AN2808
Application note

Complete DDR2/3 memory power supply controller

Introduction

The PM6670S device is a complete DDR2/3 power supply regulator for portable
applications designed to meet JEDEC specifications. It integrates a constant on-time (COT)
buck controller, a 2 Apk sink/source low dropout regulator (LDO) and a 15 mA low noise
buffered reference.

The COT architecture ensures a fast transient response supporting both polymeric and
ceramic output capacitors. An embedded integrator control loop compensates the DC
voltage error caused by the output ripple. The 2 Apk sink/source linear regulator provides
the memory termination voltage with a fast load transient response.

The device is fully compliant with system sleep states S3, S4 and S5, setting the LDO
output to high-impedance in the suspend-to-RAM state, and performing the tracking
discharge of all outputs in the suspend-to-disk state.

Figure 1. PM6670S demonstration board

November 2008 Rev 1 1/40

www.st.com

Contents AN2808

Contents

1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 Switching section (VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 Reference and termination voltages (VTTREF and VTT) . . . . . . . . . . . . . 5

2 Demonstration kit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Component assembly and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 Recommended equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.1 JP3 fixed or adjustable output voltage (mode pin) . . . . . . . . . . . . . . . . . . 13

7.2 JP1 DDR2/DDR3 or power-saving mode (DDRSEL pin) . . . . . . . . . . . . . 13

7.3 JP2 output discharge (DSCG pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.4 JP5 compensation network (COMP pin) . . . . . . . . . . . . . . . . . . . . . . . . . 14

8 Test set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

9 Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

9.1 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

9.2 Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10 PM6670S evaluation tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

10.1 VDDQ, VTT and VTTREF turn on (Soft Start) . . . . . . . . . . . . . . . . . . . . . 17

10.2 VDDQ working mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

10.2.1 VDDQ forced PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

10.2.2 VDDQ pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

10.2.3 VDDQ no-audible pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

10.3 VDDQ, VTT and VTTREF load regulation . . . . . . . . . . . . . . . . . . . . . . . . 19

10.4 VDDQ and VTT load transient responses . . . . . . . . . . . . . . . . . . . . . . . . 21

2/40

AN2808 Contents

10.5 VDDQ efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

10.6 VDDQ gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10.7 VDDQ, VTT and VTTREF turn off (soft end) . . . . . . . . . . . . . . . . . . . . . . 23

10.7.1 Tracking discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10.7.2 Non-traking discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

10.8 UV, OV and thermal protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10.8.1 Latched UV protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10.8.2 Latched OV protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10.9 VTT current limit (foldback) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10.10 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.10.1 Switching frequency vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.10.2 Switching frequency vs output current . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.11 Thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10.12 DDR memories (VDDQ = 2.5 V) characterization . . . . . . . . . . . . . . . . . . 32

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3/40

List of figures AN2808

List of figures

Figure 1. PM6670S demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. Demonstration schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Top slide component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Top slide view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. Layer 2 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6. Layer 3 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. Bottom side view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 8. Bottom side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 9. JP3 (mode) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 10. JP1 options when JP3 is in the lower position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 11. JP1 options when JP3 is in the upper position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 12. JP2 (DSCG) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 13. JP5 (COMP) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 14. PM6670S test set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 15. VDDQ Soft Start @150mW load, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 16. VDDQ turn on (S5), pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 17. VTT turn on (S0), pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 18. VDDQ=1.8V , VIN=12V, IVDDQ=0A, forced-PWM mode. . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 19. VDDQ=1.8V, VIN=12V, IVDDQ=0.5A, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 20. VDDQ=1.8V, VIN=12V, no load, no-audible pulse-skip mode (33kHz) . . . . . . . . . . . . . . . 18

Figure 21. VDDQ load regulation - VIN=12V, pulse-skip mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 22. VTT load regulation - LDOIN=VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 23. VTT load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 24. VDDQ load transient (VIN=12V, LOAD=0A->8A @2.5A/ms). Pulse-skip mode. . . . . . . . . 20

Figure 25. VTT load transient (VIN=12V, LOAD=-2A->2A @2.5A/ms). Pulse-skip mode. . . . . . . . . . 21

Figure 26. VDDQ efficiency vs. load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 27. External MOSFET gate signal (VIN=12 V, load= 0 A). Pulse-skip mode . . . . . . . . . . . . . . 22

Figure 28. External MOSFET gate signal (VIN=12 V, load= 8 A). Pulse-skip mode . . . . . . . . . . . . . . 22

Figure 29. VDDQ, VTTREF, VTT output voltages anl LDO input current. Tracking discharge. No load on

any rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 30. VDDQ, VTTREF, VTT. No-tracking discharge. No load on any output. . . . . . . . . . . . . . . . 23

Figure 31. UV protection, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 32. OV protection, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 33. VTT current limit during an output short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 34. fsw vs input voltage, DDR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 35. fsw vs iload, Vin = 12V voltage, DDR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 36. VTT current vs temperature , IVTT= 0 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 37. VTT current vs temperature, IVTT= 0.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 38. VTT current vs temperature, IVTT= 1 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 39. VTT current vs temperature, IVTT= 1.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 40. VDDQ load regulation, Vin = 12 V and switching frequency 400 kHz . . . . . . . . . . . . . . . . 32

Figure 41. VDDQ load regulation, Vin = 5 V and switching frequency 400 kHz . . . . . . . . . . . . . . . . . 32

Figure 42. VTT load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 43. VTTREF load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 44. Efficiency vs load - VDDQ = 2.5 V, Vin = 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 45. Efficiency vs load - VDDQ = 2.5 V, Vin = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 46. SW efficiency vs load - VDDQ = 2.5 V, Vin = 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 47. SW efficiency vs load - VDDQ = 2.5 V, Vin = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 48. VDDQ load transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 49. VTT load transient response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4/40

AN2808 Main features

1 Main features

1.1 Switching section (VDDQ)

● 4.5 to 28-V input voltage range

● 0.9 V, ±1% voltage reference

● 1.8 V (DDR2) or 1.5 V (DDR3) fixed output voltages

● 0.9 to 2.6 V adjustable output voltage

● 1.237 V ± 1% reference voltage available

● Very fast load transient response constant on-time control loop

● No-RSENSE current sensing using low-side MOSFETs' R

●

Negative current limit

● Latched OVP, UVP and thermal shutdown

● Fixed 3 ms Soft-Start

● Selectable pulse-skipping at light loads

● Selectable non-audible (33 kHz) pulse-skip mode

● All ceramic output capacitor applications supported

● Output voltage ripple compensation

DS(on)

1.2 Reference and termination voltages (VTTREF and VTT)

● 2 A peak LDO with foldback for VTT

● Remote VTT output sensing

● High-Z VTT output in S3

● Ceramic output capacitors supported

● ±15 mA low-noise buffered reference for VTTREF

5/40

Demonstration kit schematic AN2808

DD

11

66

0S

24

23

22

21

20

19

18

17

16

15

14

13

12
11
10

AV

DD

SE

25

10

BA

54J

30k

18k

1u

0u

0u

220u

0u

10

100n

0n

10u

10

10

00p

5k

8k

47n

68

0u

0u

22

00p

33n

0n

13

00k

DD

SE

PS

30A

39k

39k

10

18

2 Demonstration kit schematic

Figure 2. Kit schematic

Q

1L30A

VDD

STPS

1

D3

2 1

220u

C4

12

C3

220u

12

2

R15 6. 8k

1 2

C15 47n

1

R14 7.5k

8
7
6
5

Q2

4

R17 0

C1313100n

0

1 2

R3 1k2

VCC

18

17

VCC

CSNS

19

PHASASE

20

HGATE

21

BOOT

22

LDOIN

23

VTT

24

U1

VTTGND1THPD

2

25

0

10u

0

10u

1n

R16

4R7

12

STPSPS1L3L30M

D2

2 1

3
2
1

S12NH3LL

VCC

0k

0k

R12 10

R11 10

1 2

1 2

12

12

C2121100p

16

14

15

PG

PGND

LGATE

70S

PM66

L

RSE

VTTREF4DD

VTTSNS

5

3

DSCG

13

S3

S5

DSCG

12

COMP

11

MODE

10

VSVSNS

9

VOSC

8

VREF

7

CC
AV

SGND

6

12

100n

C10

12

C8

12

1 C18

J8

VTTREF

R6

0 0

8
7
6
5

Q1

0

0

12

R10100 C12

0

J6

J2

0

L1 1u

S12NH3LL

3
2
1

4

R4 3R3

1 2

1 2

0n
10

0

C202010u

12

C191910u

12

C7

12

C6

12

1

1

J7

VTT

LDOIN

J1

VIN

1

C2

10u

12

12

C1

10u

R1 330k

1 2

C1414100n

12

12

R2

18k

T54J

D1

BA

21

VCC

C111110u

12

R7

3R9

12

VCC

C5

1u

12

1

1

J5

J9

VCC

VCCGND

J3

PGND

J4

1

GND_TP

TP1

12

100k

R13

SW1

2

3

1

4

C22

100p

0

JP2

5 6
3 4
1 2

JP3

MODE

R9

39k

R8

C9

L

RSE

JP1

DD

5 6
3 4
1 2

33n

0

J10

AGND 1

PG

1

JP5

INT_CER

0p

0

1 2

C16 68

0

12

0

C17

0

39k

0

0

0

J11

AGND 1

6/40

AM00646v1

AN2808 Component list

3 Component list

Table 1. BOM list

Qty. Component Description Package P/n Manufacturer Value

2C1, C2

2C3, C4

1C5

3 C6, C7, C11

1C8

4

1C12

1C15

1C16

C9, C10,

C13, C14

Ceramic, 50V,
X5R, 20%

POSCAP, 4V,
15mΩ, 20%

Ceramic, 6.3V,
X5R, 10%

Ceramic, 6.3V,
X5R, 10%

Ceramic, 50V,X7R,
20%

Ceramic, 50V,
X7R, 20%

Ceramic, 50V,
X7R, 10%

Ceramic, 50V,
X7R, 10%

Ceramic, 50V,
X7R, 10%

SMD 1210 UMK325BJ106KM-T Taiyo Yuden 10 µF

SMD 7343

(D)

SMD 1206 Standard 1 µF

SMD 0805 JMK212BJ106KG-T Taiyo Yuden 10 µF

SMD 0603 Standard 33 nF

SMD 0603 Standard 100 nF

SMD 0805 Standard 100 nF

SMD 0603 Standard 6n8

SMD 0603 Standard 680 pF

4TPE220MF Sanyo 220 µF

1 C17 Ceramic, 20% SMD 0603 Standard N.M.

1C18

2C19, C20

2C21, C22

1R1

1R2

1R3

1R4

1R6

1R7

Ceramic, 50V,
X7R, 10%

Ceramic, 6.3V,
X5R, 10%

Ceramic, 50V,
X7R, 10%

Chip resistor,

0.1W, 1%

Chip resistor,

0.1W, 1%

Chip resistor,

0.1W, 1%

Chip resistor,

0.1W, 1%

Chip resistor,

0.1W, 1%

Chip resistor,

0.1W, 1%

SMD 0603 Standard 1 nF

SMD 0805 JMK212BJ106KG-T Taiyo Yuden N.M.

SMD 0603 Standard 100 pF

SMD 0603 Standard 330 kΩ

SMD 0603 Standard 18 kΩ

SMD 0603 Standard 1k2

SMD 0603 Standard 3R3

SMD 0805 Standard 0

SMD 0603 Standard 3R9

7/40

Component list AN2808

Table 1. BOM list (continued)

Qty. Component Description Package P/n Manufacturer Value

1R8

1R9

1R10

R11, R12,

3

1R14

1R15

1R16

1R17

1L1

1 Q1 N-channel, 30V SO-8 STS12NH3LL STMicroelectronics STS12NH3LL

1 Q2 N-channel, 30V SO-8 STS12NH3LL STMicroelectronics STS12NH3LL

R13

Chip resistor,

0.1W, 1%

Chip resistor,

0.1W, 1%

Chip resistor,

0.1W, 1%

Chip resistor,

0.1W, 1%

Chip resistor,

0.1W, 1%

Chip resistor,

0.1W, 1%

Chip resistor,

0.1W, 1%

Chip resistor,

0.1W, 1%

SMT, 12.4Arms,

3.46mΩ

SMD 0603 Standard 39 kΩ

SMD 0603 Standard 39 kΩ

SMD 0603 Standard 0

SMD 0603 Standard 100 kΩ

SMD 0805 Standard 7k5

SMD 0603 Standard 6k8

SMD 0603 Standard 4R7

SMD 0603 Standard 0

15.0x13.2mm MLC1538-102MX Coilcraft 1 µH

1 D1 Schottky, 30V, 0.3A SOD-323 BAT54J STMicroelectronics BAT54J

1 D2 Schottky, 30V, 1A

1 D3 Schottky, 30V, 1A

1 U1 Controller VFQFPN-24 PM6670S STMicroelectronics PM6670S

J1, J2, J3,
J4, J5, J6,

11

J7, J8, J9,

J10,J11

JP1, JP2,

5

1 JP5 PCB pads selector

1 TP6 Test point

1 SW1 Dip switch 2 DIP-2 Standard

JP3

Header, single pin

Jumper, 2x3,
100mils

Stmite

(DO216-AA)

Stmite

(DO216-AA)

STPS1L30M STMicroelectronics STPS1L30M

STPS1L30M STMicroelectronics N.M.

8/40

AN2808 Component assembly and layout

4 Component assembly and layout

Figure 3. Top side component placement

Figure 4. Top side view

9/40

Component assembly and layout AN2808

Figure 5. Layer 2 view

Figure 6. Layer 3 view

10/40

AN2808 Component assembly and layout

Figure 7. Bottom side view

Figure 8. Bottom side component placement

11/40

I/O interface AN2808

5 I/O interface

The PM6670S demonstration board has the following test points.

Table 2. PM6670S demonstration board input and output interface

Test point Description

VIN Battery input voltage positive terminal

PGND Battery input and VDDQ output common return

VDDQ VDDQ output

LDOIN LDO linear regulator input

VTT VTT output (LDO)

AGND VTT and VTTREF outputs common return

VTTREF VTTREF output

VCC +5 V supply, positive terminal

VCCGND Signal ground and VCC supply return

PG VDDQ output Power-Good signal

TP1 Connection point between power and signal grounds

6 Recommended equipment

● 4 to 28-V, 30 W power supply

● Active loads

● Digital mutimeters

● 200 MHz four-trace oscilloscope

12/40