ST AN2787 APPLICATION NOTE

AN2787

Application note

Monolithic VR demonstration board for chipset and DDR2/3 supply for ultramobile PC (UMPC) applications

Introduction

PM6641 demonstration board order code: STEVAL-ISA050V1 (previously coded as PM6641EVAL).

The PM6641 demonstration board is a monolithic voltage regulator (VR) module with internal power MOSFETs, specifically designed to supply DDR2/3 memory and chipset in ultramobile PC and real estate constrained portable systems.

It integrates three independent, adjustable, constant frequency buck converters, a ±2 Apk low dropout (LDO) linear regulator, and a ±15 mA low-noise buffered reference.

Each regulator is provided with basic undervoltage (UV) and overvoltage (OV) protections, programmable soft-start and current limit, active soft-end, and pulse skipping at light loads.

This document describes all features of the PM6641 demonstration board.

Figure 1. PM6641 demonstration board

September 2008

Rev 1

1/37

www.st.com

Contents	AN2787

Contents

1	Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
2	Demonstration kit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 7
3	Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
4	Component assembly and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
5	I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
6	Recommended equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
7	Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
	7.1	JP1 VDDQ output discharge (DSCG pin) . . . . . . . . . . . . . . . . . . . . . . . . .	15
	7.2	JP3 switching regulator phase control (SET_PH1 pin) . . . . . . . . . . . . . .	15
	7.3	JP4 1.8 V (VDDQ) external/internal divider (VFB_1S8 pin) . . . . . . . . . . .	16
	7.4	JP5 1.5 V external/internal divider (VFB_1S5 pin) . . . . . . . . . . . . . . . . . .	17
	7.5	JP6 1.05 V external/internal divider (VFB_1S05 pin) . . . . . . . . . . . . . . . .	17
	7.6	JP7 current limit (CSNS pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
8	Test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
9	Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
10	STEVAL-ISA050V1 evaluation tests . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
	10.1	SW regulators turn-on (soft-start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
	10.2	SW regulator - working mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	10.3	Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
	10.4	Load transient responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	10.5	Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
	10.6	Phase management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
	10.7	Fault management (OVP, UVP, UVLO, thermal) . . . . . . . . . . . . . . . . . . .	30
	10.8	SW regulators current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
	10.9	Soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33

2/37

AN2787		Contents
	10.10 Thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 35
11	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 36

3/37

List of figures	AN2787

List of figures

Figure 1.	PM6641 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 1
Figure 2.	PM6641 demonstration board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 7
Figure 3.	Top side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
Figure 4.	Top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
Figure 5.	Layer 2 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
Figure 6.	Layer 3 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
Figure 7.	Bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
Figure 8.	Bottom side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
Figure 9.	JP1 DSCG pin setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
Figure 10.	JP3 phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 11.	JP4 1.8 V divider selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 12.	JP5 1.5 V divider selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
Figure 13.	JP6 1.05 V divider selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
Figure 14.	PM6641 demonstration board programmed current limit vs. CSNS resistor . . . . . . . . . . .	18
Figure 15.	JP8 setting switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
Figure 16.	PM6641 demonstration board test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
Figure 17.	VDDQ turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
Figure 18.	VDDQ, VTT and VTTREF turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
Figure 19.	PWM mode: VDDQ output voltage, phase voltage and inductor current, current
	load = 2.3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
Figure 20.	Pulse skip mode: VDDQ output voltage, phase voltage and inductor current, current
	load = 0 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
Figure 21.	Forced PWM mode (soft OV): VDDQ output voltage, phase voltage, inductor current
	and Power Good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
Figure 22.	VDDQ (1.8 V) load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
Figure 23.	1.5 V load regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
Figure 24.	1.05 V load regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 25.	VTT load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 26.	VTTREF load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 27.	VDDQ, VTT and VTTREF, VDDQ load transient response, IVDDQ = 0 to
	2.3 A at 2.5 A/µs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Figure 28.	1.5 V output voltage and inductor current, 1.5 V rail load transient response,
	1.5 V = 0 to 1.25 A at 2.5 A/µs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Figure 29.	1.05 V output voltage and inductor current, 1.05 V rail load transient response.
	I1.05 V = 0 to 1.75 A at 2.5 A/µs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Figure 30.	VDDQ, VTTREF, VTT and VTT output current, VTT rail load transient response,
	IVTT = –1 A to +1 A at 2.5 A/µs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Figure 31.	SW regulators efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
Figure 32.	SW regulators phases, 120 deg phase shift. SETPH1 pin tied to AGND . . . . . . . . . . . . . .	29
Figure 33.	SW regulators phases, no phase shift - synchronous clock, SETPH1 pin tied to AVCC . .	30
Figure 34.	VDDQ, VTT, VTTREF output voltage, VDDQ temporarily shorted to 3.3 V, output
	overvoltage protection triggered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
Figure 35. VDDQ, VTT, VTTREF output voltage and VDDQ inductor current, VDDQ feedback pin
	temporarily shorted to GND, output undervoltage protection triggered . . . . . . . . . . . . . . .	31
Figure 36.	VDDQ (1.8 V), 1.5 V, 1.05 V output voltage and AVCC input power supply, input
	undervoltage lockout triggered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 37.	VDDQ (1.8 V), 1.5 V, 1.05 V and VTT rails output voltage, thermal shutdown triggered . .	32
Figure 38.	1.5 V rail output voltage, 1.5 V inductor current and output current, peak current limit

4/37

AN2787		List of figures
	reached. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . 33
Figure 39.	VDDQ(1.8 V), VTT and VTTREF rail output voltage, EN_1S8 and EN_VTT tied to
	AGND - soft off with tracking discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . 34
Figure 40.	VDDQ(1.8 V), VTT and VTTREF rail output voltage. EN_1S8 and EN_VTT tied to
	AGND - soft off without tracking discharge. . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . 34
Figure 41.	PM6641 demonstration board surface temperature when loaded with typical currents,
	Tamb = 23 °C, VIN = 3.3 V, FSW = 660 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . 35

5/37

Main features	AN2787

1 Main features

Switching section

●0.8 V ±1% voltage reference

●2.7 V to 5.5 V input voltage range

●Fast response, constant frequency, current mode control

●Three independent, adjustable, SMPS for DDR2/3 (VDDQ) and chipset supply

●S3-S5 states compliant with DDR2/3 section

●Active soft-end for all outputs

●Selectable tracking discharge for VDDQ

●Separate Power Good signals

●Pulse skipping at light load

●Programmable current limit and soft-start for all outputs

●Latched OVP, UVP protection

●Thermal protection

Reference and termination voltages (VTTREF and VTT)

●±2 Apk LDO for DDR2/3 termination (VTT) with foldback

●Remote VTT output sensing

●High-Z VTT output in S3

●±15 mA low-noise DDR2/3 buffered reference (VTTREF)

6/37

2

AN2787

AVCC

TP1

schematic board demonstration PM6641 .2 Figure

schematic kit Demonstration

TP5

TP6

TP15

TP14

TP16

3

VTTREF

VCC

AGND

LDOIN

VTT

AGND

JP1

TP18

1

1

1

STRIP 3

2

1

1

1

AUX

1

0603-join

1

R2

AVCC

AUX

VCC

0603-4R3

JP3

R34

R1

2

STRIP 3

C1

0603-4R3

C17

AVCC

0603-100n

1

0603-1u

C11

C16

1206-22u

2

0603-100n

AUX

TP9

C18

VOUT_1S8

0603-33n

R20

R21

R22

R23

SW1

1

AVCC

AVCC

0603-68k

0603-68k

0603-68k

0603-68k

1

8

JP7

JP8

2

7

3

6

1

1

AVCC

4

5

R5

2

2

C25

C26

C27

C28

SW DIP-4

0603-150k

C12

STRIP 2

STRIP 2

0805-10u

0603-100p

0603-100p

0603-100p

0603-100p

R6

JP4

0603-120k

R3

R4

VIN

2

STRIP 3

0603-100k

0603-68k

R33

0603-join

C3

TP10

48

47

46

45

44

43

42

41

40

39

38

37

0805-10u

VOUT_1S5

1

VCC

DSCG VTTREF

LDO IN VTT VTT GND AVCC AGND 2

EN 1S8

+

C5

EL SMD C-10u

C15

L2

TP8

C6

B Case - 220u

1

36

1

2

R7

GND

B Case - 220u

AGND_1

EN_VTT

0603-100k

2

35

2839-1u5

3

SET_SWF

EN_1S5

34

+

C8

4

VOUT_1S8

U1

EN_1S05

33

C7

EL SMD C-10u

JP5

R8

5

CSNS

VIN_1S5

32

B Case - 220u

0603-120k

1

L1

6

SGND_1S8_1

VSW_1S5_2

31

2

STRIP 3

2

7

SGND_1S8_2

VSW_1S5_1

30

8

VSW_1S8_1

PM6641_QFPN

SGND_1S5_2

29

R12

C23

TP11

C2

2839-1u

9

VSW_1S8_2

SGND_1S5_1

28

0603-47k

0603-470p

GND

31

21

0805-10u

10

VIN_1S8_1

SS 1S8 SS 1S05 VTTFB

VFB_1S5

27

31

11

VIN_1S8_2

COMP_1S5

26

C30

VIN

12

VFB_1S8

SS_1S5

25

COMP_1S8

PG_1S5

C34

0603-100p

1

COMP 1S05 VFB 1S05

SGND 1S051 SGND 1S052 VSW 1S051 VSW 1S052 VIN 1S05 1 VIN 1S05PH1SET2 PG 1S05AGND3 PG 1S8

12

31

1

C29

0603-15p

R11

R32

49

THERMAL

0603-100p

0603-100k

C32

C20

0603-15p

0603-join

13

14

15

16 17

18

19

20

21

22 23

24

0603-22n

C22

0603-330p

Demonstration

C19

0603-22n

R13

C33

1 2

L3

VIN

0603-15p

C31

0603-68k

2839-1u

C21

C24

0603-100p

0603-22n

C4

TP3

TP2

TP4

0603-330p

AUX

0805-10u

PG_1S5

PG_1S8

PG_1S05

1

R17

R18

R19

1

1

1

+

C13

0603-68k

0603-68k

0603-68k

C9

C10

EL SMD C-10u

B Case - 220u

C14

B Case - 220u

2

1

2

kit

+

R9

EL SMD C-10u

0603-56k

schematic

TP12

TP13

TP17

TP7

R10

1

1

1

JP6

1

2

0603-180k

STRIP 3

VOUT_1S05

GND

GND

1 3

VIN

R31

0603-join

R30

7/37

0603-join

VCC

Bill of material	AN2787

3 Bill of material

Table 1.		PM6641 demonstration board list of components
Qty	Component		Description	Package	Part number	MFR	Value	Note
1		C1	Ceramic, 10 V,	SMD 0603		Standard	1 µ
			X5R, 20%
4	C2, C3, C4,		Ceramic, 10 V,	SMD 0805	GRM21BR61A106KE19	Murata	10 µ
		C12	X5R, 20%
4	C5, C8, C13,			SMD C case				n.m.
		C14
5	C6, C7, C9,		Ceramic, 4 V,	SMD 1206	AMK316BJ107ML	Taiyo Yuden	100 µ
	C10, C15		X5R, 20%
1		C11	Ceramic, 6.3 V,	SMD 1206	GRM31CR60J226KE19	Murata	22 µ
			X5R, 10%
2	C16, C17		Ceramic, 16 V,	SMD 0603		Standard	100 n
			X7R, 10%
1		C18	Ceramic, 25 V,	SMD 0603	GRM188R71E333KA01	Murata	33 n
			X7R, 10%
3	C19, C20,		Ceramic, 16 V,	SMD 0603		Standard	22 n
		C21	X7R, 10%
2	C22, C24		Ceramic, 50 V,	SMD 0603		Standard	330 pF
			C0G, 5%
1		C23	Ceramic, 50 V,	SMD 0603		Standard	470 pF
			C0G, 5%
4	C25, C26,		Ceramic, 50 V,	SMD 0603		Standard	100 pF
	C27, C28		C0G, 5%
3	C29, C30,		Ceramic, 50 V,	SMD 0603				n.m.
		C31	C0G, 5%
3	C32, C33,		Ceramic, 50 V,	SMD 0603				n.m.
		C34	C0G, 5%
2		R1, R2	Chip resistor,	SMD 0603		Standard	3R3
			0.1 W, 1%
1		R3	Chip resistor,	SMD 0603		Standard	100 kΩ
			0.1 W, 1%
	R4, R13
	R17, R18,		Chip resistor,				68 kΩ
9	R19, R20,			SMD 0603		Standard
			0.1 W, 1%
	R21, R22,
		R23
1		R16	Chip resistor,	SMD 0603				n.m.
			0.1 W, 1%
1		R5	Chip resistor,	SMD 0603		Standard	150 kΩ
			0.1 W, 1%

8/37

AN2787							Bill of material
Table 1.		PM6641 demonstration board list of components (continued)
Qty	Component		Description	Package	Part number	MFR		Value	Note
2	R6, R8		Chip resistor,	SMD 0603		Standard		120 kΩ
			0.1 W, 1%
1	R7		Chip resistor,	SMD 0603		Standard		100 kΩ
			0.1 W, 1%
1	R9		Chip resistor,	SMD 0603		Standard		56 kΩ
			0.1 W, 1%
1	R10		Chip resistor,	SMD 0603		Standard		180 kΩ
			0.1 W, 1%
1	R11		Chip resistor,	SMD 0603		Standard		100 kΩ
			0.1 W, 1%
1	R12		Chip resistor,	SMD 0603		Standard		47 kΩ
			0.1 W, 1%
3	R32, R33,		Chip resistor,	SMD 0603		Standard		0 Ω	short
	R34		0.1 W, 1%
2	R30, R31		Chip resistor,	SMD 0603					n.m.
			0.1 W, 1%
2	L1, L3		SMT 11Arms,	SMD 2827	744312100 /LF	Würth		1.0 µH
			9.5 mΩ
1	L2		SMT 9 Arms,	SMD 2827	744312150 /LF	Würth		1.5 µH
			10.5 mΩ
1	U1		IC VR - 48-pin	VFQFPN 7x7	PM6641	STMicroelectronics
	JP1,	JP3,
5	JP4, JP5,		Header, 3-pin	SIP3
	JP6
2	JP7, JP8		Header, 2-pin	SIP2
	TP1, TP2,		Header, single
5	TP3, TP4,
			pin
	TP18
	TP5, TP6,
	TP7, TP8,
	TP9, TP10,
13	TP11, TP12,		Test point
	TP13, TP14,
	TP15, TP16,
	TP17
1	SW1		Switch 4-SPST	DIP-8		Standard

9/37

Component assembly and layout	AN2787

4 Component assembly and layout

Figure 3. Top side component placement

Figure 4. Top view

10/37

AN2787	Component assembly and layout

Figure 5. Layer 2 view

Figure 6. Layer 3 view

11/37

Component assembly and layout		AN2787
	Figure 7. Bottom view

Figure 8. Bottom side component placement

12/37