PM8800 demonstration kit for standard and high power PoE
PD interface and power supply, with auxiliary sources
Introduction
This document details the characteristics and performances of the PM8800 demonstration
kit which has been designed to cover a broad range of power over Ethernet (PoE)
applications. PM8800 is a highly integrated device embedding an IEEE802.3af compliant
powered device (PD) interface together with a PWM controller and support for auxiliary
sources.
Even though PM8800 can be configured to work in both isolated and non-isolated
topologies, this application note focuses on an isolated topology only, in two different output
power configurations (10 W and 20 W) and 2 different output voltages (5 V and 3.3 V).
The PM8800 demonstration kit supports diode as well as synchronous rectification.
Auxiliary sources can be connected to the board on 2 input points. One input allows
prevalence of the auxiliary sources with respect to the PoE, while the other input allows the
usage of a wall adaptor with voltage lower than the internal PoE UVLO threshold and still
benefits from the inherent inrush and DC current limit.
The above mentioned configurations are all supported by the PM8800 demonstration kit as
options on the same PCB. The bill of material (BOM) (see Section 5 on page 12) provides
the list of components to be mounted for each of the targeted configurations.
Figure 1.PM8800 demonstration kit
The high-power board appears on the left of the photo and standard board is on the right.
Figure 49.Switch between 48 V PoE and 24 V AUXII with 3.3 V at 2 A . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 50.Back to 48 V removing the 24 V AUXII voltage with 3.3 V at 2 A . . . . . . . . . . . . . . . . . . . . 41
Figure 51.Switch between 48 V PoE and 12 V AUXII with 3.3 V at 2 A . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 52.Back to 48 V removing the 12 V AUXII voltage with 3.3 V at 2 A . . . . . . . . . . . . . . . . . . . . 41
Figure 53.Schematic of the 3.3/5 Vout high power with synchronous rectification . . . . . . . . . . . . . . . 44
Figure 54.Schematic of the 3.3/5 Vout standard power with diode rectification . . . . . . . . . . . . . . . . . 45
5/47
Main featuresAN2783
1 Main features
The PM8800 demonstration kit has been designed to cover several PoE configurations with
easy customization.
●Basic configuration: (high-power applications)
–5 V output
–Up to 4 A output
–250 kHz operating switching frequency
–Flyback topology DCM/CCM
●Board size 70 x 90 mm
●Power Good indication
●Overall efficiency of 85% at full-load condition (Figure 12)
●Prevalence of the auxiliary source with respect to the PoE line (Section 8.7)
●1500 Vrms isolation ensured by the power transformer
●Support for (see BOM options in Section 5):
–5 V and 3.3V output
–diode or synchronous rectification
–standard IEEE802.3af or high-power applications
–non-isolated flyback topology
●Support for class 0-3 (IEEE802.3af) and class 4 (pre-standard modes)
The following 2 basic board configurations are addressed with the same PCB and referred
in the rest of the text as:
–Standard power: this configuration covers IEEE802.3af applications and it is
based on flyback topology with diode rectification.
–High power: this configuration targets applications with output power in excess of
the IEEE802.3af standard up to 20 W as output. This configuration is based on
flyback topology with synchronous rectification. The same configuration can be
used in PoE designs targeting high efficiency and/or with wide range auxiliary
input (down to 12 V with prevalence of the auxiliary with respect to PoE).
6/47
AN2783Electrical specifications
2 Electrical specifications
Table 1.Specifications
Parameter10 W20 W
VIN30 V to 60 V at 10 W output30 V to 60 V at 20 W output
Auxiliary VIN AUXI 18 V to 60 V18 V to 60 V
Auxiliary VIN AUXII12 V to 60 V12 V to 60 V
VOUT
Peak-to-peak output
ripple
3.35 V +/- 100 mV at 3 A3.35 V +/- 100 mV at 6 A
5.05 V +/- 100 mV at 2 A5.05 V +/- 100 mV at 4 A
10 mVpp20 mVpp
Efficiency DC-DC only
Overall efficiency
Switching frequency250 kHz typ +/- 10%250 kHz typ +/- 10%
Dynamic current step
Maximum overshoot200 mV400 mV
Maximum overshoot
time duration
Maximum undershoot200 mV400 mV
Maximum undershoot
time duration
Maximum DC test
current
Minimum DC test
current
83% typ at 3.3 V 3 A86% typ at 3.3 V 6 A
87% typ at 5 V 2 A88% typ at 5 V 4 A
78% typ at 3.3 V 3 A81% typ at 3.3 V 6 A
81% typ at 5 V 2 A84% typ at 5 V 4 A
1- 3 A max at 3.3 V1- 6 A max at 3.3 V
1- 2 A max at 5 V1- 4 A max at 5 V
200 ms300 ms
200 ms300 ms
3.5 A at 3.3 V6.5 A at 3.3 V
2.5 A at 5 V4.5 A at 5 V
00
7/47
Demonstration kit schematicAN2783
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g
g
k
k
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k
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M
3 Demonstration kit schematic
Figure 2.Demonstration kit schematic
J5
1
2
DC OUTPU T
0.1u
C39
TP14
OUTOUTOUT
1k
R17
RJ45 D ata Jac
10
Chassis
1
234
1
2
4
5
12
13
T3
16
1
234
Chassis
10
RJ45 D at a and Po wer Jac
T
J2
9
Chassis
OUTPU
5
6
7
8
0
R1
0805
R7NM
6
M
R
N
6
3
7
89
H2019 / TLA-6T127LF
10
111415
567
8
Chassis
T
9
J1
INPU
Chassis
0
1206
R30
0805
C7NM0805
200V
Chassis
5
C6
200V
080
NM
0805
To be placed on sol der si de
Termination
123
4
5
6
T4
7
8
9
11
10
C5
R5
NM
NM
0805
0805
M
R4
N
C4
200V
NM
0805
0805
R3
NM
C3
NM
0805
0805
R2
C2
NM
NM
0805
0805
D3
SMAJ58 A
TP1
C1
0805
100V
0.1u
D24
SMA
4
STPS1H10 0
-
+
1
D2
3
A
SM
D22
STPS1H10 0
0
D20
SMA
4
STPS1H10
+
-
1
D1
3
A
STPS1H100SM
D18
ETH1-230LD
16
15
12
14
13
s
The H2019 footpri nt will be placed
NOTE f or dat aTr a nsf or me r
200V
e
Chassis
C8
1808
2KV
NM
200V
Termi na t i onTo be placed on solder sid
200V
TP 2
0
D25
SMA
2512
2512
STPS1H10
R9 N M
R8 N M
2
DF01S N M
SMA
D23
STPS1H10 0
SEE BO M
D21
SMA
STPS1H10 0
The resistors must be placed on
NOTE for 2512 Power Resis tors
2
DF01S N M
D19
STPS1H100SMA
solder side, belhind the SO8 body .
NOTE for Output Inductor
The 1206 footpri nt wil l be placed
The DPack footprint for the diode will be on top side.
NOTE for Output Recti er
T2
321
inside the FA2706 footprint
NOTE for Power Transf or mer
The 13P footprint will be placed
inside the E TH1-230LD one
D6
D4
SMC
STTH302 S
C41
0805
0.1u
100V
SO8
5
678
R12
Q1
4
STS10PF30L
3
1
2
330K
R10
0805
C27
0.1u
0
R5 0
BZX84C15
SOT23
3
1
D5
TP3
R11
15K
0805
1
2
3
J4
DC Power Jac k
AUX II
M
SEE BO
L
2
2
4
M
L2
L3 NM
N
R1
1206
0.33uH
between the inductor pad s
The Power SO8 footpr int of the mosfe t and the
4
SOD323
BAT46J NM
330K
0805
0.33uH
LPS401 2- 331
DO1813H-331ML
1
1
SEE BO M
5
8
6
7
470p
C11
0805
DPac
1
2
3
STPS15L30CB
7
2
D8
TP
15
R13
1206
Snubber on solder si de.
8910
7
COILCRAFT POE13P
SMC
STTH302 S
GND
TP5
TP4
1
DC Power Jac k
Q
143
SEE BO M
10
9
NM
T1
4
3
D10
5
C16NM080
TP6
R16NM1206
A
D9
SMAJ58
C17
1812
100V
2.2u
SEE BO M
2.2u
100V
C15
1812
2.2u
C14
100V
1812
2
L1
3.3uH
ME32 2 0 - 332 ML
1
C13
22u100V
8x10.2
D7
BAS21
K
R15
15
0805
2
3
J3
AUXI_IRL
TP8
N
NTR
TR
D11
Green LED
C24
330u
8x10.5
6.3V
1206
6.3V
10u
C23
C21
10u
1206
6.3V
C20
1206
6.3V
10u
9
C1
6.3V
10u
1206
C18
6.3V
10u
1206
4
3
D13
1
1
PowerSO 8
D12
STSJ60NH3LL
3
7118
12
5
1
2
6
R1 8
10
SMA
STPS1H100
D14
C25
BAT46J
SOD323
3.3k
R19
D15
GND
M
R49
N
SEE BO M
D26
SOT2 3
R23
10k
0
R25
0
R24
NM
R22
R26
BZX84C18
SOT23
SOT23
BZX84C18
NOTE
PowerSO8 footpr int wi ll be pl aced
on the solder side behi nd the DPac k one
COILCRAFT FA2706 - BL
TP10
0603
1u
16V
GND
C26
0.1u
Green LED
C34
0.1u
AGND
NM
C42
C28
0.1u
AGND
15
16
R21
AGND
88.7K
1%
RT
U1
1
RT
SS
%
21k
R32
1
10
1u
16V
C30
0603
NM
R34
R29
1
23
R41
Sharp PC3 H7
U2
D
41
AGN
R28
1k
C32
0.1u
M
C31
N
Q3A N M
PowerSO 8
8
7
6
2 3
5
1
6
4
R4
R40
SEE BO M
DPac k
STD22NM20L
Q3
3
2
TP11
BAT46J
SOD323
R39
1
D17 N
10
R38
R31
10 0805
100
R33
C33
1%
R44
12.4
M
M
1%
R47
N
1%
10
R43
SEE BO
M
22
C35
SEE BO
C37
4.7n
4
3
5
U3
TS431
SOT23-5
NM
1206
Those components will be plac ed
NOTE
GND
A
0
R42
TP1 2
1206
NM
1206
0.47 ohm
GND
1206
0.47 ohm
on the solder sid e
1812
2.2n
R2 0
NM
1206
C29
0
round that will be connected to th e
nal
470p
round plane close to pin 9 of PM880
D
D
D
G
GPnDGPn
G
G
P
P
P
P
GD
CS
VCC
GND
n
nD
n
nDG
13
14
9
10
12
11
CS
GD
VFB
VCC
GND
nPGD
PM8800
COMP
UXII
SS2A
3
4
I
I
X
XUAII
VIN
UA
HTSSO1 6
C36
0.1u NM
0805
Ex Pad
17
S
S
VIN
RCLAS
AUXI_IRL
DCCL
VS
6
5
7
8
VSS
DCC L
RCLASS
AUXI_IRL
100V
D27 NM
15k
1%
R37
1%
NM
0805
R35
GND po wer
NOTE
The AGND is a dedicated pla ne of si
A
SM
STPS1H100
V
C40
100p N M
R48
NM
D16
10k
R27
R36
SOD323
BAT46 J
TP9
TP13
NM
e is 50
is 0603 and tolera nce 5 %
is 0603 and the volta
NOTE for Ca paci tors
Where not indicated the bod
NOTE for Re sist ors
Where not indicated the bod
Sync Input
2KV
GND
AM01333v1
8/47
AN2783Board layout
4 Board layout
Figure 3.Assembly view: top and bottom layer
9/47
Board layoutAN2783
Figure 4.Top layer
Figure 5.Inner layer 1
Figure 6.Inner layer 2
10/47
AN2783Board layout
Figure 7.Bottom layer
4.1 Input/output connectors
In Figure 3 the main input / output connections of the reference board are presented:
●J1 is the RJ45 connector for the PoE input, with data and power applied through the
CAT5 cable (as an alternative, a positive voltage between 30 V and 60 V can be applied
to test points TP1 + and TP2 -)
●J2 is the RJ45 data output
●J3 is the power jack for AUXI input (as an alternative, the test points TP 3 + and TP4 -
can be used)
●J4 is the power jack for AUXII input (as an alternative, the test points TP5 + and TP9 -
can be used)
●J5 is the DC output connector
4.2 Notes
●Please note that the use of TP1 and TP2 limits the voltage polarity applied and that
these points are after the data transformer and diode bridges.
●AUXII is not protected against reverse polarity applied to it.
●For synchronization tests the capacitor C40 =100 pF must be mounted. Please take
care when using test point TP13 because this is a high impedance point that can easily
pick up noise from the board.
●Resistive or electronic loads can be used as loads. Limit the output capacitance
externally applied in order to not impact the loop compensation.
●As an input source a DC power supply with 60 V and 2 A capability is required.
●For auxiliary inputs a DC source of 60 V and 3 A capability is recommended.
11/47
Bill of materialAN2783
5 Bill of material
Table 2.Components for the 4 isolated configurations possible with the PM8800
ReferenceDescriptionPkgManufacturer
5 V std power
3.3 V std power
3.3 V high power
Qty Qty Qty Qty
Printed circuit board
1111PM8800 eval kit
Capacitors
1111C1Ceramic cap 0.1 µF 100 V805TDK
NMNMNMNMC36Ceramic cap 0.1 µF 100 V805NM
NMNMNMNMC2, C7Ceramic cap 200 V805NM
5 V high power
(1)
NMNMNMNMC8Ceramic cap 2 kV1812NM
NMNMNMNMC9Ceramic cap 805NM
NMNMNMNMC10, C12Ceramic cap 805NM
1111C11Ceramic cap 470 pF 50 V805Std
1111C13Electrolytic cap 22 µF 100 V KX8 x 10.2SANYO
2222C14, C15Ceramic cap 2.2 µF 100 V1812TDK
NM1NM1C17Ceramic cap 2.2 µF 100 V1812TDK
NMNMNMNMC16Ceramic cap805NM
22NMNMC18, C19Ceramic cap 10 µF 6.3 V1206TDK
33NMNM
NMNM22C18, C19Ceramic cap 10 µF 16 V1206TDK
NMNM33
NMNMNMNMC22, C38Ceramic cap1206NM
1111C24Electrolytic cap 330 µF 6.3 V EX8 x 10.5SANYO
2222C25, C30Ceramic cap 1 µF 16 V603TDK
5555
1111C29Ceramic cap 2.2 nF 2 kV1812TDK
C20, C21,
C23
C20, C21,
C23
C26, C27,
C28, C34,
C39
Ceramic cap 10 µF 6.3 V1206TDK
Ceramic cap 10 µF 16 V1206TDK
Ceramic cap 0.1 µF 50 V 603Std
NMNMNMNMC31Ceramic cap 603Std
1111C32Ceramic cap 0.1 µF 50 V 603Std
12/47
AN2783Bill of material
Table 2.Components for the 4 isolated configurations possible with the PM8800 (continued)