ST AN2782 Application note

Solution for designing a 400 W fixed-off-time controlled

PFC preregulator with the L6562A

Introduction

In addition to the transition mode (TM) and fixed-frequency continuous conduction mode (FF-CCM) operation of PFC pre-regulators, a third approach is proposed that couples the simplicity and affordability of TM operation with the high-current capability of FF-CCM operation. This solution is a peak current-mode control with fixed off-time (FOT). Design equations are given and a practical design for a 400 W board is illustrated and evaluated. Two methods of controlling power factor corrector (PFC) pre-regulators based on boost topology are currently in use: the fixed-frequency (FF) PWM and the transition mode (TM) PWM (fixed on-time, variable frequency). The first method employs average current-mode control, a relatively complex technique requiring sophisticated controller ICs (e.g. the L4981A/B from STMicroelectronics) and a considerable component count. The second one uses the simpler peak current-mode control, which is implemented with cheaper controller ICs (e.g. the L6561, L6562, L6562A from STMicroelectronics), much fewer external parts and is therefore much less expensive. In the first method the boost inductor works in continuous conduction mode (CCM), while TM makes the inductor work on the boundary between continuous and discontinuous mode, by definition. For a given power throughput, TM operation involves higher peak currents as compared to FF-CCM (Figure 1 and 2).

Figure 1. Line, inductor, switch and diode

currents in FF-CCM PFC

AN2782

Application note

Figure 2. Line, inductor, switch and diode

currents in TM PFC

"CCM" type

"TM" type

IAC

MOSFET

OFF

This demonstration, consistent with the above mentioned cost considerations, suggests the use of TM in a lower power range, while FF-CCM is recommended for higher power levels. This criterion, though always true, is sometimes difficult to apply, especially for a midrange power level, around 150-300 W. The assessment of which approach gives the better cost/performance trade-off needs to be done on a case-by-case basis, considering the cost and the stress of not only power semiconductors and magnetic but also of the EMI filter. At the same power level, the switching frequency component to be filtered out in a TM system is twice the line current, whereas it is typically 1/3 or 1/4 in a CCM system.

March 2010 Doc ID 14763 Rev 2 1/39

MOSFET

OFF

www.st.com

Contents AN2782

Contents

1 Introduction to FOT control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Operation of an FOT-controlled PFC pre-regulator . . . . . . . . . . . . . . . . 5

3 The circuit implementing the line-modulated fixed off-time with the new

L6562A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Designing a fixed off-time PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1 Input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3 Power section design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3.1 Bridge rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3.4 Boost inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3.5 Power MOSFET selection and the dissipation . . . . . . . . . . . . . . . . . . . . 16

4.3.6 Boost diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.3.7 L6562A biasing circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 Design example using the L6562A FOT PFC Excel spreadsheet . . . . 28

6 EVL6562A-400W demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Test results and significant waveforms . . . . . . . . . . . . . . . . . . . . . . . . 32

8 L6562A layout hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2/39 Doc ID 14763 Rev 2

AN2782 List of figures

List of figures

Figure 1. Line, inductor, switch and diode currents in FF-CCM PFC. . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. Line, inductor, switch and diode currents in TM PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 3. Basic waveforms for fixed-frequency PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. Basic waveforms for fixed off-time PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 5. Block diagram of an FOT-controlled PFC pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. Circuit implementing FOT control with the L6562A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 7. ZCD pin signal with the fixed off-time generator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 8. Switching frequency fixing the line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9. The effect of fixing OFF-time - boundary between DCM and CCM . . . . . . . . . . . . . . . . . . 15

Figure 10. Conduction losses and total losses in the two STP12NM50 MOSFETs for the 400 W FOT

PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 11. L6562A internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 12. Bode plot - open-loop transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 13. Bode plot - phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 14. Multiplier characteristics family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 15. Switching frequency function on the peak of the sinusoid input voltage waveform and the cor-

responding off-time value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 16. Off-time vs. input mains voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 17. Switching frequency vs. input mains voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 18. Excel spreadsheet design specification input table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 19. Other design data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 20. Excel spreadsheet FOT PFC schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 21. Excel spreadsheet BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 22. EVL6562A-400W demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 23. Wide-range 400 W demonstration board electrical circuit (EVL6562A-400W) . . . . . . . . . . 31

Figure 24. EVL6562A-400W compliance to EN61000-3-2 standard at full load . . . . . . . . . . . . . . . . . 32

Figure 25. EVL6562A-400W compliance to JEIDA-MITI standard at full load . . . . . . . . . . . . . . . . . . . 32

Figure 26. EVL6562A-400W compliance to EN61000-3-2 standard at 70 W . . . . . . . . . . . . . . . . . . . 32

Figure 27. EVL6562A-400W compliance to JEIDA-MITI standard at 70 W . . . . . . . . . . . . . . . . . . . . . 32

Figure 28. Power factor vs. Vin and load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 29. THD vs. Vin and load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 30. Efficiency vs. Vin and load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 31. Static Vout regulation vs. Vin and load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 32. EVL6562A-400W: input current waveform at 100 V - 50 Hz - 400 W load . . . . . . . . . . . . . 34

Figure 33. EVL6562A-400W: input current waveform at 230 V -50 Hz - 400 W load . . . . . . . . . . . . . 34

Figure 34. EVL6562A-400W: input current waveform at 100 V - 50 Hz - 200 W load . . . . . . . . . . . . . 34

Figure 35. EVL6562A-400W: input current waveform at 230 V - 50 Hz - 200 W load . . . . . . . . . . . . . 34

Figure 36. EVL6562A-400W: input current waveform at 100 V - 50 Hz - 70 W load . . . . . . . . . . . . . . 35

Figure 37. EVL6562A-400W: input current waveform at 230 V - 50 Hz - 70 W load . . . . . . . . . . . . . . 35

Doc ID 14763 Rev 2 3/39

Introduction to FOT control AN2782

1 Introduction to FOT control

In this area where the TM/CCM usability boundary is uncertain, a third approach that couples the simplicity and affordability of TM operation with the high-current capability of CCM operation can be a solution to the dilemma. Generally speaking, FF PWM is not the only alternative when CCM operation is desired. FF PWM modulates both switch ON and OFF times (their sum is constant by definition), and a given converter operates in either CCM or DCM depending on the input voltage and the loading conditions. Exactly the same result can be achieved if the ON-time only is modulated and the OFF-time is kept constant, in which case, however, the switching frequency is no longer fixed (Figure 3 and Figure 4). This is referred to as “fixed off-time” (FOT) control. Peak-current-mode control can still be used.

Figure 3. Basic waveforms for fixed-

Gate drive

signal

frequency PWM

TON'

TOFF'

TON

TOFF

TSW TSW

TON'

TON

TOFF'

TOFF

TON'

TON

An important point is that FOT control does not need a specialized control IC. A simple modification of a standard TM PFC controller operation, requiring just a few additional passive parts and no significant extra cost, is all that is needed.

Figure 4. Basic waveforms for fixed off-time

PWM

Gate drive

signal

TON' TON' TON'

TOFF TOFF

TSW' TSW'

TON TON TON TOFF TOFF

TSW TSW

4/39 Doc ID 14763 Rev 2

AN2782 Operation of an FOT-controlled PFC pre-regulator

2 Operation of an FOT-controlled PFC pre-regulator

Figure 5 shows a block diagram of an FOT-controlled PFC pre-regulator. An error amplifier

(VA) compares a portion of the pre-regulator's output voltage Vout with a reference VREF and generates an error signal V hypothesis, is fed into an input of the multiplier block and multiplied by a portion of the rectified input voltage V V

, whose amplitude is proportional to that of V

CSREF

MULT

sinusoidal reference for PWM modulation. V comparator that, on the non-inverting input, receives the voltage V Rsense, proportional to the current flowing through the switch M (typically a MOSFET) and the inductor L during the ON-time of M. When the two voltages are equal, the comparator resets the PWM latch and M, supposedly already ON, is switched off.

Figure 5. Block diagram of an FOT-controlled PFC pre-regulator

proportional to their difference. VC, a DC voltage by

. At the output of the multiplier, there will be a rectified sinusoid,

and to VC, which represents the

MULT

is fed into the inverting input of a

CSREF

on the sense resistor

As a result, V

determines the peak current through M and the inductor L. As V

CSREF

is a rectified sinusoid, the inductor peak current is enveloped by a rectified sinusoid as well. The line current Iin will be the average inductor current that is the low-frequency component of the inductor current resulting from the low-pass filtering operated by the EMI filter.

The PWM latch output Q going high activates the timer that, after a predetermined time T

has elapsed, sets the PWM latch, thus turning M on and starting another switching

OFF

cycle. If T

is such that the inductor current does not fall to zero, the system operates in

OFF

CCM. It is apparent that FOT control requires nearly the same architecture as TM control, just the way the off-time of M is determined changes. It is not a difficult task to modify externally the operation of the standard TM PFC controller so that the off-time of M is fixed. As a controller we will refer to the L6562A [4], which is suitable for a few hundred watts power applications because of its gate drive capability and its high noise immunity.

For a more detailed and complex description of the fixed off-time technique and in particular the line modulated FOT, please refer to [7].

Doc ID 14763 Rev 2 5/39

The circuit implementing the line-modulated fixed off-time with the new L6562A AN2782

(

3 The circuit implementing the line-modulated fixed

off-time with the new L6562A

The circuit that implements LM-FOT control with the L6562A is shown in Figure 6. During the ON-time of the MOSFET the gate voltage V biased and the voltage at the ZCD pin is internally clamped at V off-time of M V

= 10 V is low, the diode D is reverse-biased and the voltage at the pin

decays with an exponential law until it reaches the triggering threshold (V that causes the switch to turn on. The time needed for the ZCD voltage to go from V to V

ZCDtrigger

defines the duration of the off-time T

Figure 6. Circuit implementing FOT control with the L6562A

= 15 V is high, the diode D is forward-

OFF

ZCDclamp

≈ 5.7 V. During the

ZCDtrigger

≈ 0.7 V)

ZCDclamp

The circuit of Figure 6 makes T

a function of the RMS line voltage thanks to the peak-

OFF

holding effect of T1 (which acts as a buffer) along with R and C whose time constant is significantly longer than a line half-cycle. With the addition of R voltage on the ZCD pin during T

is above V

OFF

mult+VBE

, C is discharged through R and R0,

and T, as long as the

following the law:

)RR(t

+⋅

−

′

As V’

⎡

V)t(V

⎢

ZCDclampZCD

⎣

(t) falls below V

ZCD

−=

mult+VBE

()

, T1 is cut off and C is discharged through R only, so that

⎤

()

⋅

+⋅

eVV

⎥

BEmult

⎦

CRR

+⋅

()

+⋅

(1)

BEmult

its evolution from that point on is described by:

(t) decreases from V

ZCD

′

′′

ZCD

ZCDclamp

⋅

−= +

)t(V

()

= 5.7 V to V

BEmult

mult+VBE

⎡

⋅⋅

lnC

⎢ ⎢

⎣

−

⋅

eVV

⋅+⋅

(2)

in the following time period t':

)

⋅+

RVV

0BEmult

()

⎤ ⎥

⋅+−+⋅

RVV)RR(V

⎥

BEmult0ZCDclamp

⎦

(3)

6/39 Doc ID 14763 Rev 2

AN2782 The circuit implementing the line-modulated fixed off-time with the new L6562A

and V''

(t) decreases from V

ZCD

mult+VBE

to V

ZCDtriggering

= 0.7 V level in the following time

period t'':

⎡

′′

⋅−=

lnRCt

ZCDtrigger

⎢ ⎣

⎤ ⎥

BEmult

⎦

(4)

Figure 7 illustrates the signal on the ZCD pin with the two discharging time constants

depending on the two resistors R, R

and the L6562A parameters, particularly the upper

clamp voltage and the triggering voltage of the ZCD pin.

Figure 7. ZCD pin signal with the fixed off-time generator circuit

ZCDclamp

Vzcd (V)

′

ZCD

)(tV

′′

)(tV

ZCD

7.5=

VV +

BEmult

02468

′

usec

′′

OFF

ZCDtrigger

7.0=

The sum of the two time periods is the OFF-time function:

⎤

⎞

(5)

⎟

⎥

⎟

⎥

BEmult

⎠

⎦

OFF

⎡

⎢

⋅−=

RCT

⎢

⎣

⎡

⋅

⎢

⎣

()

⋅+

RVV

0BEmult

()

In this way, once the multiplier operating point (that is, the V proper selection of R and R maximum line voltage, it is always T condition needed in order to avoid line distortion [

It is easy to see that T

OFF

it is possible to increase T

ON>TONmin

= 450 ns for the L6562A [4]. This is a

OFF

7].

is now a function of the instantaneous line voltage. We will refer to

this technique as “line-modulated fixed off-time” (LM-FOT) [

⎤ ⎥

⋅+−+⋅

RVV)RR(V

⎥

BEmult0ZCDclamp

⎦

/VAC ratio) is fixed, with a

mult

⎛

ZCDtrigger

⎜

()

⎝

with the line voltage so that, at

7].

This modification, though simple, introduces profound changes in the timing relationships, with a positive influence on the energetic relationships. From the control point of view, modulating T

is a feedforward term that modifies the gain but does not change its

OFF

Doc ID 14763 Rev 2 7/39

The circuit implementing the line-modulated fixed off-time with the new L6562A AN2782

characteristics. Consequently, all of the properties of the standard FOT control are maintained.

Due to the highly non-linear nature of the T

modulation introduced by T1 and R0, its

OFF

effects are discussed only qualitatively and the quantitative aspects are provided graphically for a specific case in [

7].

As a practical rule, it is convenient to first select a capacitor and then to calculate the resistor needed to achieve the desired T

As the gate voltage V as possible up to V

goes high, the resistor Rs charges the timing capacitor C as quickly

ZCDclamp

, without exceeding clamp rating (I

(see Section 4.3.7).

OFF

=10 mA). Then it must

ZCDx

fulfill the following inequalities:

VVV

FZCDclampGD

(6)

= 15 V its

GDx

ZCDx

where V

(assume VGD = 10 V) is the voltage delivered by the gate driver, V

maximum value, and V

VVV −−

−−

FZCDclampGDx

ZCDclamp

the forward drop on D.

RRs

⋅<<

ZCDclamp

When working at high line/light load the on-time of the power switch becomes very short and the resistor Rs alone is no longer able to charge C up to V

ZCDclamp

. The speed-up capacitor Cs is then used in parallel to Rs. This capacitor causes an almost instantaneous charge of C up to a level, after that Rs completes the charge up to V

ZCDclamp

. It is important that the steep edge caused by Cs does not reach the clamp level, otherwise the internal clamp of the L6562A undergoes uncontrolled current spikes (limited only by the dynamic resistance of the 1N4148 and the ESR of Cs) that could overstress the IC. Cs must then be:

CCs−−<

ZCDclamp

VVV

FZCDclampGDx

(7)

8/39 Doc ID 14763 Rev 2

AN2782 Designing a fixed off-time PFC

4 Designing a fixed off-time PFC

4.1 Input specification

The following is a possible design flowchart in reference to a fixed off-time mode PFC using the L6562A. This first part is a detailed specification of the operating conditions of the circuit that is needed for the following calculations in input range mains PFC circuit has been considered. Some design criteria are also given.

Section 4.2. In this example a 400 W, wide

● Mains voltage range (Vac rms):

● Minimum mains frequency:

● Rated output power (W):

min

Vac90VAC

out

max

Hz47f

W400P

Vac265VAC

(8)

(9)

(10)

Because the PFC is a boost topology the regulated output voltage depends strongly on the maximum AC input voltage. In fact, for correct boost operation the output voltage must always be higher than the input and thus, because Vin max is V

VAC

max

2 374=⋅

, the output has been set at 400 Vdc as the typical value. If the input voltage is higher, as typical in ballast applications, the output voltage must be set higher accordingly. As a rule of thumb the output voltage must be set 6/7% higher than the maximum input voltage peak.

● Regulated DC output voltage (Vdc):

out

V400V

(11)

The target efficiency and PF are set here at minimum input voltage and maximum load. They are used for the following operating condition calculation of the PFC. Of course at high input voltage the efficiency is higher.

● Expected efficiency (%):

● Expected power factor:

out

%90

==η

99.0PF

(12)

(13)

Because of the narrow loop voltage bandwidth, the PFC output can face overvoltages at startup or in case of load transients. To protect from excessive output voltage that can overstress the output components and the load, the L6562A integrates an OVP. The overvoltage protection sets the extra voltage overimposed to Vout:

● Maximum output overvoltage (Vdc):

Doc ID 14763 Rev 2 9/39

V40OVP

(14)

Designing a fixed off-time PFC AN2782

The mains frequency generates a 2fL voltage ripple on the output voltage at full load. The ripple amplitude determines the current flowing into the output capacitor and the ESR.

Additionally, a certain holdup capability in case of mains dips can be requested from the PFC in which case the output capacitor must also be dimensioned, taking into account the required minimum voltage value (Vout min) after the elapsed holdup time (t

● Maximum output low frequency ripple:

● Minimum output voltage after line drop (Vdc):

● Holdup capability (ms):

out

Hold

V10V

minout

Hold

(15)

V300V

ms20t

(16)

(17)

The PFC minimum switching frequency is the one of the main parameters used to dimension the boost inductor. Here we consider the switching frequency at low mains on the top of the sinusoid and at full load conditions. As a rule of thumb, it must be higher than the audio bandwidth in order to avoid audible noise and additionally it must not interfere with the L6562A minimum internal starter period, as given in the datasheet. On the other hand, if the minimum frequency is set too high the circuit shows excessive losses at higher input voltage and probably operates skipping switching cycles not only at light load. Typical minimum frequency range is 55÷95 kHz for wide range operation.

● Minimum switching frequency (kHz):

Where f

= 1/(T+220 nsec) due to the ZCD - gate drive signal delay typical of the

swmin

kHz72f

minsw

(18)

L6562A.

The design will be done on the basis of a ripple factor (the ratio of the maximum current ripple amplitude to the inductor peak current at minimum line voltage) k

● Ripple factor

=0.36.

34.0k

(19)

In order to properly select the power components of the PFC and dimension the heat sinks in case they are needed, the maximum operating ambient temperature around the PFC circuitry must be known. Please note that this is not the maximum external operating temperature of the entire equipment, but it is the local temperature at which the PFC components are working.

● Maximum ambient temperature (°C)

ambx

C50T

°=

(20)

10/39 Doc ID 14763 Rev 2

AN2782 Designing a fixed off-time PFC

4.2 Operating condition

The first step is to define the main parameters of the circuit, using the specification points given in

● Rated DC output current

● Maximum input power

Section 4.1:

out

W400

I =

out

W400

V400

=⋅=

(21)

A00.1

(22)

W44.444100

Referring to the main currents shown in

Figure 1, the following formula expresses the

maximum value of current circulating in the boost cell which means at minimum line voltage of the selected range:

● RMS input current

out

min

PFVAC

⋅

W400

99.0Vac90

⋅

(23)

A99.4

It is important to define the following ratios in order to continue describing the energetic relationships in the PFC:

VAC

min

max

2k =

VAC

out

max

out

min

max

Vac90

Vac265

32.0

V400

94.0

V400

(24)

(25)

From (24), (25):

● Line peak current:

⋅

maxPK

⋅

outmin

maxPK

⋅

)W44.444(2

V400318.0

⋅

(26)

A98.6

● Inductor ripple-

ΔILpk:

IL ⋅

=Δ

Doc ID 14763 Rev 2 11/39

⋅

k38

⋅−

maxPK

=Δ

34.06

⋅

34.038

⋅−

=⋅

(27)

A18.2A98.6

Designing a fixed off-time PFC AN2782

● Inductor peak

current:

IL ⋅

maxpk

k38

⋅−

maxPK

maxpk

34.038

⋅−

=⋅

(28)

A07.8A98.6

It is also possible to calculate the RMS current flowing into the switch and into the diode, needed to calculate the losses of these two elements.

● RMS

switch current:

● RMS

diode current:

ISW

rms

⋅

outmin

⋅

outmin

It is worth reminding that the accuracy of the approximate energetic relationships described here is quite good at maximum load for low values of the parameter k, that is, at low line voltage, but worsens at high line and as the power throughput is reduced. Since in the design phase current stress is calculated at maximum load and minimum line voltage, their accuracy is acceptable for design purposes.

4.3 Power section design

4.3.1 Bridge rectifier

The input rectifier bridge can use standard slow recovery, low-cost devices.Typically a 600 V device is selected in order to have good margin against mains surges. An NTC resistor limiting the current at turn-on is required to avoid overstress to the diode bridge.

⋅

k16

min

ISW

rms

−⋅

k16

min

⋅

W400

⋅

W400

⋅

V400318.0

⋅

V400318.0

318.016

⋅

−⋅

⋅

318.016

A22.4

A57.2

(29)

(30)

The rectifier bridge power dissipation can be calculated using equations threshold voltage and dynamic resistance of a single diode of the bridge can be found in the component datasheet.

⋅

inrms

avg_in

⋅

The power dissipated on the bridge is:

12/39 Doc ID 14763 Rev 2

(31), (32), (33). The

A99.42

A53.3

A25.2

(31)

(32)

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