ST AN2771 APPLICATION NOTE

AN2771

Application note

2x58 W/T8 or 2x36 W/T8 ballast demonstration board driven by L6585D

Introduction

This application note describes a demonstration board able to drive 2x58 W linear T8 fluorescent tubes. In addition, the modifications needed to adapt the same board for 2x36 W linear T8 fluorescent tubes are specified.

The ballast is controlled by STMicroelectronics’ L6585D which integrates PFC and halfbridge control circuits, the relevant drivers, and the circuitry able to manage all lamp operating phases (preheating, ignition and run mode). Protections against primary failures (lamp disconnection, anti-capacitive mode, PFC overvoltage) are guaranteed and obtained with a minimum number of external components. After presenting the circuit description and design criteria, a short overview of the ballast performances is given.

Fluorescent lamps are driven more and more by electronic, rather than electromagnetic ballast, primarily because fluorescent lamps can produce around 20 % more light for the same input power when driven above 20 kHz instead of 50/60 Hz. Operation at this frequency also eliminates both light flickering (the response time of the discharge is too slow for the lamp to have a chance to extinguish during each cycle) and audible noise. An electronic ballast consumes less power and therefore dissipates less heat than an electromagnetic ballast. The energy saved can be estimated in the range of 20-25% for a given lamp power. Finally the electronic solution allows better control of the filament current and lamp voltage during preheating with the unquestionable benefit of increasing the mean lamp life.

Figure 1. 2x58W T8 ballast demonstration board

August 2008		Rev 1	1/27

www.st.com

Contents	AN2771

Contents

1	Basis of half-bridge inverter topology . . . . . . . . . . . . . . . . . . . . . . . . .		. 4
2	Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
3	Ballast design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
	3.1	L6585D biasing circuitry (pin by pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	3.2	PFC power section design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	3.3	Half-bridge inverter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	3.4	Symmetrical and asymmetrical EOL protection: improvements . . . . . . . .	13
4	Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
5	Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
6	Conduction emissions test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
	6.1	Adapting the design for a 2x36 W T8 electronic ballast . . . . . . . . . . . . . .	21
7	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		26

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AN2771	List of figures

List of figures

Figure 1. 2x58W T8 ballast demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Electronic lamp ballast - capacitor-to-ground configuration . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. Electronic lamp ballast - lamp-to-ground configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. Dual lamp ballast series configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 5. Dual lamp ballast parallel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 6. Electrical schematic 2x58 W T8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 7. TSM101 window comparator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8. External symmetrical EOL protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9. L6585 startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10. One lamp ignition phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11. Low-side current in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12. Voltage and current lamp in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 13. Asymmetrical EOL protection with broken cathode during run mode. . . . . . . . . . . . . . . . . 19 Figure 14. Symmetrical EOL protection behavior during ignition phase . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 15. Conducted emissions at 230 Vac 50 Hz - line 1 peak detector . . . . . . . . . . . . . . . . . . . . . 21 Figure 16. Conducted emissions at 230 Vac 50 Hz - line 2 peak detector . . . . . . . . . . . . . . . . . . . . . 21

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Basis of half-bridge inverter topology	AN2771

1 Basis of half-bridge inverter topology

The half-bridge inverter operates in zero voltage switching (ZVS) resonant mode, to reduce the switching losses and the electromagnetic interference generated by the output wiring and the lamp. Voltage-fed series resonant half-bridge inverters are currently used for compact fluorescent lamp ballasts (CFL) and for many European tube lamp (TL) ballasts.

Generally, for lighting applications, considering the current preheating, it's possible to choose between two different topologies of the resonant circuit: capacitor-to-ground (Figure 2) or lamp-to-ground (Figure 3).

Figure 2. Electronic lamp ballast - capacitorFigure 3.	Electronic lamp ballast - lamp-to-
to-ground configuration	ground configuration

+	CRES	+
LRES		LrRES	CBlock
Vdc		Vdc	CRES
		CBlock
_		_

In the design presented in this application note, a capacitor-to-ground configuration was used. For dual lamp ballast the lamps can be connected in series (Figure 4) or in parallel (Figure 5). In the system presented here, a parallel configuration was chosen for the following reasons:

●lower voltage stress on the ballast output stage components, on the wiring, and on the fixture sockets

●the resonant L and C associated with the lamps are less sensitive to component tolerances due to the lower operating lamp voltages compared to the series configuration

●better lamp control as it is possible to independently monitor both lamp operations

Figure 4. Dual lamp ballast series	Figure 5. Dual lamp ballast parallel
configuration	configuration

+	CRES	+	CRES
			LrRES
	LrRES	LrPRE
-	CBlock	-	CBlock
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AN2771	Main characteristics

2 Main characteristics

The electrical specifications for the electronic lamp ballast are given in Table 1 and the schematic for the 2x58 W T8 is presented in Figure 6. The ballast design procedure is detailed in the following section.

Table 1.	Input and output parameters
		Input parameters
	VIN	Input voltage range		185 to 265 VRMS
	fline	Line frequency		50/60 Hz
		Tube lamp
	Number	2
	Type	T8 in parallel configuration
	Power	58 W or 36 W
		Target output parameters
	PF	Power factor		≈ 0.9
	THD%	Total harmonic distortion		≤ 10
	η %	Efficiency		≈ 90 %

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		D10
		8
		R5
		1 MOhm
	C4	5
	470 nF
		R9
		390 kOhm
		R33	0
D3	D4	R17
GF1M	GF1M
		20//11 kOhm

J1			1	LPFC2
				4	C11
2		C10
					100nF 275V X2
1	100nF 275V X2
3			2	3	D5	D6
CON3					GF1M	GF1M
	F1	3A	2x39 mH/0.7A
			C20
			1nF 275 VAC Y1

1N4007

	D2
	STTH1L06
3
	0.8 mH			R6		R7
	LPFC1			1.5 MOhm910 kOhm
1	C1	+	C21
	47uF 450V	100nF 630V		R11		R12
	R32			1.5 MOhm910 kOhm
	0
	R10					C8
	15 kOhm		R18		R19	10 nF
		18 kOhm
				13 kOhm
		D7
		BAT46Z
	Q3
	STD6NK50Z		R21
			10 Ohm
		R53	0
	R22				C25
	0.33 ohm 1% 1W
					CAP NP

3

Q8

BC847

2

1 3

1

R27

56K

C2

R13

R30

470//100 nF

30 KOhm

C3

R8

56K

33 nF

16 kOhm

R14

C7

R15

C5

20 kOhm

C6

240 kOhm

1.8 nF

470//150 1.2 MOhm470//220 nF

R16

10 9 8 7 6 5 4 3 2 1

INV Comp

Mult

CTR -EOLR

EOLP TCH EOI

RF

Osc

U1

R20

C22

L6585D

Q2

62 Ohm

220 pF 1kV

STD8NM60N

ZCD PFCS

PFG

HBCS GND

LSD VCC Out

HSD

Boot

1

5

L1

11

12

13

14

15

16

17

18

19

20

1.8 mH

R36

68k

C13

100nF 50V

R37

56k

L2

1

5

1.8 mH

Q4

R40

R23

62 Ohm

68k

STD8NM60N

R41

56k

D8 1N4148

R29

10 Ohm

C16

C17

D9

1 nF 1kV

D13

R31

C18

LL4148

16V

4.7uF 50V

0.33 ohm 1% 1W

100nF

R56

18k

R52

0

D11

BAT46Z

D12

BAT46Z

R49

R47

330k

330k

R51	2k
2
Q7	3	R48	10
XO205MA
		1	3

R50		BC847	1
56k	2
R55		Q6	BC847
470		2		R46
			Q5
				470k

						.6 Figure	characteristics Main
		R3		R4		Electrical
		560 kOhm		560 kOhm
		LAMP1				schematic
R34		C9
180k		10 nF 1600V
1				4		2x58
2				3
		T8 Lamp1-58W			C12
				100 nF, 400V		W
R35		C14
		10 nF 1600V
180k
						T8
		LAMP2
4				1
3				2
		T8 Lamp1-58W
					C15
				R24	100 nF, 400V
			1.802 MOhm
					R25
					1.6 kOhm	R54
						0R
		U2				R26
	1 Vref			8
			+Vcc			10 kOhm
	2	Csense	Vrin	7
C19	3	Crref	Output	6
100 nF	4	GND	Crin	5
		TSM101

AN2771

AN2771	Ballast design

3 Ballast design

The design of the major parts of the circuit is described in this section.

3.1L6585D biasing circuitry (pin by pin)

Designed in high-voltage BCD offline technology, the L6585D embeds a PFC controller, a half-bridge controller, the relevant drivers and the logic necessary to build an electronic ballast.

●Pin 1 OSC is one of the two oscillator inputs. The value of the capacitor connected to ground defines the half-bridge switching frequency in each operating state. A value of 1.8 nF was chosen.

●Pin 2 RF. The component choice with oscillator capacitance defines the half-bridge

switching frequency in each operating state. A resistor R14 connected to ground sets the run frequency while during preheating the switching frequency is set by the parallel of R14 with R13 connected between pins RF and EOI (short-circuit during preheating).

Choosing the following frequencies and ignition time:

f = 39 kHz	f = 65 kHz tign = 60 ms
run	pre

we can immediately calculate R14 with the following formula:

Equation 1

R14 = 1.326 = 20 kΩ

frun C5

and for the value of R13:

Equation 2

	R13	=	1.326 R14				= 30 kΩ
			fpre C5	R14	− 1.41

●Pin 3 EOI is a multifunction pin. During preheating the pin is internally shorted to

ground by the logic, so the resistor (RPRE//RRUN) connected between the RF pin and ground sets the preheating switching frequency. During ignition pin EOI becomes high impedance. The ignition time is the time necessary for the pin voltage to exponentially

rise from zero to 1.9 V. The growth is steered by the C6* R13 time constant. As the value of R13 has already been calculated and tign at start is fixed, the value of C6 is calculated by the following formula:

Equation 3

C6	=		tign	= 666 nF
			R13
	3

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Ballast design	AN2771

The value C6=620 nF was chosen. In order to have this value, two capacitors in parallel were mounted C6=470//150 nF.

●Pin 4 TCH is the time counter and it is necessary to establish the preheating time and the protection intervention time (either overcurrent or EOL). To implement the time

counter, a R15C7 parallel network is connected between this pin and ground. Choosing C7=690 nF and tpre=1 sec and considering the internal current generator ICH=34 µA, we can calculate R15 as follows:

Equation 4

	tpre −	C7	4.63
		ICH
R15 =				= 1.2 MΩ

C7 ln 4.63

1.5

● Pin 5 EOLP is a 2 V reference and allows programming the window comparator of pin 6 (EOLR) according to table 5 of the L6585D datasheet. Choosing a reference tracking with the CTR pin and a window voltage amplitude ± 220 mV, we chose R16=240 kΩ.

● Pin 6 EOLR is the input of both the window comparator and a re-lamp comparator. Concerning the window comparator (choosing tracking with CTR pin), the center is the same voltage as the CTR pin so the resistive divider connected across the block capacitor (see Cblock in Figure 2) is set such that under normal conditions:

Equation 5

VCTR = VBUSpfc

R19

R

+ (R

7

+ R )

19

12

VEOLR =

VBUSpfc

R8

+ (R3 + R4 )

2 R8

V

= V

(R7 + R12 )

= 2

(R3 + R4 )

+ 1

EOLR

CTR

R19

R8

To determine the resistance values of

(R7+R12), R19, (R3+R4), R8, decisions concerning

pin 7 CTR are needed.

●Pin 7 CTR is a multifunction pin (PFC overvoltage, feedback disconnection, reference for EOL in case of tracking reading), connected to a resistive divider to the PFC output bus. Establishing the maximum PFC overvoltage (PFC output overshoot e.g. at startup)

at VOVPBUSpfc = 480 V and considering that the correspondent threshold on the CTR pin must be VthrCTR = 3.4 V, we can immediately calculate R7+R12 = 1.82 MΩ and R19 = 13 kΩ. From Equation 5, fixing R3+R4 = 1120 kΩ, the following resistance value is obtained R8 = 16 kΩ.

●Pin 8 MULT. Assuming a peak value of VmultpkMax = 1.8 V (at VAC = 265 V) on the multiplier input (MULT, pin 8), the peak value at minimum line voltage is

VMULTpkmin = 1.8 × 185/265 = 1.25 V which, multiplied by the maximum slope of the multiplier, 0.75, gives 0.94 V peak voltage on current sense (CS, pin 4). Since the

linearity limit (1 V) is not exceeded, this is acceptable. Considering about 250 µA current for the divider, the lower resistor is 7.14 kΩ (20//11 kΩ ). To establish the upper resistance value (referring to the PFC section of the L6585D datasheet), the ratio between Vmult and Vin for different input voltage must be evaluated:

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AN2771										Ballast design
Equation 6
	V				R17	= VmultPK max = 4.8 10−3
		inMax	R17 + (R5 + R9 )					2 V
								inMax
V		17		=	VmultSlopeMax		=	VCSclamp	1	= 5.1 10−3
		R
inMin	R17	+ (R5	+ R9 )		2 V			max slope	2 V
					inMin				inMin

where:

●VCSclamp is the clamp value of the voltage current sense for L6585D

●max slope is the maximum slope of the multiplier characteristic family for L6585D

●VmultSlopeMax is the maximum voltage in the mult pin with Vin=VinMin

To work in the linear area of the multiplier characteristic family, the upper resistance choice is made considering the lowest of ratios calculated in Equation 6 R5+R9=1.487 MΩ. R5+R9 = 1.390 MΩ was mounted.

●Pin 9 COMP is the output of the E/A and also one of the two inputs of the multiplier. The feedback compensation network, placed between this pin and INV (10), is simply a

capacitor calculated as follows (considering R6+R11 is the upper resistance of the voltage divider between the PFC bus and COMP pin):

Equation 7

C2	=		10			= 530 nF
			π (R6	+ R11)
	2

A value of C2=560 nF was chosen.

●Pin 10 INV. To implement the voltage control loop, a resistive divider (Figure 6) is

connected between the regulated output voltage VBUSpfc = 420 V of the boost and the

pin. The internal reference on the noninverting input of the E/A is 2.5 V, so R6 and R11 (Figure 6) are then selected, establishing a max overvoltage ∆VOVPBUSpfc = 60 V, as follows:

Equation 8

			R	6	+ R				VBUSpfc
						11		=			− 1
				R18					2.5
R	6	+ R				=	∆VOVPBUSpfc				= 3 MΩ
				11				IOVPth

R18 = 17.964 kΩ 18 kΩ

where IOVPth = 20 µA is the threshold current flowing through the compensation network in case an abrupt load drop happens.

●Pin 11 ZCD is the input to the zero current detector circuit. The ZCD pin is connected to the auxiliary winding of the boost inductor through a limiting resistor. The ZCD circuit is negative-going edge-triggered: when the voltage on the pin falls below 0.7 V, the PWM latch is set and the MOSFET is turned on. To do so, however, the circuit must first be armed. Prior to falling below 0.7 V, the voltage on pin 11 must experience a positivegoing edge exceeding 1.4 V (due to the MOSFET's turnoff). The maximum main-to-

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