ST AN2771 APPLICATION NOTE

AN2771

Application note

2x58 W/T8 or 2x36 W/T8 ballast

demonstration board driven by L6585D

Introduction

This application note describes a demonstration board able to drive 2x58 W linear T8 fluorescent tubes. In addition, the modifications needed to adapt the same board for 2x36 W linear T8 fluorescent tubes are specified.

The ballast is controlled by STMicroelectronics’ L6585D which integrates PFC and halfbridge control circuits, the relevant drivers, and the circuitry able to manage all lamp operating phases (preheating, ignition and run mode). Protections against primary failures (lamp disconnection, anti-capacitive mode, PFC overvoltage) are guaranteed and obtained with a minimum number of external components. After presenting the circuit description and design criteria, a short overview of the ballast performances is given.

Fluorescent lamps are driven more and more by electronic, rather than electromagnetic ballast, primarily because fluorescent lamps can produce around 20 % more light for the same input power when driven above 20 kHz instead of 50/60 Hz. Operation at this frequency also eliminates both light flickering (the response time of the discharge is too slow for the lamp to have a chance to extinguish during each cycle) and audible noise. An electronic ballast consumes less power and therefore dissipates less heat than an electromagnetic ballast. The energy saved can be estimated in the range of 20-25% for a given lamp power. Finally the electronic solution allows better control of the filament current and lamp voltage during preheating with the unquestionable benefit of increasing the mean lamp life.

Figure 1. 2x58W T8 ballast demonstration board

August 2008 Rev 1 1/27

www.st.com

Contents AN2771

Contents

1 Basis of half-bridge inverter topology . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Ballast design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 L6585D biasing circuitry (pin by pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 PFC power section design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3 Half-bridge inverter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 Symmetrical and asymmetrical EOL protection: improvements . . . . . . . . 13

4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 Conduction emissions test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 Adapting the design for a 2x36 W T8 electronic ballast . . . . . . . . . . . . . . 21

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/27

AN2771 List of figures

List of figures

Figure 1. 2x58W T8 ballast demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. Electronic lamp ballast - capacitor-to-ground configuration . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Electronic lamp ballast - lamp-to-ground configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. Dual lamp ballast series configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 5. Dual lamp ballast parallel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 6. Electrical schematic 2x58 W T8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 7. TSM101 window comparator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. External symmetrical EOL protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. L6585 startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 10. One lamp ignition phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11. Low-side current in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12. Voltage and current lamp in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13. Asymmetrical EOL protection with broken cathode during run mode. . . . . . . . . . . . . . . . . 19

Figure 14. Symmetrical EOL protection behavior during ignition phase . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 15. Conducted emissions at 230 Vac 50 Hz - line 1 peak detector . . . . . . . . . . . . . . . . . . . . . 21

Figure 16. Conducted emissions at 230 Vac 50 Hz - line 2 peak detector . . . . . . . . . . . . . . . . . . . . . 21

3/27

Basis of half-bridge inverter topology AN2771

1 Basis of half-bridge inverter topology

The half-bridge inverter operates in zero voltage switching (ZVS) resonant mode, to reduce the switching losses and the electromagnetic interference generated by the output wiring and the lamp. Voltage-fed series resonant half-bridge inverters are currently used for compact fluorescent lamp ballasts (CFL) and for many European tube lamp (TL) ballasts.

Generally, for lighting applications, considering the current preheating, it's possible to choose between two different topologies of the resonant circuit: capacitor-to-ground (Figure 2) or lamp-to-ground (Figure 3).

Figure 2. Electronic lamp ballast - capacitor-

to-ground configuration

Figure 3. Electronic lamp ballast - lamp-to-

ground configuration

+

L

RES

V

dc

C

RES

C

Block

_

In the design presented in this application note, a capacitor-to-ground configuration was used. For dual lamp ballast the lamps can be connected in series (Figure 4) or in parallel (Figure 5). In the system presented here, a parallel configuration was chosen for the following reasons:

● lower voltage stress on the ballast output stage components, on the wiring, and on the

fixture sockets

● the resonant L and C associated with the lamps are less sensitive to component

tolerances due to the lower operating lamp voltages compared to the series configuration

● better lamp control as it is possible to independently monitor both lamp operations

Figure 4. Dual lamp ballast series

+

configuration

C

RES

+

L

rRES

V

dc

C

Block

_

Figure 5. Dual lamp ballast parallel

configuration

C

+

RES

C

RES

L

rRES

C

-

Block

L

rPRE

4/27

L

rRES

C

-

Block

AN2771 Main characteristics

2 Main characteristics

The electrical specifications for the electronic lamp ballast are given in Tab le 1 and the schematic for the 2x58 W T8 is presented in Figure 6. The ballast design procedure is detailed in the following section.

Table 1. Input and output parameters

Input parameters

V

IN

f

line

Number 2

Type T8 in parallel configuration

Power 58 W or 36 W

PF Power factor

THD% Total harmonic distortion ≤ 10

η % Efficiency

Input voltage range 185 to 265 V

Line frequency 50/60 Hz

Tube l a mp

Target output parameters

≈ 0.9

≈ 90 %

RMS

5/27

Main characteristics AN2771

Figure 6. Electrical schematic 2x58 W T8

R540RR54

0R

10 kOhm

R26

C15

R25

1.6 kOhm

100 nF, 400V

LAMP2

R53 0R53 0

1

4

L2

R22

23

T8 Lamp1-58W

R40

1.8 mHL21.8 mH

1 5

Q4

R23

C25

CAP NP

C25

CAP NP

0.33 ohm 1% 1W

100 nF, 400V

R24

1.802 MOhm

68k

STD8NM60NQ4STD8NM60N

62 Ohm

7

8

5

6

Vrin

Crin

+Vcc

Output

Vref1Csense2Crref3GND

U2

56k

R41

C16

R29 10 OhmR29 10 Ohm

D8 1N4148D8 1N4148

R31

D13

1 nF 1kV

D9

C17

LL4148

16VD916V

C18

4

100 nF

C19

0.33 ohm 1% 1W

R56

100nF

4.7uF 50V

TSM101U2TSM101

D12 BAT46ZD12 BAT46Z

D11 BAT46ZD11 BAT46Z

18k

R46

470k

R46

470k

1

Q5

R47

330k

R49

330k

R52 0R52 0

BC847Q5BC847

32

R48 10R48 10

1

Q6

BC847Q6BC847

32

R50

56k

R51 2kR51 2k

2

Q7

XO205MAQ7XO205MA

R55

470

R55

470

1 3

1

32

BC847Q8BC847

Q8

1N4007

D10

D2

R4

R3

STTH1L06D2STTH1L06

560 kOhmR4560 kOhm

560 kOhmR3560 kOhm

R27

R7

R6

0.8 mH

56K

910 kOhmR7910 kOhm

1.5 MOhmR61.5 MOhm

R5

LPFC1

1 MOhmR51 MOhm

C1

1 3

5 8

R13

C2

C21

+

R8

C3

30 KOhm

470//100 nFC2470//100 nF

R30

R12

910 kOhm

R11

1.5 MOhm

100nF 630V

47uF 450V

R320R32

R9

16 kOhmR816 kOhm

33 nFC333 nF

56K

0

390 kOhmR9390 kOhm

C7

R14

240 kOhm

R15

C6

20 kOhm

C5

R16

470//220 nFC7470//220 nF

1.2 MOhm

470//150C6470//150

1.8 nFC51.8 nF

R33 0R33 0

1 2 3 4 5 6 7 8 9 10

C8

R10

C9

10 nF 1600VC910 nF 1600V

R34

180k

Q2

U1

L6585DU1L6585D

Osc

RF

EOI

Mult

INV

10 nFC810 nF

R19

R18

18 kOhm

15 kOhm

R17

20//11 kOhm

R17

20//11 kOhm

C22

R20

TCH

EOLP

EOL-R

CTR

Comp

13 kOhm

220 pF 1kV

62 Ohm

4

LAMP1

1

2 3

L1

1 5

STD8NM60NQ2STD8NM60N

Boot HSD Out

VCC LSD GND HBCS PFG PFCS ZCD

C12

T8 Lamp1-58W

1.8 mHL11.8 mH

20 19 18 17 16 15 14 13 12 11

D7

BAT46ZD7BAT46Z

100 nF, 400V

R36

68k

R36

68k

Q3

C14

10 nF 1600V

C14

10 nF 1600V

R35

180k

R37

56k

R37

56k

C13

100nF 50V

R21

10 Ohm

STD6NK50ZQ3STD6NK50Z

C4

470 nFC4470 nF

GF1MD6GF1M

D4

GF1MD4GF1M

D6

D5

GF1MD5GF1M

D3

GF1MD3GF1M

C11

100nF 275V X2

C11

100nF 275V X2

43

LPFC2

12

2x39 mH/0.7A

C10

100nF 275V X2

F1 3AF1 3A

213

J1

CON3J1CON3

6/27

C20

1nF 275 VAC Y1

AN2771 Ballast design

3 Ballast design

The design of the major parts of the circuit is described in this section.

3.1 L6585D biasing circuitry (pin by pin)

Designed in high-voltage BCD offline technology, the L6585D embeds a PFC controller, a half-bridge controller, the relevant drivers and the logic necessary to build an electronic ballast.

● Pin 1 OSC is one of the two oscillator inputs. The value of the capacitor connected to

ground defines the half-bridge switching frequency in each operating state. A value of

1.8 nF was chosen.

● Pin 2 RF. The component choice with oscillator capacitance defines the half-bridge

switching frequency in each operating state. A resistor R the run frequency while during preheating the switching frequency is set by the parallel of R

with R13 connected between pins RF and EOI (short-circuit during preheating).

14

Choosing the following frequencies and ignition time:

connected to ground sets

14

=

run

we can immediately calculate R

kHz39f

with the following formula:

14

pre

=

kHz65f

ign

=

ms60t

Equation 1

and for the value of R

13

14

⋅

Cf

5run

326.1

= k20

R

:

Ω=

Equation 2

R326.1

⋅

PRE

145pre

//R

14

41.1RCf

−⋅⋅

) connected between the RF pin and

RUN

Ω=

R

= k30

13

● Pin 3 EOI is a multifunction pin. During preheating the pin is internally shorted to

ground by the logic, so the resistor (R ground sets the preheating switching frequency. During ignition pin EOI becomes high impedance. The ignition time is the time necessary for the pin voltage to exponentially rise from zero to 1.9 V. The growth is steered by the C value of R

has already been calculated and t

13

ign

* R13 time constant. As the

6

at start is fixed, the value of C6 is

calculated by the following formula:

Equation 3

t

C

ign

=

6

R3

⋅

13

nF666

=

7/27

Ballast design AN2771

The value C6=620 nF was chosen. In order to have this value, two capacitors in parallel were mounted C

● Pin 4 TCH is the time counter and it is necessary to establish the preheating time and

=470//150 nF.

6

the protection intervention time (either overcurrent or EOL). To implement the time counter, a R

=690 nF and t

C

7

we can calculate R

parallel network is connected between this pin and ground. Choosing

15C7

=1 sec and considering the internal current generator ICH=34 µA,

pre

as follows:

15

Equation 4

C

7

⋅−

t

pre

= M2.1

R

15

⋅

7

● Pin 5 EOLP is a 2 V reference and allows programming the window comparator of pin 6

63.4

I

CH

lnC

63.4

5.1

Ω=

(EOLR) according to table 5 of the L6585D datasheet. Choosing a reference tracking with the CTR pin and a window voltage amplitude ± 220 mV, we chose R

● Pin 6 EOLR is the input of both the window comparator and a re-lamp comparator.

=240 kΩ.

16

Concerning the window comparator (choosing tracking with CTR pin), the center is the same voltage as the CTR pin so the resistive divider connected across the block capacitor (see C

in Figure 2) is set such that under normal conditions:

block

Equation 5

R

19

()

RRR

++

12719

R

8

()

++

RRR

438

()

RR

+

127

2

⋅=

43

1

+

R

8

V

EOLR

VV

CTREOLR

VV

⇒=

⋅=

BUSpfcCTR

V

BUSpfc

⋅=

2

()

RR

+

R

19

To determine the resistance values of (R7+R12), R19, (R3+R4), R8, decisions concerning pin 7 CTR are needed.

● Pin 7 CTR is a multifunction pin (PFC overvoltage, feedback disconnection, reference

for EOL in case of tracking reading), connected to a resistive divider to the PFC output bus. Establishing the maximum PFC overvoltage (PFC output overshoot e.g. at startup) at V

OVPBUSpfc

pin must be V

= 13 kΩ. From Equation 5, fixing R3+R4 = 1120 kΩ, the following resistance value

R

19

is obtained R

● Pin 8 MULT. Assuming a peak value of V

= 480 V and considering that the correspondent threshold on the CTR

thrCTR

= 16 kΩ.

8

= 3.4 V, we can immediately calculate R7+R

multpkMax

= 1.8 V (at VAC = 265 V) on the

= 1.82 MΩ and

12

multiplier input (MULT, pin 8), the peak value at minimum line voltage is V

MULTpkmin

= 1.8 × 185/265 = 1.25 V which, multiplied by the maximum slope of the multiplier, 0.75, gives 0.94 V peak voltage on current sense (CS, pin 4). Since the linearity limit (1 V) is not exceeded, this is acceptable. Considering about 250 µA current for the divider, the lower resistor is 7.14 kΩ (20//11 kΩ ). To establish the upper resistance value (referring to the PFC section of the L6585D datasheet), the ratio between Vmult and Vin for different input voltage must be evaluated:

8/27

AN2771 Ballast design

Equation 6

RRR

9517

inMin

V

=

V2

⋅

inMax

V

CSclamp

slopemax

maxmultPK

=

axmultSlopeM

3

−

108.4

⋅=

1

V2

⋅

inMin

3

−

101.5

⋅=

V

inMin

⇒

R

V

⇒

inMax

R

17

()

RRR

++

9517

17

()

++

V

=

⋅

V2

where:

● V

CSclamp

● max slope is the maximum slope of the multiplier characteristic family for L6585D

● V

multSlopeMax

is the clamp value of the voltage current sense for L6585D

is the maximum voltage in the mult pin with Vin=V

inMin

To work in the linear area of the multiplier characteristic family, the upper resistance choice is made considering the lowest of ratios calculated in R

● Pin 9 COMP is the output of the E/A and also one of the two inputs of the multiplier. The

= 1.390 MΩ was mounted.

5+R9

Equation 6 ⇒ R

=1.487 MΩ.

5+R9

feedback compensation network, placed between this pin and INV (10), is simply a capacitor calculated as follows (considering R

is the upper resistance of the

6+R11

voltage divider between the PFC bus and COMP pin):

Equation 7

C

=

2

10

()

RR2

+⋅π⋅

116

nF530

=

A value of C2=560 nF was chosen.

● Pin 10 INV. To implement the voltage control loop, a resistive divider (Figure 6) is

connected between the regulated output voltage V pin. The internal reference on the noninverting input of the E/A is 2.5 V, so R

Figure 6) are then selected, establishing a max overvoltage ∆V

(

= 420 V of the boost and the

BUSpfc

OVPBUSpfc

and R

6

= 60 V, as

11

follows:

Equation 8

V

RR

where I

+

R

18

RR

=+ M3

116

18

= 20 µA is the threshold current flowing through the compensation network in

OVPth

116

V

∆

OVPBUSpfc

I

BUSpfc

OVPth

1

−=

5.2

Ω=

Ω⇒Ω=⇒ k18k964.17R

case an abrupt load drop happens.

● Pin 11 ZCD is the input to the zero current detector circuit. The ZCD pin is connected to

the auxiliary winding of the boost inductor through a limiting resistor. The ZCD circuit is negative-going edge-triggered: when the voltage on the pin falls below 0.7 V, the PWM latch is set and the MOSFET is turned on. To do so, however, the circuit must first be armed. Prior to falling below 0.7 V, the voltage on pin 11 must experience a positivegoing edge exceeding 1.4 V (due to the MOSFET's turnoff). The maximum main-to-

9/27