ST AN2761 Application note

AN2761

Application note

Solution for designing a transition mode

PFC preregulator with the L6562A

Introduction

The TM (transition mode) technique is widely used for power factor correction in low and
middle power applications, such as lamp ballasts, high-end adapters, flat TVs and monitors,
and PC power supplies. The L6562A is the latest proposal from STMicroelectronics for this
market as well as emerging markets that may require a low-cost power factor correction.
Based on a well-established architecture, the L6562A offers excellent performance that
considerably enlarges its field of application.

Figure 1. L6562A PFC controller in an SMPS architecture

SMPS

400 VDC

Cin

PFC

CONV.
DC-DC

EMI

filter

PFC controller:

L6562A

November 2009 Doc ID 14690 Rev 2 1/36

www.st.com

Contents AN2761

Contents

1 Introduction to power factor correction . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 TM PFC operation (boost topology) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Designing a TM PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3 Power section design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.3.1 Bridge rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.3.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3.4 Boost inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3.5 Power MOSFET selection and dissipation . . . . . . . . . . . . . . . . . . . . . . . 14

3.3.6 Boost diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4 L6562A biasing circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 Design example using the L6562A-TM PFC Excel spreadsheet . . . . . 25

5 EVL6562A-TM-80W demonstration board . . . . . . . . . . . . . . . . . . . . . . . 27

6 Test results and significant waveforms . . . . . . . . . . . . . . . . . . . . . . . . 29

7 L6562A layout hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2/36 Doc ID 14690 Rev 2

AN2761 List of figures

List of figures

Figure 1. L6562A PFC controller in an SMPS architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. Boost converter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Inductor current waveform and MOSFET timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. Switching frequency fixing the line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5. Transition angle versus input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6. Capacitive losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 7. Conduction losses and total losses in the STP8NM50 MOSFET for the 80W TM PFC . . . 17

Figure 8. L6562A internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. Bode plot - open-loop transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10. Bode plot - phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. Multiplier characteristics family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12. Optimum MOSFET turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 13. Excel spreadsheet design specification input table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 14. Other design data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 15. Excel spreadsheet TM PFC schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 16. Excel spreadsheet BOM - 80 W TM PFC based on L6562A . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 17. EVL6562A-TM-80W demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 18. Wide range 80W demonstration board electrical circuit (EVL6562A-TM-80W) . . . . . . . . . 27

Figure 19. EVL6562A-TM-80W compliance to EN61000-3-2 standard . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 20. EVL6562A-TM-80W compliance to JEIDA-MITI standard . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 21. EVL6562A-TM-80W power factor vs. Vin and load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 22. EVL6562A-TM-80W THD vs. Vin and load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 23. EVL6562A-TM-80W efficiency vs. Vin and load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 24. EVL6562A-TM-80W static Vout regulation vs. Vin and load . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 25. EVL6562A-TM-80W input current at 100 V-50 Hz - 80 W load . . . . . . . . . . . . . . . . . . . . . 31

Figure 26. EVL6562A-TM-80W input current at 230 V-50 Hz - 80 W load . . . . . . . . . . . . . . . . . . . . . 31

Figure 27. EVL6562A-TM-80W input current at 100 V-50 Hz - 40 W load . . . . . . . . . . . . . . . . . . . . . 31

Figure 28. EVL6562A-TM-80W input current at 230 V-50 Hz - 40 W load . . . . . . . . . . . . . . . . . . . . . 31

Figure 29. EVL6562A-TM-80W input current at 100 V-50 Hz - 20 W load . . . . . . . . . . . . . . . . . . . . . 32

Figure 30. EVL6562A-TM-80W input current at 230 V-50 Hz - 20 W load . . . . . . . . . . . . . . . . . . . . . 32

Doc ID 14690 Rev 2 3/36

Introduction to power factor correction AN2761

1 Introduction to power factor correction

The front-end stage of conventional offline converters, typically consisting of a full-wave
rectifier bridge with a capacitor filter, has an unregulated DC bus from the AC mains. The
filter capacitor must be large enough to have a relatively low ripple superimposed on the DC
level. This means that the instantaneous line voltage is below the voltage on the capacitor
most of the time, thus the rectifiers conduct only for a small portion of each line half-cycle.
The current drawn from the mains is then a series of narrow pulses whose amplitude is 5-10
times higher than the resulting DC value. Many drawbacks result such as a much higher
peak and RMS current down from the line, distortion of the AC line voltage, overcurrents in
the neutral line of the three-phase systems and, consequently, a poor utilization of the power
system's energy capability. This can be measured in terms of either total harmonic distortion
(THD), as norms provide for, or power factor (PF), intended as the ratio between the real
power (the one transferred to the output) and the apparent power (RMS line voltage times
RMS line current) drawn from the mains, which is more immediate. A traditional input stage
with capacitive filter has a low PF (0.5-0.7) and a high THD (>100%). By using switching
techniques, a power factor corrector (PFC) preregulator, located between the rectifier bridge
and the filter capacitor, allows drawing a quasi-sinusoidal current from the mains, in phase
with the line voltage. The PF becomes very close to 1 (more than 0.99 is possible) and the
previously mentioned drawbacks are eliminated. Theoretically, any switching topology can
be used to achieve a high PF but, in practice, the boost topology has become the most
popular thanks to the advantages it offers:

● primarily because the circuit requires the fewest external parts (low-cost solution)

● the boost inductor located between the bridge and the switch causes the input di/dt to

be low, thus minimizing the noise generated at the input and, therefore, the
requirements on the input EMI filter

● the switch is source-grounded, therefore easy to drive

However, boost topology requires the DC output voltage to be higher than the maximum
expected line peak voltage (400 VDC is a typical value for 230 V or wide-range mains
applications). In addition, there is no isolation between the input and output, thus any line
voltage surge is passed on to the output. Two methods of controlling a PFC preregulator are
currently widely used: the fixed frequency average current mode PWM (FF PWM) and the
transition mode (TM) PWM (fixed ON-time, variable frequency). The first method needs a
complex control that requires a sophisticated controller IC (ST's L4981A, with the variant of
the frequency modulation offered by the L4981B) and a considerable component count. The
second one requires a simpler control (implemented by ST's L6562A), much fewer external
parts and is therefore much less expensive. With the first method the boost inductor works
in continuous conduction mode, while TM makes the inductor work on the boundary
between continuous and discontinuous mode, by definition. For a given throughput power,
TM operation involves higher peak currents. This, also consistently with cost considerations,
suggests its use in a lower power range (typically below 200 W), while the former is
recommended for higher power levels. For completion, FF PWM is not the only alternative
when CCM operation is desired. FF PWM modulates both switch ON and OFF times (their
sum is constant by definition), and a given converter operates in either CCM or DCM
depending on the input voltage and the load conditions. Exactly the same result can be
achieved if the ON-time only is modulated and the OFF-time is kept constant, in which case,
however, the switching frequency is no longer fixed. This is referred to as "fixed-OFF-time"
(FOT) control. Peak-current-mode control can still be used. In this application note transition
mode is studied in depth.

4/36 Doc ID 14690 Rev 2

AN2761 TM PFC operation (boost topology)

2 TM PFC operation (boost topology)

The operation of the PFC transition mode controlled boost converter, can be summarized in
the following description.

The AC mains voltage is rectified by a bridge and the rectified voltage is delivered to the
boost converter. This, using a switching technique, boosts the rectified input voltage to a
regulated DC output voltage (Vo).

The boost converter consists of a boost inductor (L), a controlled power switch (Q), a catch
diode (D), an output capacitor (Co) and, obviously, a control circuitry (see Figure 2).

The goal is to shape the input current in a sinusoidal fashion, in phase with the input
sinusoidal voltage. To do this the L6562A uses the transition mode technique.

Figure 2. Boost converter circuit

The error amplifier compares a partition of the output voltage of the boost converter with an
internal reference, generating an error signal proportional to the difference between them. If
the bandwidth of the error amplifier is narrow enough (below 20 Hz), the error signal is a DC
value over a given half-cycle.

The error signal is fed into the multiplier block and multiplied by a partition of the rectified
mains voltage. The result is a rectified sinusoid whose peak amplitude depends on the
mains peak voltage and the value of the error signal.

The output of the multiplier is in turn fed into the (+) input of the current comparator, thus it
represents a sinusoidal reference for PWM. In fact, as the voltage on the current sense pin
(instantaneous inductor current times the sense resistor) equals the value on the (+) of the
current comparator, the conduction of the MOSFET is terminated. As a consequence, the
peak inductor current is enveloped by a rectified sinusoid. As demonstrated in Section 3.3.4,
TM control causes a constant ON-time operation over each line half-cycle.

After the MOSFET has been turned off, the boost inductor discharges its energy into the
load until its current goes to zero. The boost inductor has now run out of energy, the drain
node is floating and the inductor resonates with the total capacitance of the drain. The drain
voltage drops rapidly below the instantaneous line voltage and the signal on ZCD drives the
MOSFET on again and another conversion cycle starts.

This low voltage across the MOSFET at turn-on reduces both the switching losses and the
total drain capacitance energy that is dissipated inside the MOSFET.

The resulting inductor current and the timing intervals of the MOSFET are shown in

Figure 3, where it is also shown that, by geometric relationships, the average input current

Doc ID 14690 Rev 2 5/36

TM PFC operation (boost topology) AN2761

(the one which is drawn from the mains) is just one-half of the peak inductor current
waveform.

Figure 3. Inductor current waveform and MOSFET timing

ILpk

IL

ISW

ID

IAC

ON

MOSFET

OFF

The system operates not exactly on, but very close to, the boundary between continuous
and discontinuous current mode and that is why this system is called a transition mode PFC.

Besides the simplicity and the few external parts required, this system minimizes the
inductor size due to the low inductance value needed. On the other hand, the high current
ripple on the inductor involves high RMS current and high noise on the rectified main bus,
which needs a heavier EMI filter to be rejected. These drawbacks limit the use of the TM
PFC to lower power range applications.

6/36 Doc ID 14690 Rev 2

AN2761 Designing a TM PFC

=

=

=

=

=

=

3 Designing a TM PFC

3.1 Input specification

The following is a possible design flowchart in reference to a transition mode PFC, using the
L6562A. This first part is a detailed specification of the operating conditions of the circuit that
is needed for the following calculation. In this example a 80 W, wide input range mains PFC
circuit has been considered. Some design criteria are also given.

● Mains voltage range (Vac rms):

● Minimum mains frequency:

● Rated output power (W):

min

max

l

out

Vac85VAC

(1)

Vac265VAC

Hz47f

W80P

(2)

(3)

Because the PFC is a boost topology the regulated output voltage depends strongly on the
maximum AC input voltage. In fact, for boost correct operation the output voltage must
always be higher than the input and thus, because the Vin max is V

VAC

max

2 374=⋅

pk

the output has been set at 400 Vdc as the typical value. If the input voltage is higher, as
typical in ballast applications, the output voltage must be set higher accordingly. As a rule of
thumb the output voltage must be set 6/7% higher than the maximum input voltage peak.

● Regulated DC output voltage (Vdc):

out

V400V

(4)

,

The target efficiency and PF are set here at minimum input voltage and maximum load.
They are used for the following operating condition calculations of the PFC. Of course at
high input voltage the efficiency is higher.

● Expected efficiency (%):

● Expected power factor:

Doc ID 14690 Rev 2 7/36

P

out

P

in

%93

==η

99.0PF

(5)

(6)

Designing a TM PFC AN2761

=

Δ

=

Δ

=

=

=

=

Because of the narrow loop voltage bandwidth, the PFC output can face overvoltages at
startup or in case of load transients. To prevent from excessive output voltage that can
overstress the output components and the load, the L6562A integrates an OVP. The
overvoltage protection sets the extra voltage overimposed at Vout:

● Maximum output overvoltage (Vdc):

The mains frequency generates a 2f

L

V55OVP

(7)

voltage ripple on the output voltage at full load. The

ripple amplitude determines the current flowing into the output capacitor and the ESR.

Additionally, a certain holdup capability in case of mains dips can be requested of the PFC
in which case the output capacitor must also be dimensioned, taking into account the
required minimum voltage value (V

● Maximum output low-frequency ripple:

● Minimum output voltage after line drop

(Vdc):

● Holdup capability (ms):

) after the elapsed holdup time (t

out min

out

minout

Hold

),

Hold

V20V

V300V

ms10t

(8)

(9)

(10)

The PFC minimum switching frequency is one of the main parameters used to dimension
the boost inductor. Here we consider the switching frequency at low mains on the top of the
sinusoid and at full load conditions. As a rule of thumb, the switching frequency must be
higher than the audio bandwidth in order to avoid audible noise and additionally it must not
interfere with the L6562A minimum internal starter period, as given in the datasheet. On the
other hand, if the minimum frequency is set too high, the circuit shows excessive losses at a
higher input voltage and probably operates skipping switching cycles not only at light load.
The typical minimum frequency range is 20÷50 kHz for wide range operation.

● Minimum switching frequency (kHz):

minsw

kHz35f

(11)

In order to properly select the power components of the PFC and dimension the heat sinks
in case they are needed, the maximum operating ambient temperature around the PFC
circuitry must be known. Please note that this is not the maximum external operating
temperature of the entire equipment, but it is the local temperature at which the PFC
components are working.

● Maximum ambient temperature (°C):

8/36 Doc ID 14690 Rev 2

ambx

C50T

°

(12)

AN2761 Designing a TM PFC

3.2 Operating condition

The first step is to define the main parameters of the circuit, using the specifications given in

Section 3.1:

● Rated DC output

current:

● Maximum input power:

● RMS input current:

● Peak inductor current:

As shown in

Figure 3, the inductor current is a triangle shape at switching frequency, and

P

in

I

=

in

I =

out

P

=

P

in

min

out

η

P

out

I

V

out

PFVAC

⋅

I22IL ⋅⋅=

inpk

out

P

in

I

=

in

pk

93

W80

V400

W80

A2.0

==

=⋅=

W86

⋅

W02.86100

=

99.0Vac85

=⋅⋅=

(13)

(14)

(15)

A02.1

(16)

A89.2A02.122IL

the peak of triangle is twice its average value. The average value of the inductor current is
exactly the peak of the input sine wave current, and therefore it can be easily calculated as
its rms value is obtained from equation

(15). To write down a complete inductor specification

for the inductor manufacturer we also provide the RMS and the AC current that can be
calculated using equations

(17) and (18).

● RMS inductor current:

● AC inductor

current:

IL ⋅=

2

rmsac

2

I

IL

inrms

3

2

IILIL −=

in

()( )

ac

rms

2

A18.1A02.1

=⋅=

(17)

3

22

=−=

(18)

A59.0A02.118.1IL

The current flowing in the inductor can be split in two parts, depending on the instant of
conduction. During the on time, the current increases from zero up to the peak value and
circulates into the switch, while during the following off-time the current decreases from
peak down to zero and circulates into the diode. Therefore there is a current with a triangular
wave, with the same peak value equal to the inductor current flowing into these two
components. Thus, it is also possible to calculate the RMS current flowing into the switch
and into the diode (

Figure 3), needed to calculate the losses of these two elements.

Doc ID 14690 Rev 2 9/36

Designing a TM PFC AN2761

● RMS switch current:

● RMS diode current:

3.3 Power section design

3.3.1 Bridge rectifier

The input rectifier bridge can use standard, slow-recovery, low-cost devices. Typically a
600 V device is selected in order to have good margin against mains surges. An NTC
resistor limiting the current at plug-in is required to avoid overstress to the rectifier bridge
and fuse.

ILISW ⋅

pkrms

rms

ILID ⋅

pkrms

rms

VAC

1
6

24

⋅

−⋅=

9

π

min

V

out

(19)

Vac85

−⋅=

π

VAC

24

24

⋅

9

π

min

V

out

Vac85

V400

=⋅

V400

A01.1

=⋅

(20)

A59.0

1

A89.2ISW

6

24

⋅

⋅=

9

π

⋅

A89.2ID

⋅=

9

The rectifier bridge power dissipation can be calculated using equations

(21), (22), (23). The

threshold voltage and dynamic resistance of a single diode of the bridge can be found in the
component datasheet.

I2

⋅

I

inrms

I

avg_in

in

=

=

=

2

⋅

I2

in

=

π

A02.12

⋅

2

⋅

A02.12

π

A72.0

=

A46.0

=

(21)

(22)

The power dissipated on the bridge is:

bridge

2

diodebridge

inrms

2

IV4IR4P ⋅⋅+⋅⋅=

avg_inth

W98.1A46.0V14)A72.0(07.04P

=⋅⋅+⋅Ω⋅=

(23)

10/36 Doc ID 14690 Rev 2

AN2761 Designing a TM PFC

=

3.3.2 Input capacitor

The input high-frequency filter capacitor (Cin) has to attenuate the switching noise due to
the high-frequency inductor current ripple (twice the average line current,

The worst conditions occur at the peak of the minimum rated input voltage.

The maximum high-frequency voltage ripple across Cin is usually imposed between 5% and
20% of the minimum rated input voltage. This is expressed by a coefficient r (from 0.05 to

0.2) as an input design parameter:

● Ripple voltage coefficient (%):

C

=

in

I

in

VACrf2

⋅⋅⋅π

minminsw

C

=

in

A02.1

Vac852.0kHz352

⋅⋅⋅π

In real conditions the input capacitance is designed taking the EMI filter into account and a
tolerance on the component of about 5% -10% (typical for polyester capacitors).

A commercial value of Cin = 0.22 µF has been selected. Of course a bigger capacitor
provides a benefit from the EMI point of view but worsens the THD, especially at high mains.
Therefore a compromise must be found between these two parameters. A good quality film
capacitor for this component must be selected in order to provide good filtering
effectiveness.

Figure 3).

2.0r

F26.0

μ=

(24)

(25)

3.3.3 Output capacitor

The output bulk capacitor (Co) selection depends on the DC output voltage (4), the allowed
overvoltage

The 100/120 Hz (twice the mains frequency) voltage ripple (
value) is a function of the capacitor impedance and the peak capacitor current:

With a low ESR capacitor the capacitive reactance is dominant, therefore:

C

O

ΔVout is usually selected in the range of 1.5% of the output voltage.

Although ESR usually does not affect the output ripple, it should be taken into account for
power loss calculations. The total RMS capacitor ripple current, including mains frequency
and switching frequency components, is:

(7) and the converter output power(3).

I

Crms

out

Vf2

Δ⋅⋅π

outl

≥

ΔVout = peak-to-peak ripple

I2V +

⋅⋅=Δ

outout

P

=

2

rms

out

VVf2

Δ⋅⋅⋅π

2

IIDI −=

out

Crms

1

2

)Cf22(

⋅⋅π

Ol

C

≥

outoutl

O

()()

ESR

2

W80

V20V400Hz472

⋅⋅⋅π

22

A56.0A20.0A59.0I

=−=

(26)

F8.33

μ=

(27)

(28)

Doc ID 14690 Rev 2 11/36