ST AN2715 Application note

AN2715

Application note

IBIS models for signal integrity

simulation of SPEAr600 applications

Introduction

This application note is intended for hardware developers that are using the SPEAr600 embedded MPU in their target design.

The IBIS models are mandatory to run signal integrity simulation in the application PCB. PCB simulation is very important to make sure that the layout of the PCB does not introduce any functional problems or timing marginality in high speed interfaces like DDR2 and Ethernet.

The IBIS models provided for SPEAr600 are organized in a model library containing several models for each I/O pin (or for a functional group of I/Os). Each I/O pin or functional group of I/O has a set of models; each model corresponds to a certain operating mode of the I/O pads.

The operating modes are programmable and are defined by a proper setting of two registers, one in the miscellaneous register block and the other one in the memory controller block of the SPEAr600 device (for more details please refer to the miscellaneous registers and memory controller sections of the SPEAr600 user manual).

This document explains how to select the correct model from the library sp600_v13.ibs after reading the register settings or knowing the operating mode from the SPEAr600 user manual.

Note: The registers referred to in this document are described in detail in the SPEAr600 user

manual.

December 2009 Doc ID 14454 Rev 1 1/12

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PL_CLK & PL_GPIO IBIS model selection AN2715

1 PL_CLK & PL_GPIO IBIS model selection

The I/O signals of the PL_CLK & PL_GPIO interface form two main groups. Please refer to the following table for the I/O signals and the associated model name.

Table 1. Relation between the PL_.... block signals and the used model

PL_.... block signal name IBIS model group name

PL_CLK[4:1] PL_CLK

PL_GPIO[83:0] PL_GPIO

2/12 Doc ID 14454 Rev 1

AN2715 GMAC IBIS model selection

2 GMAC IBIS model selection

The I/O signals of the GMAC interface form two main groups. Please refer to the following table for the I/O signals and the associated model name.

Table 2. Relation between the GMAC block signals and the used model

GMAC block signal name IBIS model group name

GMII_TXCLK GMII_TXCLK125 MII_TXCLK TXD_0 TXD_1 TXD_2 TXD_3 GMII_TXD_4 GMII_TXD_5 GMII_TXD_6 GMII_TXD_7 TX_ER TX_EN RX_ER RX_DV RX_CLK RXD_0 RXD_1 RXD_2 RXD_3 GMII_RXD_4 GMII_RXD_5 GMII_RXD_7 GMII_RXD_6 COL CRS

MDIO MDC

GMAC_HF

GMAC_LF

Doc ID 14454 Rev 1 3/12

SMI IBIS model selection AN2715

3 SMI IBIS model selection

The I/O signals of the SMI interface form two main groups. Please refer to the following table for the SMI interface I/O signals and the associated model name.

Table 3. Relation between the SMI block signals and the used model

SMI block signal name IBIS model group name

SMI_CLK SMIDATAIN SMIDATAOUT SMICS_0 SMICS_1

PL_GPIO

4/12 Doc ID 14454 Rev 1

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