The general purpose I/O (GPIO) ports of STR7xx devices are programmable by firmware in
several modes: input, output, alternate function, output open drain, output push-pull,
bidirectional weak push-pull and high impedance. It is possible to manage the analog input
mode as well.
This application note describes the best way of configuring the GPIO ports.
Each of the general purpose I/O ports has three 16-bit Configuration registers (PC0, PC1,
PC2) and one 16-bit Data register (PD).
Subject to the specific hardware characteristics of each I/O port listed in the “Pin
description” table provided in the relevant STR7x datasheet, each port bit can be individually
configured as an input, output, alternate function, etc.
Each I/O port bit is freely programmable, however the I/O port registers have to be accessed
as 16-bit words. 32-bit or byte access is not allowed.
Figure 1 shows the basic structure of an I/O port bit.
Figure 1.Basic structure of an I/O port bit
To on-chip peripheral
Read/Write
I/O Data register
From on-chip peripheral
Alternate function (IN)
Input latch
Output latch
Alternate function (OUT)
TTL
CMOS
Analog input
Push-pull
Tristate
Open drain
Weak push-p ull
I/O pin
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AN2710STR71x & STR73x I/O ports
Table 1.STR71x port bit configuration table
Port Configuration
Registers (bit)
(1)
Val ues
PC0(n)01010101
PC1(n)00110011
PC2(n)00001111
ConfigurationHiZ/AINININIPUPDOUTOUTAFAF
Output TRITRITRIWPODPPODPP
Input AINTTLCMOSCMOSNANACMOSCMOS
1. AF = alternate function, AIN = analog input, HiZ = high impedance, IN = input, IPUPD = input pull-up/pulldown, OD = open drain, OUT = output, PP = push-pull, TRI = tristate, TTL = TTL input levels, WP = weak
push-pull.
NA = not applicable. In Output mode, a read access the port will get the output latch value). See Figure 4.
Table 2.STR73x port bit configuration table
(1)
Port
Configuration
Val ues
Registers (bit)
PC0(n)01 0 10101
PC1(n)00 1 10011
PC2(n)00 0 01111
ConfigurationHiZ/AININ
Output TRITRIWP
reserved
Input -TTLTTLTTLTTLTTLTTL
1. AF = alternate function, AIN = analog input, HiZ = high impedance, IN = input, IPUPD = input pull-up/pulldown, OD = open drain, OUT = output, PP = push-pull, TRI = tristate, TTL = TTL input levels, WP = weak
push-pull.
2. Depending on the PD(n) value, it behaves as weak pull-up (PD=1) or weak pull-down (PD=0)
1.2 General-purpose I/O (GPIO)
At reset the I/O ports are configured as general-purpose (memory mapped I/O).
When the user writes to the I/O Data register, the data are always loaded into the output
latch. The output latch holds the data to be output while the input latch captures the data
present on the I/O pin.
A read access to the I/O Data register reads the input latch or the output latch depending on
whether the port bit is configured as an input or an output.
IPUPDOUTOUTAFAF
(2)
ODPPODPP
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STR71x & STR73x I/O portsAN2710
1.2.1 Alternate function I/O (AF)
The alternate functions for each pin are listed in the datasheet. Configuring a port bit as
alternate function will disconnect the output latch and connect the pin to the output signal of
an on-chip peripheral.
●For alternate function inputs, the port must be configured in Input mode and the input
pin must be driven externally.
Note:It is also possible to emulate the AFI input pin by firmware by programming the GPIO
controller. In this case, the port should be configured in Alternate Function Output mode.
And obviously, the corresponding port should not be driven externally as it will be driven by
the firmware using the GPIO controller.
●For AF output or input-output, the port bit must be in AF configuration.
External interrupts/wakeup lines
Some ports have external interrupt capability (see datasheet). To use external interrupts, the
port must be configured in input mode. For more information on interrupts and wakeup lines,
refer to the reference manual.
1.2.2 Input configuration
When the I/O port is programmed as Input:
●The output buffer is forced tristate
●The data present on the I/O pin are sampled into the input latch with every clock cycle
●A read access to the Data register gets the value in the input latch.
Figure 2 shows the input configuration of the I/O port bit.
Figure 2.Input configuration
Alternate function (IN)
Input latch
I/O Data register
Output latch
Alternate function (OUT)
1. For STR73x only.
TTL
CMOS
Analog input
(1)
Tristate
I/O pin
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AN2710STR71x & STR73x I/O ports
1.2.3 Input pull-up/pull-down configuration
When the I/O port is programmed as input pull-up/pull-down:
●The output buffer is turned on in weak push-pull configuration and the firmware can
write the appropriate level into the output latch to activate the weak pull-up or pull-down
as required.
●The data in the output latch drive the I/O pin (a logic zero activates a weak pull-down, a
logic one activates a weak pull-up).
●A read access to the I/O Data register gets the input latch value.
Figure 3 shows the Input pull-up/pull-down configuration of the I/O port.
Figure 3.Input pull-up/pull-down configuration
I/O port Data register
1.2.4 Output configuration
When the I/O port is programmed as output:
●The output buffer is turned on in open drain or push-pull configuration
●The data in the output latch drive the I/O pin
●A read access to the I/O Data register gets the output latch value.
Figure 4 shows the output configuration of the I/O port bit.
Input latch
Output latch
Alternate function (IN)
Alternate function (OUT)
PU
PD
Analog input
When AIEN = 1
I/O pin
Weak push-pull
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