2X36 W digital dimmable ballast with L6574 and ST7FDALI
Introduction
This document describes a high-efficiency, high power factor, low THD and digital dimming
electronic ballast designed to drive 2X36 W T8 tube lamps.
The system consists of three main blocks:
The high-frequency ballast includes an active power factor correction circuit based on the
L6562 for universal input voltage as well as a ballast control circuit based on the L6574. The
digital dimming is performed by interfacing the ST7FDALI microcontroller with the analog
half-bridge driver.
The DALI control unit is dedicated to address the slaves, to display the lamp status and to
send the dimming commands. This unit is provided with a keyboard which allows setting
different dimming scenes over a wide range (5-100%) as well as putting in standby and
restarting the ballast. The DALI communication protocol includes single and group mode, as
well as broadcast mode to address the slaves.
The AC-DC adapter is based on the VIPer12A-E. This is an offline double-output isolated
power supply in DCM flyback configuration. The outputs are set for 20 V to supply the
communication bus and for 5 V to supply the MASTER microcontroller.
The three blocks are described in detail and their performances are shown. In addition some
of DALI basics are explained.
Figure 27.VIPer12A-E steady state behavior at full load at 110 V
Figure 28.VIPer12A-E steady state behavior at full load at 230 V
Figure 29.VIPer12A-E steady state behavior at minimum load at 110 V
Figure 30.VIPer12A-E steady state behavior at minimum load at 230 V
Figure 31.Startup waveforms at full load at 110 V
Figure 32.Startup waveforms at full load at 230 V
Figure 33.Startup waveforms at minimum load at 110 V
Figure 34.Startup waveforms at minimum load at 230 V
Figure 35.Dynamic load waveforms at 110 V
Figure 36.Dynamic load waveforms at 230 V
Figure 40.Conducted emissions at 110 V
Figure 41.Conducted emissions at 110 V
Figure 42.Conducted emissions at 230 V
Figure 43.Conducted emissions at 230 V
AN2708Block diagram and system operating conditions
1 Block diagram and system operating conditions
Figure 1 shows the block diagram of the system.
Figure 1.System block diagram
HIGH
FREQUENCY
BALLAST
ACíDC ADAPTER
SCI communication is considered as an option.
MASTER UNIT
SCI
Communication
Option
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Block diagram and system operating conditionsAN2708
The present system has been designed according to the following specifications:
Table 1.System operating conditions
ParameterValue
Input voltage range176-265 Vac/50 Hz; 90-140 Vac/60 Hz
Lamp type2X36 W T8 tube lamps
Circuit power (max)80 W
Lamp power (max)72 W
Dimming range5% to 100%
Power factor> 0.99
Current THD< 10%
Warm start< 1.5 sec
Standby mode power< 0. 6 W
In addition to the previous specs, the DALI communications are optically isolated, the digital
dimming is performed with high precision, and the lamp filament preheating time is
programmable as well as the ignition time.
Figure 2.2X36 W digital dimmable ballast with L6574 and ST7FDALI
HIGH FREQUENCY BALLAST
MASTER UNIT
MASTER UNIT
ACíDC
ACíDC
ADAPTE R
ADAPTE R
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AN2708High-frequency ballast
2 High-frequency ballast
This section describes the high-frequency ballast board which includes the power factor
correction stage, the half-bridge inverter driving circuitry, the output stage and the DALI
slave unit. The schematic of the board is shown in Figure 3.
This block is essentially a "double board" as the DALI slave board and its external circuitry
are mounted on a small separated board which is connected to the bottom side by means of
a 7-pin connector. Ta bl e 2 shows the ballast-slave communication.
Table 2.Ballast-slave communication
Pin ref.DescriptionAnalog stage Microcontroller
1PWM0 (ref op-amp)
2Disable L6574 EN1 & disconnected lamp
3Enable L6574 EN2 & not ignited lamp
4GND
55 VDD
6PB2 disable PFC
7SIGN (lamp failure)
Table 3.Ballast bill of material
ReferenceValueDescription
BridgeW08G 1.5 A 800 V Bridge rectifier
Cout, CVdd10 µF 25 VElectrolytic cap
C7,Cf4.7 µF 50 VElectrolytic cap
Cfb22 nF 25 VCeramic cap
Cin1,Cin23.3 µF 450 VElectrolytic cap
C1100 nF 400 VPolyester cap
C210 nF 50 VCeramic cap
C3330 nF 50 VCeramic cap
C41000 nF 50 VCeramic cap
C5,C8,C9,C1
9
C647 µF 450 VElectrolytic cap
C14100 nF 100 VCeramic cap
C104.7 nF 100 VCeramic cap
C111 nF 630 VEvox Rifa polypropylene cap Rs
C12470 pF 50 VCeramic cap
C131 µF 50 VCeramic cap
C15330 µF 25 VElectrolytic cap
100 nF 50 VCeramic cap
= 5 Ω at 100 kHz
max
C1610 nF 25 VCeramic cap
C17, C21100 nF 250 VPolyester cap
C18,C208.2 nF 1600 VPolyester cap
C422.2 µF16 VElectrolytic cap
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AN2708High-frequency ballast
Table 3.Ballast bill of material (continued)
ReferenceValueDescription
C431 µF 20 VSMD tantalum cap
C44,C45100 nF 50 V0805 SMD cap
C4622 µF 20 V SMD tantalum cap
C7233 nF 50 V0805 SMD cap
C7368 pF 50 V0805 SMD cap
DZ1,DZ215 V 0.5 WZener diode
D2,D13,D14STTH1L06
D3,D4,D8,D1
1
1N4148Small signal rectifier 200 mA 100 V
STMicroelectronics ultrafast high voltage rectifier 1 A 600
V
D5,D6,D7,D9
, D10,D61
D1218 V 0.5 W Zener diode
D151N4007 1 A 1000 VGeneral purpose rectifier
D16MB2S 0.5 A 200 V SMD bridge rectifier
D17BAS16Small signal diode
D18BZX284C 2V70.5 W Zener diode
FUSE4 A 250 VRadial fuse
J1Input 250 V connector3-way PCB screw terminal, 5.08 mm
J2Ballast-slave connector7-way strip line socket
J3Dali Bus2-way vertical PCB header, 3.81 mm pitch
J4Ballast-slave connector7-way strip line connector
U7LE50CZ TO-92STMicroelectronics very low drop voltage regulators
U8VIPer12A-E DIP8
U9,U10SFH6156-2Optocoupler
U11ST7FDALIF2M6 SO20
680 kΩResistor
100 kΩ2 W resistor
STMicroelectronics offline SMPS primary IC 730 V 0.4 A
27R
STMicroelectronics
8-bit MCU with single voltage Flash memory, data
EEPROM, ADC, timers, SPI, DALI
Note:Resistors are 0.25 W unless specified. Q1, Q2 &Q3 are mounted with 8 °C/W heatsink.
2.1 PFC converter
This block allows drawing a quasi-sinusoidal current from the mains, in phase with the line
voltage in order to get a PF very close to 1 (more than 0.99).
To achieve such high PF the boost topology is implemented because of the advantages it
offers:
●Minimum number of external components, thus making it a low-costsolution
●Low input di/dt thus minimizing the noise generated at the input and, therefore, the
requirements on the input EMI filter
●The switch is source-grounded, therefore is easy to drive
However, boost topology requires the DC output voltage (400 Vdc) to be higher than the
maximum expected line peak voltage.
ST's L6562 has been used as the driver. It implements a transition mode control (fixed ON
time, variable frequency), that, for such output power, is preferred to the fixed frequency
average current mode being simpler and cheaper. The circuit operates on the boundary
between continuous and discontinuous current mode.
Besides providing good results in terms of power factor, this IC considerably reduces the
Total Harmonic Distortion (THD) as it reduces the conduction dead-angle that occurs to the
AC input current near the zero-crossings of the line voltage.
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High-frequency ballastAN2708
The basic design specifications are listed in Tab le 4 .
Table 4.PFC operating conditions
ParameterValue
Mains voltage range: Virms(min) - Virms(max) 90 – 265 Vac
Regulated DC output voltage: Vo400 Vdc
Rated output power: Po75 W
Minimum switching frequency: f
sw
Maximum output voltage ripple: ∆Vo< ± 10 V
35 kHz
Maximum overvoltage admitted: ∆V
Expected efficiency: η
PFC
OVP
60 V
> 90 V
For reference, it is useful to define also the following quantities:
●Input power: Pi (= Po / η ) ≈ 80 W
●Maximum mains RMS current: Iirms (= Pi/Virms(min)) ≈ 1 A
●Rated output current: Io (= Po/Vo) ≈ 0.2 A
The design guidelines are deeply explained in AN966 ("L6561, enhanced transition mode
power factor corrector"), AN1757 ("Switching from the L6561 to the L6562) and AN1089
("control loop model of L6561-based TM PFC"). The main design formulas are summarized
as follows inTab le 5.