ST AN2683 Application note

AN2683

Application note

Compact dual output point of load converter based on the PM6680 step-down controller

Introduction

This application note demonstrates the performance of the PM6680 dual step-down controller by implementing a two output point of load converter in a small printed circuit board footprint. Utilizing constant on-time architecture and featuring a no-audio skip mode of operation, a common bus voltage that ranges between 10 to 16 VDC is converted to 1.0 VDC at 10.5 amps and 1.8 VDC at 2.5 amps for a total output power level of 15 watts. The unique no-audio skip feature significantly improves efficiency at light load. Using surface mount components on both the top and bottom of the circuit board and featuring ceramic output capacitors, the area needed for the converter measures only 1.0 by 1.25 inches (25.4 by 37.75 mm). The method for component value dimensioning is described along with the schematic and construction details. Typical efficiencies and functional test data are also presented.

Figure 1. PM6680 - top and bottom view

April 2008

Rev 1

1/38

www.st.com

Contents	AN2683

Contents

1	Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
	1.1	Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	1.2	Output ripple voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	1.3	Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	1.4	Output overload/short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
2	Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
3	Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
4	Functional testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		26
	4.1	Input/output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
	4.2	Ripple/noise voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
	4.3	Load transient overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
	4.4	Output current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
	4.5	Output short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
	4.6	Input under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
5	Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		35
6	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		37

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AN2683	List of figures

List of figures

Figure 1. PM6680 - top and bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Circuit board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Components of virtual ESR network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4. Top layer component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 5. Top layer copper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 6. Inner layer 1 showing additional power traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 7. Power ground layer (inner layer 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 8. Signal ground layer (inner layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 9. Bottom layer components placement (mirrored). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10. Bottom layer copper (mirrored). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 11. Inner layer 4 (mirrored) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 12. Efficiency vs. load current in PWM mode (1.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 13. Efficiency vs. load current in NA-skip mode (1.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 14. Efficiency vs. load current in PWM mode (1.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 15. Efficiency vs. load current in NA-skip mode (1.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 16. VDC output - 100% to 50% load change (20 s/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 17. VDC output - 50% to 100% load change (20 s/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 18. VDC output - 20% to 80% step load change (50 s/div). . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 19. VDC output - 100% to 50% load change (20 s/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 20. VDC output - 50% to 100% load change (20 s/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 21. VDC output - 20% to 80% step load change (50 s/div). . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3/38

List of tables	AN2683

List of tables

Table 1. Input voltage range 10 - 16 VDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 3. 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 4. 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 5. 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6. 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 7. 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 8. 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 9. 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 10. 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 11. 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 12. Part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4/38

AN2683	Main characteristics

1 Main characteristics

1.1Input voltage range

Table 1.	Input voltage range 10 - 16 VDC
Output	Nominal voltage VDC	Max. current amp	Regulation %(1)
1	1.8	2.5	0.44
2	1.0	10.5	2.6

1. Regulation over entire line and load range

1.2Output ripple voltage

●Output 1: 45 mV p-p at maximum output current

●Output 2: 30 mV p-p at maximum output current

1.3Switching frequency

●Output 1: 1 - 300 kHz

●Output 2: 2 - 400 kHz

1.4Output overload/short circuit

●Output 1: nominal trip level 3.37 A (135%)

●Output 2: nominal trip level 13.65 A (130%)

Protection is latched. Power must be cycled to reset.

5/38

Circuit description	AN2683

2 Circuit description

The PM6680 contains all the control circuitry needed to implement two independent stepdown synchronous buck regulators using the constant on-time method. The constant ontime method, an improved variant of hysteretic control, provides superior transient response to changes of input voltage and load levels. One of the big advantages of this control method is that it can provide this quick response without the use of an error amplifier which in turn eliminates the need for frequency compensation.

As shown in the photographs (Figure 1) all the parts used are surface mount type including the inductors. The circuit board is a multiple layer type consisting of six layers. The top two layers are power routing, the middle two are ground layers split as power and signal, and the bottom two are signal routing layers. In this design, in order to have a low inductor value for the higher current 10.5 A output side, the PM6680 runs in its intermediate range with output one running at 300 kHz and output two running at 400 kHz. So as a consequence the 2.5 A output will run at 300 kHz. With the switching frequencies established the dimensions of the other components can be defined.

6/38

AN2683

.2 Figure

P1

Circuit

+

QC

1

R4

3R92

R17

1/4W

110k

C8

Vin 10.2

-

16.0 VDC

P2

C6

C7

1%

1

10 uF

10 uF

10 uF

board

C4

-

QC

C5

R3

4.7uF

C3

0.22uF

47R5

1/8W

0.1uF

1%

C17

R18

2

21

100pF

30.0k

21

C22

K1

K2

2

schematic

C21

4.7uF

1uF

BAT54A

D1

Q1

STS12NH3LL

R1

10R0

5

4

R2

A

2 1

C2

10R0

Vout2

-

1.0 VDC @ 10.5 A

R8

6

3

0.1uF

2 1

R10

5.11k

P3

1

2

R7

7

2

C1

3.74k

26.1k

9

19

31

18

23

0.1uF

1

2

QC

1

2

8

1

7 8

STS8DNF3LL

C10

57.6k

C9

1.8nF

Boot2

Vin

Vcc

LD05

Boot1

10

1

2

Hgate2

C20

C15

C19

0.7uH

11

Phase2

22

2

R9

1.8nF

QC

Vout

1

-

1.8 VDC @ 2.5 A

L1

MLC1550

Hgate1

1

L2

1

47uF

100uF

100uF

13

21

5

P5

R13

Lgate2

Phase1

6

K

MSS1038

R5

1.10k

1

2

12

15

4

2.5

uH

C16

1

750R

Csense2

Lgate1

47uF

R15

14

20

1

R6

2

2

PGnd

D2

10.0k

5

4

Csense1

750R

Q3

K

1

U1

17

3

Open

SGnd1

A

R14

1

P4

D3

6

3

PM6680

V5SW

2

Open

8

29

Out2

10.0k

QC

7

2

Out1

R12

1

2

30

1

2

A

Comp2

R16

2

8

1

Comp1

C13

QC

16

26

C14

2.55k

10.0k

330pF

SGnd2

Q2

Pgood1

22pF

P6

7

FB2

28

2

STS25NH3LL

FB1

27

5

Pgood2

Shdn

R11

nc

Fsel

Skip

Vref

En1

En2

1

2

6

3

24

32

25

4

1.91k

C11

C12

330pF

22pF

C18

description Circuit

0.1uF

7/38

Circuit description	AN2683

As a starting point for the value of the inductors we look at the full load current (Ifl) for each output and let the inductor ripple (Ir) current equal 20 to 30 percent of it. For this design a value of 30 percent is used.

Ir = Ifl * 0.3

for

●Output 1: Ir = 0.75 A

●Output 2: Ir = 3.15 A

Then the values of the inductors are calculated using the formula:

Equation 1:

	Vin – Vout					Vout
L =	------------------------f		I			----------
		sw		r		V	in

where Vin is the nominal input voltage, Vout the output voltage and fsw the switching frequency.

So for input 1:

Equation 2

12 – 1.8	1.8
L = 300kHz---------------------------------------0.75	-------	=	6.8 H
	12

and for output 2:

Equation 3

12 – 1	12
L = 400kHz---------------------------------------3.15	-----	=	0.7 H
	1

The output filter capacitors are roughly approximated so that the change in output voltage (∆Vout) during a positive load transient (load is reduced) is minimized. For this design an output voltage change of two to three percent of the total output voltage is considered acceptable. The formula used is:

Equation 4

C >		L		(Ifl)2
	---------------------------------------------------------------
	2 (V	in	– V	out	) Λ V	out

8/38

AN2683	Circuit description

For output 1 a ∆Vout of 2.5% of 1.8 VDC or 45 mV is used, thus:

Equation 5

46.2 F >		6.8 H (2.5)2
	----------------------------------------------------------
	2	(12 – 1.8) 0.045

This is a nonstandard value so a 47 µF is used.

For output 2 a ∆Vout of 2% of 1.0 VDC or 20 mV is used:

Equation 6

175 F >		0.7 H (10.5)2
	----------------------------------------------------------
	2	(12 – 1.0) 0.020

As the formula indicates the capacitor value should be greater than that calculated. Even though the board area is small, this section allows the use of ceramic capacitors that are comprised of two 100 µF and one 47 µF all in parallel and which still fit in the required footprint.

With these values of capacitors the ripple voltage can be checked. This is dominated by the equivalent series resistance (ESR) of the capacitors. The ESR must be equal or less than the value calculated by:

Equation 7:

≤Vr ESR -----

Ir

where Vr is the output ripple voltage and Ir is the inductor ripple current. The ESR for the capacitors is given in their datasheets at the frequency they are used at as shown in the graphs. The value is basically the same at both 300 and 400 kHz. For the 47 µF the ESR is 2 mΩ and for the 100 µF it is 1.5 mΩ. With these values we can calculate the ripple voltage Vr by:

Equation 8:

Vr = Ir ESR

9/38

Circuit description	AN2683

for output 1:

Equation 9

0.75A 2mΩ= 1.5mV

for output 2:

Equation 10

3.15A 545µΩ= 1.9mV

These values conform to the specification. They are higher in a practical circuit because of parasitic inductance and loop resistance. Good circuit board layout techniques are essential. Additionally, because of the constant on-time control, the system regulates the output voltage by the valley value of the ripple voltage. A minimum amount of ripple voltage of 30 mV should be on the comp pin to accomplish this. Since the calculated ripple voltage is much lower than this, an additional circuit called the virtual ESR network is incorporated to provide the additional voltage. Before addressing this design, the current limit resistor

values will be established. In this design the RDS(on) of the lower MOSFETS is used to implement the current limit. For output 1 with its relatively low output current the MOSFET

chosen was the STS8DNF3LL with a nominal RDS(on) of 18 mΩ. This particular part is a dual, that is two MOSFETs are contained in the same SO-8 package realizing further circuit

board space savings. The current limit is a valley type that operates during the conduction of

the low side MOSFET. A 100 µA internal current generator connected to the Csense pin along with a resistor establishes a voltage to which the voltage generated by the RDS(on) is compared. If the RDS(on) voltage is greater, then the voltage at the Csense pin the generation of a new conduction cycle is inhibited. The value of Rcsense is determined by:

Equation 11:

Rc RDS(on) Ivalley

= -----------------------------------------

sense 100µA

The 18 mΩ value for RDS(on) is a nominal 25 °C number. As current is switched through the device and the ambient is raised, the RDS(on) increases. An increase of approximately

140% is used. Targeting the maximum output current (Ioutmax) at 3.375 A and having a Ir of 0.750 A the valley current value is:

10/38

AN2683				Circuit description
Equation 12
Ivalley	=			Ir
		Iout(max) – --
				2
then:
Equation 13
		0.750
3.375A	–	--------------	=	3.0A
		2
Rcsense is then:
Equation 14
25m-----------------------------------Ω	3.0A =			750Ω
100µA

For output 2 the current levels are substantially higher than output 1 and two discrete MOSFETS must be used. With a nominal input voltage of 12 volts and a one volt output the

low side MOSFET is conducting over 90 percent of the time. This means that the RDS(on) of the low side MOSFET must be as low as possible. For this design the STS25NH3LL

MOSFET with a nominal 3.2 mΩ on resistance is used. Because of the high current and

duty cycle an RDS(on) multiplier of 200% for the Rcsense calculation is used. Again targeting the output 2 maximum current at 13.65 A the valley current is:

Equation 15

13.65A	3.15A	=	12.075A
	– ---------------
	2

Rcsense for output 2 then is:

Equation 16

6.4mΩ 12.75A Ω

-------------------------------------------= 773 100µA

11/38

Circuit description	AN2683

With the maximum output currents established attention can be redirected at designing the virtual ESR network. As mentioned earlier, the ripple voltage should be greater than 30 mV and range between 30 to 50 mV. To derive the necessary minimum value of the virtual ESR (VESR) to produce the ripple voltage the following formula is used:

Equation 17

	0.05V
VESR(min) =	---------------		– ESRcout
	Ir

for output 1:

Equation 18

0.05V	– 2mΩ= 64.6mΩ
---------------
0.75A

for output 2:

Equation 19

	0.05V	– 0.545mΩ=	15.3mΩ
	---------------
	3.15A

The total ESR (ESRtot) is the sum of the virtual ESR (VESR) and the ESR (ESRcout) of the output capacitor.

for output 1:

Equation 20

64.6mΩ + 2mΩ= 66.6mΩ

for output 2:

Equation 21

15.3mΩ + 0.545mΩ= 15.8mΩ

12/38