ST AN2683 Application note
AN2683
Application note
Compact dual output point of load converter
based on the PM6680 step-down controller
Introduction
This application note demonstrates the performance of the PM6680 dual step-down
controller by implementing a two output point of load converter in a small printed circuit
board footprint. Utilizing constant on-time architecture and featuring a no-audio skip mode of
operation, a common bus voltage that ranges between 10 to 16 V
at 10.5 amps and 1.8 V
no-audio skip feature significantly improves efficiency at light load. Using surface mount
components on both the top and bottom of the circuit board and featuring ceramic output
capacitors, the area needed for the converter measures only 1.0 by 1.25 inches (25.4 by
37.75 mm). The method for component value dimensioning is described along with the
schematic and construction details. Typical efficiencies and functional test data are also
presented.
Figure 1. PM6680 - top and bottom view
at 2.5 amps for a total output power level of 15 watts. The unique
DC
is converted to 1.0 VDC
DC
April 2008 Rev 1 1/38
www.st.com
Contents AN2683
Contents
1 Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Output ripple voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Output overload/short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 Functional testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 Input/output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2 Ripple/noise voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3 Load transient overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4 Output current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.5 Output short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.6 Input under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/38
AN2683 List of figures
List of figures
Figure 1. PM6680 - top and bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Circuit board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Components of virtual ESR network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. Top layer component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5. Top layer copper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6. Inner layer 1 showing additional power traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. Power ground layer (inner layer 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Signal ground layer (inner layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Bottom layer components placement (mirrored). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Bottom layer copper (mirrored). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Inner layer 4 (mirrored) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Efficiency vs. load current in PWM mode (1.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Efficiency vs. load current in NA-skip mode (1.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. Efficiency vs. load current in PWM mode (1.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Efficiency vs. load current in NA-skip mode (1.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. V
Figure 17. V
Figure 18. V
Figure 19. V
Figure 20. V
Figure 21. V
output - 100% to 50% load change (20µs/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC
output - 50% to 100% load change (20µs/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC
output - 20% to 80% step load change (50µs/div). . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC
output - 100% to 50% load change (20µs/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC
output - 50% to 100% load change (20µs/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC
output - 20% to 80% step load change (50µs/div). . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC
3/38
List of tables AN2683
List of tables
Table 1. Input voltage range 10 - 16 VDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. 1.0 V
Table 3. 1.8 V
Table 4. 1.0 V
Table 5. 1.8 V
Table 6. 1.0 V
Table 7. 1.8 V
Table 8. 1.0 V
Table 9. 1.8 V
Table 10. 1.0 V
Table 11. 1.8 V
Table 12. Part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DC
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DC
4/38
AN2683 Main characteristics
1 Main characteristics
1.1 Input voltage range
Table 1. Input voltage range 10 - 16 V
Output Nominal voltage VDC Max. current amp Regulation %
11.8 2.5 0.44
2 1.0 10.5 2.6
1. Regulation over entire line and load range
1.2 Output ripple voltage
● Output 1: 45 mV p-p at maximum output current
● Output 2: 30 mV p-p at maximum output current
1.3 Switching frequency
● Output 1: 1 - 300 kHz
● Output 2: 2 - 400 kHz
1.4 Output overload/short circuit
● Output 1: nominal trip level 3.37 A (135%)
● Output 2: nominal trip level 13.65 A (130%)
DC
(1)
Protection is latched. Power must be cycled to reset.
5/38
Circuit description AN2683
2 Circuit description
The PM6680 contains all the control circuitry needed to implement two independent stepdown synchronous buck regulators using the constant on-time method. The constant ontime method, an improved variant of hysteretic control, provides superior transient response
to changes of input voltage and load levels. One of the big advantages of this control
method is that it can provide this quick response without the use of an error amplifier which
in turn eliminates the need for frequency compensation.
As shown in the photographs (Figure 1) all the parts used are surface mount type including
the inductors. The circuit board is a multiple layer type consisting of six layers. The top two
layers are power routing, the middle two are ground layers split as power and signal, and the
bottom two are signal routing layers. In this design, in order to have a low inductor value for
the higher current 10.5 A output side, the PM6680 runs in its intermediate range with output
one running at 300 kHz and output two running at 400 kHz. So as a consequence the 2.5 A
output will run at 300 kHz. With the switching frequencies established the dimensions of the
other components can be defined.
6/38
AN2683 Circuit description
Figure 2. Circuit board schematic
Vout 1 - 1.8 VDC @ 2.5 A
QC
P5
R15
10.0k
R16
D2
Open
A
Q3
3
750R
17
Csense1
U1
1
432
V5SW
PM6680
SGnd1
12
R12
1 2
29
30
Out1
Comp1
Out28PGnd14Csense2
2
10.0k
QC
P6
2.55k
C13
330pF
C14
22pF
28
26
5
En2
4
FB1
Shdn
En1
Pgood1
18
25
Vref
32
Skip
C18
24
0.1uF
Fsel
3
nc
6
Pgood2
FB27SGnd216Comp2
27
C12
22pF
C8
12
R17
110k
R4
3R92
1/4W
12
10 uF
12
C4
1%
C7
10 uF
12
R18
C17
R3
1%
47R5 1/8W
0.22uF
C3
0.1uF
C5
4.7uF
12
C16
47uF
C10
1.8nF
R10
3.74k
1 2
STS8DNF3LL
8
7
C1
R1
10R0
R2
432
0.1uF
23
18
31
19
9
10R0
C2
0.1uF
18
30.0k
100pF
D1BAT54A
12
K2
A
K1
12
C21
1uF
C22
4.7uF
2.5 uH
MSS1038
L2
R9
57.6k
1 2
K
5
6
2
4
1
R6
1 2
21
15
20
22
Boot1
Lgate1
Hgate1
Phase1
LD05
Vcc
Vin
Boot2
Phase2
Hgate2
Lgate2
12
11
10
13
R5
750R
1 2
C6
10 uF
P1
P2
QC
QC
-
+
Vin 10.2 - 16.0 VDC
Q1
STS12NH3LL
765
R7
26.1k
1 2
0.7uH
R8
5.11k
1 2
P3
MLC1550L1
C9 1.8n F
100uF
C19
100uF
C15
47uF
C20
12
R13
QC
765
Q2
A K
D3
Open
P4
QC
2
1
R14
1.10k
10.0k
C11
STS25NH3LL
330pF
R11
1.91k
1 2
Vout2 - 1.0 VDC @ 10.5 A
7/38
Circuit description AN2683
As a starting point for the value of the inductors we look at the full load current (Ifl) for each
output and let the inductor ripple (I
value of 30 percent is used.
I
= I
* 0.3
r
fl
for
● Output 1: I
● Output 2: I
Then the values of the inductors are calculated using the formula:
Equation 1:
= 0.75 A
r
= 3.15 A
r
) current equal 20 to 30 percent of it. For this design a
r
VinV
L
–
------------------------ -
f
⋅
swIr
out
⋅=
V
out
---------- -
V
in
where V
frequency.
So for input 1:
Equation 2
and for output 2:
Equation 3
The output filter capacitors are roughly approximated so that the change in output voltage
(∆V
output voltage change of two to three percent of the total output voltage is considered
acceptable. The formula used is:
is the nominal input voltage, V
in
12 1.8–
----------------------------------------
L
300kHz 0.75⋅
----------------------------------------
L
400kHz 3.15⋅
) during a positive load transient (load is reduced) is minimized. For this design an
out
the output voltage and fsw the switching
out
1.8
------- -
6.8µH=⋅=
12
12 1–
12
------
1
0.7µH=⋅=
Equation 4
----------------------------------------------------------------
C
>
2VinV
⋅⋅
8/38
LI
⋅
–()ΛV
2
()
fl
out
out
AN2683 Circuit description
For output 1 a ∆V
Equation 5
This is a nonstandard value so a 47 µF is used.
For output 2 a ∆V
Equation 6
As the formula indicates the capacitor value should be greater than that calculated. Even
though the board area is small, this section allows the use of ceramic capacitors that are
comprised of two 100 µF and one 47 µF all in parallel and which still fit in the required
footprint.
of 2.5% of 1.8 VDC or 45 mV is used, thus:
out
6.8µH2.5()
46.2µF
of 2% of 1.0 VDC or 20 mV is used:
out
175µF
----------------------------------------------------------
>
2121.8–()0.045⋅⋅
0.7µH 10.5()
----------------------------------------------------------
>
2121.0–()0.020⋅⋅
⋅
⋅
2
2
With these values of capacitors the ripple voltage can be checked. This is dominated by the
equivalent series resistance (ESR) of the capacitors. The ESR must be equal or less than
the value calculated by:
Equation 7:
V
r
ESR
where V
capacitors is given in their datasheets at the frequency they are used at as shown in the
graphs. The value is basically the same at both 300 and 400 kHz. For the 47 µF the ESR is
2 mΩ and for the 100 µF it is 1.5 mΩ. With these values we can calculate the ripple voltage
V
r
Equation 8:
by:
is the output ripple voltage and Ir is the inductor ripple current. The ESR for the
r
V
r
-----
≤
I
r
IrESR⋅=
9/38
Circuit description AN2683
for output 1:
Equation 9
0.75A 2mΩ 1.5mV=⋅
for output 2:
Equation 10
3.15A 545µΩ 1.9mV=⋅
These values conform to the specification. They are higher in a practical circuit because of
parasitic inductance and loop resistance. Good circuit board layout techniques are
essential. Additionally, because of the constant on-time control, the system regulates the
output voltage by the valley value of the ripple voltage. A minimum amount of ripple voltage
of 30 mV should be on the comp pin to accomplish this. Since the calculated ripple voltage
is much lower than this, an additional circuit called the virtual ESR network is incorporated
to provide the additional voltage. Before addressing this design, the current limit resistor
values will be established. In this design the R
implement the current limit. For output 1 with its relatively low output current the MOSFET
chosen was the STS8DNF3LL with a nominal R
dual, that is two MOSFETs are contained in the same SO-8 package realizing further circuit
board space savings. The current limit is a valley type that operates during the conduction of
the low side MOSFET. A 100 µA internal current generator connected to the C
along with a resistor establishes a voltage to which the voltage generated by the R
compared. If the R
voltage is greater, then the voltage at the C
DS(on)
of a new conduction cycle is inhibited. The value of Rc
of the lower MOSFETS is used to
DS(on)
of 18 mΩ. This particular part is a
DS(on)
pin the generation
is determined by:
sense
sense
sense
pin
DS(on)
is
Equation 11:
Rc
sense
The 18 mΩ value for R
is a nominal 25 °C number. As current is switched through the
DS(on)
device and the ambient is raised, the R
140% is used. Targeting the maximum output current (I
0.750 A the valley current value is:
10/38
R
DS on()Ivalley
----------------------------------------- -=
⋅
100µA
increases. An increase of approximately
DS(on)
) at 3.375 A and having a Ir of
outmax
AN2683 Circuit description
Equation 12
I
r
---–=
2
3.0A=–
then:
Equation 13
I
valley
3.375A
I
out max()
0.750
-------------- -
2
R
Equation 14
csense
is then:
25mΩ 3.0A⋅
----------------------------------- - 750Ω=
100µA
For output 2 the current levels are substantially higher than output 1 and two discrete
MOSFETS must be used. With a nominal input voltage of 12 volts and a one volt output the
low side MOSFET is conducting over 90 percent of the time. This means that the R
the low side MOSFET must be as low as possible. For this design the STS25NH3LL
MOSFET with a nominal 3.2 mΩ on resistance is used. Because of the high current and
duty cycle an R
the output 2 maximum current at 13.65 A the valley current is:
Equation 15
multiplier of 200% for the R
DS(on)
13.65A
3.15A
--------------- -
2
calculation is used. Again targeting
csense
12.075A=–
DS(on)
of
R
Equation 16
for output 2 then is:
csense
6.4mΩ 12.75A⋅
--------------------------------------------
100µA
11/38
773Ω=
Circuit description AN2683
With the maximum output currents established attention can be redirected at designing the
virtual ESR network. As mentioned earlier, the ripple voltage should be greater than 30 mV
and range between 30 to 50 mV. To derive the necessary minimum value of the virtual ESR
(VESR) to produce the ripple voltage the following formula is used:
Equation 17
0.05V
⎛⎞
--------------- -
⎝⎠
I
r
–=
ESR
2mΩ 64.6mΩ=–
cout
for output 1:
Equation 18
VESR
min()
0.05V
⎛⎞
--------------- -
⎝⎠
0.75A
for output 2:
Equation 19
The total ESR (ESR
output capacitor.
for output 1:
Equation 20
for output 2:
Equation 21
0.05V
⎛⎞
--------------- -
⎝⎠
3.15A
) is the sum of the virtual ESR (VESR) and the ESR (ESR
tot
0.545mΩ 15.3mΩ=–
64.6mΩ 2mΩ 66.6mΩ=+
cout
) of the
15.3mΩ 0.545mΩ 15.8mΩ=+
12/38
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