ST AN2682 Application note

AN2682

Application note

Connecting I2S audio devices to

the STR7/STR9 MCU

Introduction

This application note describes how to interface the STR7xx SPI peripheral with an audio device (Codec, ADC, DAC, filter...) using the I2S protocol via an external interface consisting of a low cost small CPLD. The design is referenced to the I2S protocol specification, so any I2S device is able to interface with the STR7xx and STR91x MCU through this bridge.

To avoid using extra hardware, an I2S solution could be implemented entirely by firmware but this would put a huge load on the CPU. The SPI to I2S bridge solution proposed in this application note is made with a very low cost hardware (about 1$) using a CPLD with less than 32 macrocells and a minimum of firmware overhead. Only one Timer (one Output Compare), 6 GPIOs and the DMA peripheral are used. The DMA available on STR75x and STR91x allows the CPU to be totally free for other tasks, and on STR71x the CPU load is

3.9% at 32 MHz MCLK frequency. The footprint is less than 5 Kbytes in Thumb mode.

The example CPLD described in this application note was built for the STR71x and STR750 microcontrollers but can be easily tailored to the STR91x or STM32.

January 2008 Rev 1 1/15

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Contents AN2682 - Application note

1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 I2S protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 CPLD design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 STR711 implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Hardware implemention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 STR711 firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2.1 CPU usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 STR750 implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 Hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 STR750 firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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AN2682 - Application note General description

1 General description

1.1 I2S protocol

I2S (IC to IC Sound) is an audio data transfer standard using a three-line bus for serial and synchronous data transmission.

Data are transmitted on the SD line (Serial Data) in Little Endian format (MSB first). Data length is not limited (usually 16/20/24/32/64 bits). Data are synchronized by the SCK (Serial Clock) rising or falling edge for the transmitter, and falling edge only for the receiver. Refer to

Figure 1.

Data represent stereo digital sound, so each sample contains two words, the right channel sample and the left channel sample. Instead of using two data channels, muxing is performed by transmitting each word in half a sampling period and that allows, by doubling the sampling rate, to transmit two words per period.

A control signal WS (Word Select) is then used to determine if the word being sent is the right or the left one. This signal also determines the beginning and the end of the data: there is no need to fix the data length. Receiver and transmitter data lengths can therefore be different, as well as the right and left data lengths.

WS is synchronized either on the rising or the falling edge of SCK and precedes the MSB by one SCK period in order to have enough time for storing and shifting operations.

As in the SPI protocol, there must be a master and a slave. The master controls and provides the SCK clock and the WS signal, while the slave only sends or receives data. The master can be the receiver or the transmitter or a third element (Controller). Refer to

Figure 2.

Figure 1. I2S Philips protocol waveforms 16/32-bit

Transmission

MSB

Reception

16-bit or 32-bit

MSB

LSB

Left channel Right channel

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General description AN2682 - Application note

Figure 2. I2S protocol signal description and configuration

SCK

Transmitter Receiver

Transmitter = Master Receiver = Master

Receiver Transmitter

Controller

SCK

Transmitter

Controller = Master

Receiver

SCK

1.2 SPI protocol

The SPI is chosen to implement this solution because its protocol is the most similar to the I2S protocol.

It uses four pins:

● Two pins (MOSI and MISO) to transmit and receive serial data

● One pin (SCLK) for data clocking (either rising or falling edge modes are available)

● One pin (nSS) to choose between master and slave modes.

When nSS is tied to Gnd, the SPI peripheral functions in Slave mode: it receives the data clock (SCLK) from the master which controls how and when data are transmitted or received.

When nSS is tied to Vcc, the SPI peripheral functions in master mode and SCLK is then an output.

MISO is the Master Input in master mode and the Slave Output in slave mode.

MOSI is the Master Output in master mode and the Slave Input in slave mode.

There are two main differences between the I2S and SPI protocols:

● The I2S clock is continuous while the SPI clock is generated only during word

transmission and is stopped afterwards.

● The data format in SPI protocol is fixed to 16 or 8 bits only, while the data in I2S can

have any length.

Due to these two differences, the SPI peripheral cannot be configured in master mode in this case. This is due to the fact that in SPI master mode, data are transmitted with a delay between the words. Besides, many difficulties would arise when other tasks are performed by the microcontroller. So the solution uses the SPI in slave mode.

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AN2682 - Application note CPLD design

2 CPLD design

The CLPD design is based on the MAX3000A 32 macrocell device shown in Figure 3.

Figure 3. MAX3000A CPLD pin description

The CPLD bridge is intended to function as the master for both SPI and I2S devices. Since the SPI peripheral is bidirectional, two I2S devices can be connected at once, as long as they have the same SCK clock (some I2S devices are also bidirectional).

When a single device is interfaced to the microcontroller, the unused direction logic can simply be ignored and has no effect on the interface. The CPLD bridge connections with the STR7/9 MCU and the I2S audio device(s) are illustrated in Figure 4.

Figure 4. SPI to I2S CPLD bridge connections

GPIO/AF

STR7/9

MCU

PWM OCMPA

GPIO

MOSI

MISO

SCLK

CLK

Start

Conf

CPLD

interface

SDo

SDi

SCK

WSo

WSi

Audio

I2S

device(s)

The Conf pin is used only in configuration mode. In communication mode, it can be used for any other application purpose.

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