ST AN2677 Application note

AN2677

Application note

Getting started with the STM8A

Introduction

This application note complements the information in the STM8A datasheets by describing the minimum hardware and software environment required to build an application around an STM8A 8-bit microcontroller device. It is divided into the following sections:

■Power supply

■Analog-to-digital converter (ADC)

■Clock management

■Reset control and development

■Debugging tool support

■STM8 software toolchain

■Setting up the STM8 development environment

This application note also contains detailed reference design schematics with descriptions of the main components. In addition, some hardware recommendations are given.

June 2009

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www.st.com

Contents	AN2677

Contents

1	Hardware requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. 6
2	Power supply		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 7
	2.1	Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
	2.2	Main operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	2.3	Power-on/power-down reset (POR/PDR) . . . . . . . . . . . . . . . . . . . . . . . . . .		8
3	Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			10
	3.1	Analog power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
	3.2	Analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
4	Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			12
	4.1	Clock management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
	4.2	Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
	4.3	External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
5	Reset control		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	5.1	Reset management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
	5.2	Hardware reset implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
		5.2.1	RC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
6	Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			17
	6.1	Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	6.2	Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	6.3	Ground and power supply (VSS, VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	6.4	Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	6.5	Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
	6.6	Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
	6.7	User options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
7	Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			19
	7.1	Components reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	7.2	Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20

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	7.3	Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 21
8	STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 22

8.1 Single wire interface module (SWIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.1.1 SWIM overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.1.2 SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.1.3 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.2 Emulator STice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

	8.2.1	STice overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	8.2.2	STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	8.2.3	In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . .	25
9	STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27

9.1 Integrated development environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.3 Firmware library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10	Setting up the STM8 development environment . . . . . . . . . . . . . . . . .		30
	10.1	Installing the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	10.2	Using the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31

10.2.1 Project editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.2.2 Online help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.3 Running the demonstration software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.3.1 Compiling the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.3.2 Selecting the correct debug instrument . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.3.3 Connecting the hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.3.4 Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.3.5 Running the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.3.6 Follow up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

11	Documentation and online support . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
12	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40

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List of tables	AN2677

List of tables

Table 1.	Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
Table 2.	Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
Table 3.	SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
Table 4.	Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40

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AN2677	List of figures

List of figures

Figure 1. Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. External capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Typical layout of VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. Analog input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. System clock distribution internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9. RC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10. Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11. LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12. Debug system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13. Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 14. Connection description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 15. STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 16. In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 17. STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 18. STM8 firmware library examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 19. STVD open example workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 20. STVD MCU edit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 21. STM8 firmware library online help manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 22. STVD: Building the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 23. STVD: Selecting the debug instrument. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 24. Connecting the debug instrument to the STM8 evaluation board. . . . . . . . . . . . . . . . . . . . 35 Figure 25. STVD: Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 26. STVD: Run the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 27. STM8 evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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Hardware requirements summary	AN2677

1 Hardware requirements summary

To build an application around an STM8A device, the application board should, at least, provide the following features:

●Power supply

●Clock management

●Reset management

●Debugging tool support: Single wire interface module (SWIM) connector

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AN2677	Power supply

2 Power supply

2.1Power supply overview

The device can be supplied through a 3.0 V to 5.5 V external source. An on-chip power management system provides the 1.8 V digital supply to the core logic, both in normal and low power modes. It is also capable of detecting voltage drops, on both main external (3.3 V/5 V) and internal (1.8 V) supplies.

The device provides:

●One pair of pads VDD/VSS (3.3 V ± 0.3 V to 5 V ± 0.5 V) dedicated to the main regulator ballast transistor supply.

●Two pairs of pads dedicated for VDD_IO/VSS_IO (3.3 V ± 0.3 V to 5 V ± 0.5 V), which are used to power only the I/O’s. On 32-pin packages, only one pair is bonded.

Note:	For VDDIO/VSSIO next to VDD/VSS, it is recommended to connect these two pairs together
	and to use only one decoupling capacitance. The purpose is to ensure good noise immunity
	by reducing the connection length between both supplies and also between VDD/VDDIO and
	the capacitor.

●One pair of pads VDDA/VSSA (3.3 V ± 0.3 V to 5 V ± 0.5 V) dedicated to analog functions. Refer to Section 3: Analog-to-digital converter (ADC) on page 10 for more details.

Figure 1. Power supply

		VDDA
		Analog
		signal		Analog functions
		VSSA
			VCAP
		VDD/VDDIO1
				Main / Low power		CPU
						RAM
	5V	VSS/VSSIO1		regulator
						Logic
	V -		VDDIO2
	3.3
		VSSIO2			IOs
				VDDIO	VSSIO
			OSCIN	VDDIO	VSSIO
					XTAL
		Star connected	OSCOUT			ai15330

Note:	The capacitors must be connected as close as possible to the device supplies (especially
	VDD in case of dedicated ground plane).

Placing a crystal/resonator on OSCIN/OSCOUT is optional. The resonator must be connected as close as possible to the OSCIN and OSCOUT pins. The loading capacitance ground must be connected as close as possible to VSS.

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Power supply	AN2677

2.2Main operating voltages

STM8A devices are processed in 0.13 µm technology. The STM8A core and I/O peripherals need different power supplies. In fact, STM8A devices have an internal regulator with a nominal target output of 1.8 V.

Stabilization for the main regulator is achieved using an external capacitor via the VCAP pin. The minimum value is 470 nF with low equivalent series resistance (ESR). Care should be taken to limit the series inductance per pad to less than 15 nH.

Figure 2. External capacitor

	ESR				C						ESL

Rleak

Where:

ESR is the equivalent series resistance

ESL is the equivalent inductance

The minimum value of C is 470 nF with an ESR between 0.05...0.2 Ohm

2.3Power-on/power-down reset (POR/PDR)

The input supply to the main and low power regulators is monitored by a power-on/power- down reset circuit. The monitoring voltage range is 0.7 V to 2.7 V.

During power-on, the POR/PDR keeps the device under reset until the supply voltages (VDD and VDDIO) reach their specified working area.

At power-on, a defined reset should be maintained below 0.7 V. The upper threshold for a reset release is defined in the electrical characteristics section of the product datasheets.

A hysteresis is implemented (POR > PDR) to ensure clean detection of voltage rise and fall.

The POR/PDR also generates a reset when the supply voltage drops below the VPOR/PDR threshold (isolated and repetitive events).

Recommendations

All pins need to be properly connected to the power supplies. These connections, including pads, tracks and vias should have the lowest possible impedance. This is typically achieved with thick track widths and preferably dedicated power supply planes in multi-layer printed circuit boards (PCBs).

In addition, each power supply pair should be decoupled with filtering ceramic capacitors (C) at 100 nF with one chemical C (1..2 µF) in parallel on the STM8A device. The ceramic capacitors should be placed as close as possible to the appropriate pins, or below the appropriate pins, on the opposite side of the PCB. Typical values are 10 nF to 100 nF, but exact values depend on the application needs. Figure 3 shows the typical layout of such a VDD/VSS pair.

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AN2677		Power supply
	Figure 3. Typical layout of VDD/VSS pair
	Via to VDD	Via to VSS

Cap.

VDD VSS

STM8

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Analog-to-digital converter (ADC)	AN2677

3 Analog-to-digital converter (ADC)

3.1Analog power

The ADC unit has an independent, analog supply reference voltage, isolated on input pin VDDA, which allows the ADC to accept a very clean voltage source. This analog voltage supply range is the same as the digital voltage supply range on pin VDD. An isolated analog supply ground connection on pin VSSA provides further ADC supply isolation. Together, the analog supply voltage and analog supply ground connection, offer a separate external

analog reference voltage input for the ADC unit on the VREF+ pin. This gives better accuracy on low voltage input as follows:

●VREF+ (input, analog reference positive): The higher/positive reference voltage for the ADC should be between [250 mV, VDDA]. For more details about VREF+ values please refer to the STM8A datasheets. This input is bonded to VDDA in devices that have no external VREF+ pin (packages with 48 pins or less).

●VREF- (input, analog reference negative): The lower/negative reference voltage for the ADC should be higher than VSSA. For more details about VREF- values please refer to the STM8A datasheets. This input is bonded to VSSA in devices that have no external VREF- pin (packages with 48 pins or less).

3.2Analog input

STM8A devices have 16 analog input channels, which are converted by the ADC one at a time, and each multiplexed with an I/O.

The analog input interface of the ADC is shown in Figure 4.

Figure 4. Analog input interface

Outside ADC

Inside ADC

VIN_EXT

VIN

SWSAMP

REXT

CEXT

CSAMP

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AN2677	Analog-to-digital converter (ADC)

Equation 1:

CVIN = CSAMP + CEXT

where:

●CVIN is the total equivalent capacitor on the path of VIN

●CSAMP is the equivalent sampling capacitance

●CEXT is the total external capacitance on the path of VIN to the macro pin. This includes parasitic routing capacitance, pad and pin capacitance and external capacitance. To ensure proper and accurate sampling the following equation must be satisfied

Equation 2:

( RSW + REXT) × ( CSAMP + CEXT) <	3		× TS
	------
	10

where:

●RSW = 30 kOhm

●REXT is the total external resistance on the path of VIN

●CSAMP = 3 pF

●TS = 0.5 µs (for 2 MHz input CLK)

Equation 2 is specific for REXT and CEXT when designing an analog input interface for the ADC.

Please refer to the STM8A datasheets and/or the corresponding family reference manual (RM0009) for more details.

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Clock management	AN2677

4 Clock management

4.1Clock management overview

STM8A devices offer a flexible way of selecting the core and peripheral clocks (ADC, memory, digital peripherals). The devices have internal and external clock source inputs and one output clock (CCO).

Figure 5. System clock distribution internal clock

OSCIN

1 to 24 MHz

CCO pin

crystal

and external

Clock unit

clock

External clock

OSCOUT

16 MHz/128 kHz

internal RC

Prescaler

WDG/AWU

Timer

lnternal clock

Clock distribution

For more details please refer to the section on clock management in the product datasheets

4.2Internal clock

The RC oscillator has an internal capacitor (C) and an internal resistor ladder (R). STM8A devices have two kinds of internal clock: A high speed internal clock (HSI) running at

16 MHz and a low speed internal clock (LSI) running at 128 kHz.

After reset, the CPU starts with the internal RC (HSI clock signal) divided by 8, i.e. 2 MHz.

4.3External clock

	STM8A devices can connect to an external crystal or an external oscillator.
Note:	When no external clock is used, OSCIN and OSCOUT can be used as general purpose
	I/Os.
	Table 1 describes the external clock connections.

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AN2677	Clock management

Table 1.

External clock

Crystal/ceramic resonators

Clock sources

Hardware configuration

STM8

OSCIN OSCOUT

(I/O available)

External source

Frequency: 32 kHz … 24 MHz

Comparator hysteresis: 0.1 * VDD

Caution: Without prescaler, a duty cycle of maximum 45/55% must be respected

STM8

OSCIN OSCOUT

Q1

CL1

CL2

Load capacitors

Frequency range: 1-24 MHz

Wake-up time: < 2 ms @ 24 MHz

Oscillation mode: Preferred fundamental

Output duty cycle: max 55/45 %

I/O’s: Standard I/O pins multiplexed with OSCIN and OSCOUT

Cload: 10 … 20 pF

Maximum crystal power: 100 µW

The values of the load capacitors CL1 and CL2 are heavily dependent on the crystal type and frequency. The user can refer to the datasheet of the crystal manufacturer to select the capacitances. For best oscillation stability CL1 and CL2 normally have the same value. Typical values are in the range from below 20 pF up to 40 pF (cload: 10 … 20 pF). The parasitic capacitance of the board layout also needs to be considered and typically adds a few pF to the component values.

Recommendations

In the PCB layout all connections should be as short as possible. Any additional signals, especially those that could interfere with the oscillator, should be locally separated from the PCB area around the oscillation circuit using suitable shielding.

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