ST AN2677 Application note

AN2677

Application note

Getting started with the STM8A

Introduction

This application note complements the information in the STM8A datasheets by describing
the minimum hardware and software environment required to build an application around an
STM8A 8-bit microcontroller device. It is divided into the following sections:

■ Power supply

■ Analog-to-digital converter (ADC)

■ Clock management

■ Reset control and development

■ Debugging tool support

■ STM8 software toolchain

■ Setting up the STM8 development environment

This application note also contains detailed reference design schematics with descriptions
of the main components. In addition, some hardware recommendations are given.

June 2009 Doc ID 14217 Rev 3 1/41

www.st.com

Contents AN2677

Contents

1 Hardware requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Main operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Power-on/power-down reset (POR/PDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Analog power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Clock management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 Reset management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2 Hardware reset implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2.1 RC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.3 Ground and power supply (V

6.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.7 User options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

, VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

SS

7 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.1 Components reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.2 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/41 Doc ID 14217 Rev 3

AN2677 Contents

7.3 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.1 Single wire interface module (SWIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.1.1 SWIM overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.1.2 SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.1.3 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.2 Emulator STice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.2.1 STice overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.2.2 STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.2.3 In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . 25

9 STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.1 Integrated development environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.2 Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9.3 Firmware library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10 Setting up the STM8 development environment . . . . . . . . . . . . . . . . . 30

10.1 Installing the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.2 Using the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10.2.1 Project editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.2.2 Online help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.3 Running the demonstration software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.3.1 Compiling the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.3.2 Selecting the correct debug instrument . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.3.3 Connecting the hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

10.3.4 Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.3.5 Running the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10.3.6 Follow up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

11 Documentation and online support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Doc ID 14217 Rev 3 3/41

List of tables AN2677

List of tables

Table 1. Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 2. Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 3. SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 4. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4/41 Doc ID 14217 Rev 3

AN2677 List of figures

List of figures

Figure 1. Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. External capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Typical layout of V

DD/VSS

Figure 4. Analog input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. System clock distribution internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8. Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9. RC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10. Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12. Debug system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13. Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14. Connection description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 15. STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 16. In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 17. STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 18. STM8 firmware library examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 19. STVD open example workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 20. STVD MCU edit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 21. STM8 firmware library online help manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 22. STVD: Building the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 23. STVD: Selecting the debug instrument. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 24. Connecting the debug instrument to the STM8 evaluation board . . . . . . . . . . . . . . . . . . . . 35

Figure 25. STVD: Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 26. STVD: Run the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 27. STM8 evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Doc ID 14217 Rev 3 5/41

Hardware requirements summary AN2677

1 Hardware requirements summary

To build an application around an STM8A device, the application board should, at least,
provide the following features:

● Power supply

● Clock management

● Reset management

● Debugging tool support: Single wire interface module (SWIM) connector

6/41 Doc ID 14217 Rev 3

AN2677 Power supply

2 Power supply

2.1 Power supply overview

The device can be supplied through a 3.0 V to 5.5 V external source. An on-chip power
management system provides the 1.8 V digital supply to the core logic, both in normal and
low power modes. It is also capable of detecting voltage drops, on both main external (3.3
V/5 V) and internal (1.8 V) supplies.

The device provides:

● One pair of pads V

DD/VSS

ballast transistor supply.

● Two pairs of pads dedicated for V

used to power only the I/O’s. On 32-pin packages, only one pair is bonded.

(3.3 V ± 0.3 V to 5 V ± 0.5 V) dedicated to the main regulator

DD_IO/VSS_IO

(3.3 V ± 0.3 V to 5 V ± 0.5 V), which are

Note: For V

and to use only one decoupling capacitance. The purpose is to ensure good noise immunity
by reducing the connection length between both supplies and also between V
the capacitor.

● One pair of pads V

Figure 1. Power supply

DDIO/VSSIO

next to VDD/VSS, it is recommended to connect these two pairs together

and

DDA/VSSA

DD/VDDIO

(3.3 V ± 0.3 V to 5 V ± 0.5 V) dedicated to analog
functions. Refer to Section 3: Analog-to-digital converter (ADC) on page 10 for more
details.

V

Analog

signal

3.3V - 5V

DDA

V

SSA

V

CAP

VDD/VDDIO1

VSS/VSSIO1

VDDIO2

V

SSIO2

OSCIN

Analog functions

Main / Low power

regulator

IOsIOs

V

V

DDIO

DDIO

V

V

SSIO

SSIO

XTAL

CPU
RAM

Logic

Star connected

OSCOUT

ai15330

Note: The capacitors must be connected as close as possible to the device supplies (especially

V

in case of dedicated ground plane).

DD

Placing a crystal/resonator on OSCIN/OSCOUT is optional. The resonator must be
connected as close as possible to the OSCIN and OSCOUT pins. The loading capacitance
ground must be connected as close as possible to V

Doc ID 14217 Rev 3 7/41

SS

.

Power supply AN2677

2.2 Main operating voltages

STM8A devices are processed in 0.13 µm technology. The STM8A core and I/O peripherals
need different power supplies. In fact, STM8A devices have an internal regulator with a
nominal target output of 1.8 V.

Stabilization for the main regulator is achieved using an external capacitor via the V
The minimum value is 470 nF with low equivalent series resistance (ESR). Care should be
taken to limit the series inductance per pad to less than 15 nH.

Figure 2. External capacitor

ESR ESL

Where:

ESR is the equivalent series resistance

ESL is the equivalent inductance

The minimum value of C is 470 nF

with an ESR between 0.05...0.2 Ohm

C

Rleak

2.3 Power-on/power-down reset (POR/PDR)

The input supply to the main and low power regulators is monitored by a power-on/power­down reset circuit. The monitoring voltage range is 0.7 V to 2.7 V.

During power-on, the POR/PDR keeps the device under reset until the supply voltages (V
and V

At power-on, a defined reset should be maintained below 0.7 V. The upper threshold for a
reset release is defined in the electrical characteristics section of the product datasheets.

) reach their specified working area.

DDIO

CAP

pin.

DD

A hysteresis is implemented (POR > PDR) to ensure clean detection of voltage rise and fall.

The POR/PDR also generates a reset when the supply voltage drops below the V
threshold (isolated and repetitive events).

Recommendations

All pins need to be properly connected to the power supplies. These connections, including
pads, tracks and vias should have the lowest possible impedance. This is typically achieved
with thick track widths and preferably dedicated power supply planes in multi-layer printed
circuit boards (PCBs).

In addition, each power supply pair should be decoupled with filtering ceramic capacitors (C)
at 100 nF with one chemical C (1..2 µF) in parallel on the STM8A device. The ceramic
capacitors should be placed as close as possible to the appropriate pins, or below the
appropriate pins, on the opposite side of the PCB. Typical values are 10 nF to 100 nF, but

8/41 Doc ID 14217 Rev 3

exact values depend on the application needs. Figure 3 shows the typical layout of such a
V

DD/VSS

pair.

POR/PDR

AN2677 Power supply

Figure 3. Typical layout of VDD/VSS pair

STM8

Via to V

DD

Cap.

VDDV

Via to V

SS

SS

Doc ID 14217 Rev 3 9/41

Analog-to-digital converter (ADC) AN2677

3 Analog-to-digital converter (ADC)

3.1 Analog power

The ADC unit has an independent, analog supply reference voltage, isolated on input pin
V

, which allows the ADC to accept a very clean voltage source. This analog voltage

DDA

supply range is the same as the digital voltage supply range on pin V
supply ground connection on pin V

provides further ADC supply isolation. Together, the

SSA

analog supply voltage and analog supply ground connection, offer a separate external
analog reference voltage input for the ADC unit on the V

pin. This gives better accuracy

REF+

on low voltage input as follows:

● V

● V

(input, analog reference positive): The higher/positive reference voltage for the

REF+

ADC should be between [250 mV, V
refer to the STM8A datasheets. This input is bonded to V
external V

(input, analog reference negative): The lower/negative reference voltage for the

REF-

ADC should be higher than V

pin (packages with 48 pins or less).

REF+

SSA

the STM8A datasheets. This input is bonded to V
V

pin (packages with 48 pins or less).

REF-

]. For more details about V

DDA

DDA

. For more details about V

in devices that have no external

SSA

REF-

. An isolated analog

DD

values please

REF+

in devices that have no

values please refer to

3.2 Analog input

STM8A devices have 16 analog input channels, which are converted by the ADC one at a
time, and each multiplexed with an I/O.

The analog input interface of the ADC is shown in Figure 4.

Figure 4. Analog input interface

V

IN_EXT

Outside ADC Inside ADC

R

EXT

V

C

EXT

SW

IN

SAMP

C

SAMP

10/41 Doc ID 14217 Rev 3

AN2677 Analog-to-digital converter (ADC)

Equation 1:

C

VIN

C

+=

SAMPCEXT

where:

● C

●

● C

is the total equivalent capacitor on the path of V

VIN

C

is the equivalent sampling capacitance

SAMP

is the total external capacitance on the path of VIN to the macro pin. This includes

EXT

IN

parasitic routing capacitance, pad and pin capacitance and external capacitance. To
ensure proper and accurate sampling the following equation must be satisfied

Equation 2:

3

⎛⎞

------

+()C

R

SWREXT

+()×

SAMPCEXT

⎝⎠

10

T

×<

S

where:

● R

● R

●

● T

Equation 2 is specific for R

= 30 kOhm

SW

is the total external resistance on the path of V

EXT

C

= 3 pF

SAMP

= 0.5 µs (for 2 MHz input CLK)

S

EXT

and C

when designing an analog input interface for the

EXT

IN

ADC.

Please refer to the STM8A datasheets and/or the corresponding family reference manual
(RM0009) for more details.

Doc ID 14217 Rev 3 11/41

Clock management AN2677

4 Clock management

4.1 Clock management overview

STM8A devices offer a flexible way of selecting the core and peripheral clocks (ADC,
memory, digital peripherals). The devices have internal and external clock source inputs and
one output clock (CCO).

Figure 5. System clock distribution internal clock

OSC

IN

1 to 24 MHz

crystal

and external

clock

Clock unit

CCO pin

External clock

16 MHz/128 kHz

internal RC

lnternal clock

For more details please refer to the section on clock management in the product datasheets

OSC

OUT

Prescaler

WDG/AWU

Timer

Clock distribution

4.2 Internal clock

The RC oscillator has an internal capacitor (C) and an internal resistor ladder (R). STM8A
devices have two kinds of internal clock: A high speed internal clock (HSI) running at
16 MHz and a low speed internal clock (LSI) running at 128 kHz.

After reset, the CPU starts with the internal RC (HSI clock signal) divided by 8, i.e. 2 MHz.

4.3 External clock

STM8A devices can connect to an external crystal or an external oscillator.

Note: When no external clock is used, OSCIN and OSCOUT can be used as general purpose

I/Os.

Ta bl e 1 describes the external clock connections.

12/41 Doc ID 14217 Rev 3

AN2677 Clock management

Table 1. Clock sources

Hardware configuration

STM8

OSC

IN

External source

External clock

Frequency: 32 kHz … 24 MHz

Comparator hysteresis: 0.1 * V

Caution: Without prescaler, a duty cycle of maximum 45/55% must be respected

OSC

IN

(I/O available)

STM8

Q1

OSC

OSC

OUT

DD

OUT

C

L1

Load capacitors

C

L2

Frequency range: 1-24 MHz

Crystal/ceramic resonators

Wake-up time: < 2 ms @ 24 MHz

Oscillation mode: Preferred fundamental

Output duty cycle: max 55/45 %

I/O’s: Standard I/O pins multiplexed with OSC

and OSC

IN

OUT

Cload: 10 … 20 pF

Maximum crystal power: 100 µW

The values of the load capacitors C

and CL2 are heavily dependent on the crystal type and

L1

frequency. The user can refer to the datasheet of the crystal manufacturer to select the
capacitances. For best oscillation stability C

and CL2 normally have the same value.

L1

Typical values are in the range from below 20 pF up to 40 pF (cload: 10 … 20 pF). The
parasitic capacitance of the board layout also needs to be considered and typically adds a
few pF to the component values.

Recommendations

In the PCB layout all connections should be as short as possible. Any additional signals,
especially those that could interfere with the oscillator, should be locally separated from the
PCB area around the oscillation circuit using suitable shielding.

Doc ID 14217 Rev 3 13/41

Reset control AN2677

5 Reset control

5.1 Reset management overview

The reset cell is a dedicated 5 V bidirectional I/O. Its output buffer driving capability is fixed
to Iol
buffer is reduced to the n-channel MOSFET (NMOS). If a 40 k pull-up is accepted, this cell
does not include an output buffer of 5 V capability. The receiver includes a glitch filter,
whereas the output buffer includes a 20 µs delay.

There are many reset sources, including:

● External reset through the NRST pin

● Power-on reset (POR) and brown-out reset (BOR): during power-on, the POR keeps

● Independent watchdog reset (IWDG)

● Window watchdog reset (WWDG)

● Software reset: the application software can trigger reset

● SWIM reset: an external device connected to the SWIM interface can request the

● Illegal opcode reset: if a code to be executed does not correspond to any opcode or

● Electromagnetic susceptibility (EMS) reset: generated if critical registers are corrupted

= 2 mA @ 0.4 V in the 3 V to 5.5 V range which includes a 40 k pull-up. Output

MIN

the device under reset until the supply voltage (V

DD

and V

) reach the voltage level

DDIO

at which the BOR starts to function.

SWIM block to generate a microcontroller reset

prebyte value, a reset is generated

or badly loaded

Figure 6. Reset management

STM8

VDD_IO

R

PU

NRST

External reset

Pulse generator

(min 20 µs)

Delay

Filter

A

Simplified functional I/O reset schematic

System reset

External reset
Illegal op code reset
IWDG/WWDG/software reset
SWIM reset
EMS reset
POR/BOR reset

14/41 Doc ID 14217 Rev 3

AN2677 Reset control

Output characteristics

● A valid pulse on the pin is guaranteed with a >= 20 ns pulse duration on the internal

output buffer.

● After a valid pulse is recognized, a pulse on the pin of at least 20 µs is guaranteed

starting from the falling edge of A.

Figure 7. Output characteristics

>= 20 ns

A

20 µs pulse stretch m

Reset requested

Pad

Input characteristics

● All pulses with a duration less than 75 ns are filtered

● All train/burst spikes with a ratio of 1/10 must be filtered. This means that a negative

spike of up to 75 ns is always filtered, when a 7.5 ns interval between spikes occurs
(ratio 1/10).

● All pulses with duration more than 500 ns are recognized as valid pulses

● After a valid pulse is recognized, an internal pulse of at least 30 ns is guaranteed

Figure 8. Input characteristics

>7.5 ns >7.5 ns

450 ns

<75 ns <75 ns <75 ns

>30 ns

Reset requestedNegative train of glitch filtered

Pad

System reset

5.2 Hardware reset implantation

The device functions correctly without an external reset circuitry. However, if a reset circuit is
needed, there are several reset implementation schemes to choose from, such as power
supply behavior, based on the specific parameters of the application. Whatever the solution
chosen, the idea is to keep the RESET
safe operating voltage. Therefore, the external circuit should be designed in such a manner
that there is enough delay to keep the RESET

pin at a low logic level until the supply has reached a

pin below the VIL value.

Doc ID 14217 Rev 3 15/41

Reset control AN2677

5.2.1 RC circuit

The RC circuit concept is the simplest and most cost-effective external reset solution, where
the supply waveform is monotonous and the maximum rise time is known. The principle is to
let the RESET
shown in Figure 9.

The basic solution is to use an RC delay determined by the rise rate of the supply itself. The
component values must be chosen to create enough delay to keep the RESET
V

specification until VCC reaches a safe operating voltage. Normally, a delay (time

IL

constant) corresponding to at least 30 % of the total rise time is advised.

Figure 9. RC circuit

pin rise with the microcontroller supply voltage after a delay. The circuit is

pin below the

STM8

NRSTIN

C1 100nFPush button

VDD_IO

R

PU

The RC circuit scheme requires a certain delay between a power-down and the next power­up, because the delay generator has to be reinitialized. In practice, a pull-down capacitor
between RESET

and VSS needs to be discharged. In the simplest RC circuit, the resistor is

the internal pull-up from the reset pin of the microcontroller.

16/41 Doc ID 14217 Rev 3

AN2677 Recommendations

6 Recommendations

6.1 Printed circuit board

For technical reasons, it is best to use a multi-layer PCB with a separate layer dedicated to
the V
a good shielding effect. For many applications, economical requirements prohibit the use of
this type of board. In this case, the most important feature is to ensure a good structure for
the V

6.2 Component position

A preliminary layout of the PCB must separate the different circuits according to their
electromagnetic interference (EMI) contribution in order to reduce cross-coupling on the
PCB, i.e. noisy, high-current circuits, low voltage circuits, and digital components.

6.3 Ground and power supply (VSS, VDD)

The VSS should be distributed individually to every block (noisy, low level sensitive, and
digital) with a single point for gathering all ground returns. Loops must be avoided or have a
minimum surface. The power supply should be implemented close to the ground line to
minimize the surface of the supply loop. This is due to the fact that the supply loop acts as
an antenna, and is therefore the main emitter and receiver of EMI. All component-free
surfaces of the PCB must be filled with additional grounding to create a kind of shield
(especially when using single-layer PCBs).

and another layer to the VDD supply, which results in a good decoupling, as well as

SS

and power supply.

SS

6.4 Decoupling

The standard decoupler for the external power is a 100 µF pool capacitor. Supplementary
100 nF capacitors must be placed as close as possible to the V
order to reduce the area of the current loop.

As a general rule, decoupling all sensitive or noisy signals improves electromagnetic com­patibility (EMC) performances.

There are 2 types of decouplers:

● Capacitors close to components. Inductive characteristics, which apply to all capacitors

● Inductors. Although often ignored, ferrite beads, for example, are excellent inductors

SS/VDD

pins of the micro in

beyond a certain frequency, must be taken into account. If possible, parallel capacitors
with decreasing values (0.1, 0.01,... µF) should be used.

due to their good dissipation of EMI energy and there is no loss of DC voltage (which is
not the case when simple resistors are used).

Doc ID 14217 Rev 3 17/41

Recommendations AN2677

6.5 Other signals

When designing an application, the following areas should be closely studied to improve
EMC performances:

● Noisy signals (clock)

● Sensitive signals (high impedance)

In addition to:

● Signals for which a temporary disturbance permanently affects operation of the

application, for example, interrupts and handshaking strobe signals (but not LED
commands).

A surrounding V

trace for such signals increases EMC performances, as does a shorter

SS

length or absence of noisy and sensitive traces (crosstalk effect).

For digital signals, the best possible electrical margin must be reached for the 2 logical
states. Slow Schmitt triggers are recommended for eliminating parasitic states.

6.6 Unused I/Os and features

Microcontrollers are designed for a variety of applications, where often a particular
application does not use 100 % of the microcontroller resources.

To increase EMC performance, unused clocks, counters, or I/Os, should not be left free, for
example, I/Os should be set to ‘0’ or ‘1’ (pull-up or pull-down to the unused I/O pins) and
unused functions should be ‘frozen’ or disabled.

Alternatively, unused I/Os can be programmed as push-pull ‘low’ in order to keep them at a
defined level but not to use external components.

6.7 User options

STM8A devices have user option features that can be used for remapping or
enabling/disabling an automatic reset or low speed watchdog. For more details please refer
to the product datasheets.

18/41 Doc ID 14217 Rev 3

AN2677 Reference design

7 Reference design

7.1 Components reference

Table 2. Component list

ID Component name Reference Quantity Comments

Refer to the ‘Pinouts and pin description’

1 Microcontroller STM8A 1

2 Push button 1 1

3 Resistor 10 kOhm 1

4 Capacitor 100 nF 5 Ceramic capacitor (decoupling capacitor)

5 Capacitor 1 µF 1 Decoupling capacitor

6 Capacitor 470 nF 1 Main regulator stabilization

7 Capacitor 20..40 pF 2 Used for crystal

8 Crystal 1..24 MHz 1

and ‘Package characteristics’ sections of
the STM8A datasheets, to choose the
right package

9 SWIM connector 4 pins 1

Doc ID 14217 Rev 3 19/41

Reference design AN2677

1

7.2 Schematics

Figure 10. Reference design

U1 STM8 Package L QF P 80- pin

PA0

B1

3

2

100 nF

1

C1

4

R eset

VDD 2)

C5

100 nFC6100 nFC7100 nF

Decoupling Capacitor

C2

20 pF

C3

20 pF

Clock(H SE )

CN1

4
3
2

1

SW IM connector

Debug

C9

C8

1 µF

100 nF

24 MHz

VDD

X1

470 nF

2)

VDD 2)

VCAP

C4

PA1
PA2

1

NRST

2

PA1/OSCI N

3

PA2/OSCOUT

9

PA3/TI M2_CC3

10

PA4/USART_RX

11

PA5/USART_TX

12

PA6/USART_CK

6

VCAP

34

PB0/AI N0

33

PB1/AI N1

32

PB2/AI N2

31

PB3/AI N3

30

PB4/AI N4

29

PB5/AI N5

28

PB6/AI N6

27

PB7/AI N7

42

PC0/ADC_ETR

43

PC1/TI M1_CC1

44

PC2/TI M1_CC2

45

PC3/TI M1_CC3

46

PC4/TI M1_CC4

47

PC5/SP I_SCK

50

PC6/SP I_MOSI

51

PC7/SP I_MI SO

73

PD0/TI M3_CC2

74

PD1/SWI M

75

PD2/TI M3_CC1

76

PD3/TI M2_CC2

77

PD4/TI M2_CC1_BEEP

78

PD5/LI NUART_TX

79

PD6/LI NUART_RX

80

PD7/TL I

8

VDDI O_1

49

VDDI O_2

7

VDD

23

VDDA

5

VSS

24

VSSA

4

VSSI O_1

48

VSSI O_2

PE3/TI M1_BK I N

PH5/TI M1_NCC3
PH6/TI M1_NCC2
PH7/TI M1_NCC1

MCU

PE0/MCO

PE1/I 2C_SCL

PE2/I 2C_SDA

PE5/SPI _NSS

PE6/AI N8
PE7/AI N9

PF0/AIN10
PF1/VREF -

PF2/VREF +

PF3/AIN11
PF4/AIN12
PF5/AIN13
PF6/AIN14
PF7/AIN15

PG0/CAN_TX

PG1/CAN_RX

PH4/TI M1_ETR

PE4

PG2
PG3
PG4
PG5
PG6
PG7

PH0
PH1
PH2
PH3

70
69
68
67
66
41
40
39

26
25

PF1

22

PF2
21
20
19
18
17

52
53
54
55
56
63
64
65

13
14
15
16
35
36
37
38

57

PI0

58

PI1

59

PI2

60

PI3

61

PI4

62

PI5

71

PI6

72

PI7

ai15318

R2 0

0R1 0

)

VDD 2)

1. When V
25 respectively, R1 and R2 should be removed if pins 22 and 25 are required as GPIO. When V
V

REF-

V

SSA

must be within the allowed supply voltage range of the STM8A microcontroller.

2. V

DD

REF+

and V

signals are available (64-pin packages and above) and are mapped to pins 22 and

REF-

signals are not available (48-pin packages and below), they are internally connected to V

.

20/41 Doc ID 14217 Rev 3

REF+

DDA

and

and

AN2677 Reference design

7.3 Pinouts

STM8A devices have several package types, including the LQFP 80-pin pinout shown in

Figure 11. Please refer to the STM8A datasheets for more details.

Figure 11. LQFP 80-pin pinout

C_SDA

C_SCL

2

2

NRST

OSCIN/PA1

OSCOUT/PA2

V

SSIO_1

V

VCAP

V

V

DDIO_1

TIM2_CC3/PA3

USART_RX/PA4

USART_TX/PA5

USART_CK/PA6

(HS) PH0

(HS) PH1

PH2

PH3
AIN15/PF7
AIN14/PF6
AIN13/PF5
AIN12/PF4

SS

DD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PD7/TLI

PD6/LINUART_RX

PD5/LINUART_TX

78

79

80

212224

23

DDA

REF+

V

V

AIN11/PF3

PD4 (HS)/TIM2_CC1/BEEP

PD2 (HS)/TIM3_CC1

PD1 (HS)/SWIM

PD3 (HS)/TIM2_CC2

75

76

77

2526282730

SSA

REF-

V

V

AIN7/PB7

AIN10/PF0

PD0 (HS)/TIM3_CC2

AIN6/PB6

PI7

727473

29

AIN5/PB5

PI6

71

AIN4/PB4

PE0/CLK_CCO

PE1/I

69

70

32

31

AIN3/PB3

AIN2/PB2

PE2/I

33

AIN1/PB1

PE3/TIM1_BKIN

67

34

AIN0/PB0

PE4

PG7

666865

36

35

TIM1_ETR/PH4

TIM1_NCC3/PH5

PG6

PG5

PI5

62

63

64

38

37

39

AIN8/PE7

TIM1_NCC2/PH6

TIM1_NCC1/PH7

PI4

61

60

PI3

59

PI2

58

PI1

57

PI0

56

PG4

55

PG3

54

PG2

53

PG1/CAN_RX

52

PG0/CAN_TX

51

PC7/SPI_MISO

50

PC6/SPI_MOSI

49

V

DDIO_2

48

V

SSIO_2

47

PC5/SPI_SCK

46

PC4 (HS)/TIM1_CC4

45

PC3 (HS)/TIM1_CC3

44

PC2 (HS)/TIM1_CC2

43

PC1 (HS)/TIM1_CC1

42

PC0/ADC_ETR

41

PE5/SPI_NSS

40

AIN9/PE6

(HS) High sink capability

Doc ID 14217 Rev 3 21/41

STM8 development tools AN2677

8 STM8 development tools

Development tools for STM8A microcontrollers include the STice emulation system
supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger.

8.1 Single wire interface module (SWIM)

8.1.1 SWIM overview

In-circuit debugging mode or in-circuit programming mode are managed through a single
wire hardware interface based on an open-drain line, featuring ultra fast memory
programming. Coupled with an in-circuit debugging module, the SWIM also offers a non­intrusive read/write to RAM and peripherals. This makes the in-circuit debugger extremely
powerful and close in performance to a full-featured emulator.

The SWIM pin can be used as a standard I/O (with 8 mA capability) which has some
restrictions if the user wants to use it for debugging. The most secure way to use it is to
provide a strap option on the PCB. Please refer to the STM8 SWIM communication protocol
and debug module user manual (UM0470) for more SWIM protocol details.

Figure 12. Debug system block diagram

8.1.2 SWIM connector pins

The SWIM connector pins consist of 4 pins as described in Ta bl e 3 .

Table 3. SWIM connector pins

100

kHz Osc

Peripheral

RAM

NVM

DBG

SWIM entry

Comm

layer

Internal RC

CMD

decode

DM

STM8

core

Pin number Pin name

Pin 1 V

DD

Pin 2 SWIM pin

Pin 3 V

SS

Pin 4 Reset

22/41 Doc ID 14217 Rev 3

AN2677 STM8 development tools

8.1.3 Hardware connection

Figure 13. Hardware connection

AD/ICC SWIM adapter

V

DD

SWIM connector

1

2

3

4

SWIM cable

Application board

V

DD

1

2
3

4

STM8

Caution: It is recommended to place the SWIM header as close as possible to the STM8A device, as

this minimizes any possible signal degradation caused by long PCB tracks.

8.2 Emulator STice

8.2.1 STice overview

The STice is a modular, high-end emulator system which connects to the PC via a USB
interface, and to the application board in place of the target microcontroller.

It is supported by the free STM8 toolset: IDE ST visual develop (STVD) programmer, ST
visual programmer (STVP) and STM8 assembler. Please refer to the STice emulator for
STM8 for more details.

Figure 14. Connection description

Emulation system

Connection flex

Connection adapter

Adapter socket

Doc ID 14217 Rev 3 23/41

STM8 development tools AN2677

Emulation system: STice

● Emulator box

● Cables for USB, power supply, trigger, analyzer input

Connection flex

● 60-pin or 120-pin cable for connection to the application board

Connection adapter

● Links the connection flex to the footprint of the STM8A microcontroller

Adapter socket

● Package-specific socket for connection adapter and STM8A microcontroller

8.2.2 STice in emulation configuration

In emulation configuration, the STice is connected to the PC via a USB interface and to the
application board in place of the target microcontroller being used.

● Connection flex: Flexible cable (60-pin or 120-pin depending on the target

microcontroller) that relays signals from the STice to the application board

● Connection adapter: Links the connection flex to the footprint of the target

microcontroller on the users application board.

● Adapter socket: Socket that solders to the application board in place of the

microcontroller and receives the connection adapter.

The above accessories are not included with the STice system. To determine exactly what

is required for any supported microcontroller, refer to the online product selector on

www.st.com.

24/41 Doc ID 14217 Rev 3

AN2677 STM8 development tools

Figure 15. STice in emulation configuration

Free ST/STM8 toolset: STVD and STVP running on your PCdrive STice

STice-SYSxxx: Includes all emulation resources, MEB, TEB,

CF/FPxxx: Connection flex to connect to application board

AD/xxxx: Connection

adapter to link connection

cable to microcontroller

8.2.3 In-circuit programming and debugging

In the in-circuit debugging/programming configuration, STice allows the application to be
programmed in the microcontroller and for the application to be debugged while it runs on
the microcontroller on the application board. STice supports the SWIM protocol, making it
possible to in-circuit program and debug the microcontroller using only one general purpose
I/O.

and PEB

AS/xxxx: Adapter socket on application

board to plug in emulator in place of

microcontroller

In both the emulation and the in-circuit programming/debugging configuration, STice is
driven by the ST visual develop (STVD) or ST visual programmer (STVP) integrated
development environment running on the host PC. This provides total control of advanced
application building, debugging and programming features from a single easy-to-use
interface.

Doc ID 14217 Rev 3 25/41

STM8 development tools AN2677

Figure 16. In-circuit programming and debugging

ICD/ICP flat cable connects STice to microcontroller via

ICD/ICP connector on application board

SWIM connector linked to microcontroller

(SWIM protocol for STM8, or ICC protocol

for ST)

ST microcontroller on

application board

26/41 Doc ID 14217 Rev 3

AN2677 STM8 software toolchain

9 STM8 software toolchain

To write, compile and run the first software on an STM8A device, the following components
of the software toolchain are required (see Figure 17):

● Integrated development environment

● Compiler

● Firmware library (optional, used to ease the start-up)

Figure 17. STM8 software toolchain

9.1 Integrated development environment

The integrated development environment ST visual develop (STVD) provides an easy-to­use, efficient environment for start-to-finish control of application development, from building
and debugging the application code to programming the microcontroller. STVD is delivered
as part of the free ST toolset, which also includes the ST visual programmer (STVP)
programming interface and the ST assembler linker.

Doc ID 14217 Rev 3 27/41

STM8 software toolchain AN2677

To build applications, STVD provides seamless integration of C and assembly tool chains for
ST including the Cosmic and Raisonance C compilers and the ST assembler linker. When
debugging, STVD provides an integrated simulator (software) and supports a complete
range of hardware tools including the low-cost RLink in-circuit debugger/programmer and
the high-end STice emulator.

To program applications to an STM8A, the STVD also provides an interface for reading from
the microcontroller memories, writing to them and verifying them. This interface is based on
the ST visual programmer (STVP), and supports all the target devices and programming
tools supported by STVP.

The free ST toolset for STM8 is available from STMicroelectronics homepage (see

www.st.com).

9.2 Compiler

STM8A devices can be programmed by a free assembler toolchain which is included in the
ST toolset.

As the core is designed for optimized high-level-language support, use of a C compiler is
recommended!

C compilers for STM8 are offered by the third party companies Cosmic and Raisonance.

A free version of the C compiler with up to 16 Kbytes of generated code is available at:
www.cosmic-software.com and www.raisonance.com.

28/41 Doc ID 14217 Rev 3

AN2677 STM8 software toolchain

9.3 Firmware library

The STM8 firmware library is a complete set of source code examples for each STM8
peripheral. It is written in strict ANSI-C and it is fully MISRA C 2004 compliant (see

Figure 18).

All examples are delivered with workspace and project definition files for STVD and Cosmic
C compiler which enables the user to load and compile them easily into the development
environment.

The examples run on the STMicroelectronics STM8 evaluation board and can be tailored
easily to other types of hardware.

For additional information on the STM8 firmware library, please contact STMicroelectronics.

Figure 18. STM8 firmware library examples

Doc ID 14217 Rev 3 29/41

Setting up the STM8 development environment AN2677

10 Setting up the STM8 development environment

The STM8 development environment setup looks different depending on the supplier of the
software (SW) and hardware (HW) tools.

Typical setups are described below for the following SW and HW tools:

● STM8 C compiler from Cosmic

● ST toolset and STM8 firmware library from STMicroelectronics

● HW debug interface "Rlink" from Raisonance

● STM8 evaluation board from STMicroelectronics

10.1 Installing the tools

All software tools are delivered with a setup wizard which guides the user through the
installation process. It is recommended to install the tools in the following order:

1. C compiler

2. ST toolset

3. STM8 firmware library

The Rlink does not need any dedicated software installation in the STM8 development
environment because the necessary drivers are delivered with the ST toolset.

Note: These R-link drivers must be launched separately as follows:

Start/Programs/STtoolset/Setup/Install Rlink driver.

30/41 Doc ID 14217 Rev 3

AN2677 Setting up the STM8 development environment

10.2 Using the tools

Once the tools installation is complete, the ST visual develop (STVD) integrated
development environment can be launched.

The user then has the choice to generate either a new workspace with a new project or to
open an existing workspace. If using the STVD for the first time, it is recommended to open
an existing project from the STM8 firmware library.

The STM8 firmware library includes several examples for each peripheral plus one
workspace containing a project which is already configured for the dot-matrix-display of the
STM8 evaluation board. It is located in the firmware subdirectory \Project\Cosmic (see

Figure 19).

Figure 19. STVD open example workspace

Doc ID 14217 Rev 3 31/41

Setting up the STM8 development environment AN2677

10.2.1 Project editing

All project source files are visible and can be edited (see Figure 20).

Figure 20. STVD MCU edit mode

10.2.2 Online help

An online help manual is available inside the firmware installation directory (see Figure 21)
to help the user understand the structure of the STM8 firmware library.

Figure 21. STM8 firmware library online help manual

32/41 Doc ID 14217 Rev 3

AN2677 Setting up the STM8 development environment

10.3 Running the demonstration software

To run the demonstration software on the STM8 evaluation board, the project has to be
compiled and the correct HW tool must be selected before the debug session can be
started.

10.3.1 Compiling the project

The project can be compiled using the ‘Build’ function in the ‘Build’ menu (see Figure 22).

Figure 22. STVD: Building the project

Doc ID 14217 Rev 3 33/41

Setting up the STM8 development environment AN2677

10.3.2 Selecting the correct debug instrument

In the example below, the Rlink tool is used for communicating via the SWIM interface with
the on-board debug module of the STM8.

The Rlink tool can be selected from the ‘Debug Instrument Selection’ list in the ‘Debug
Instrument Settings’ dialog (see Figure 23).

Figure 23. STVD: Selecting the debug instrument

34/41 Doc ID 14217 Rev 3

AN2677 Setting up the STM8 development environment

10.3.3 Connecting the hardware

The Rlink tool can be connected to the PC by a standard USB connection. It is also powered
by the USB interface.

On the controller side the connection to the STM8 evaluation board is made by the SWIM
interface cable. The STM8 evaluation board is powered by an external 5 V supply (see

Figure 24).

Figure 24. Connecting the debug instrument to the STM8 evaluation board

Rlink USB connection

Rlink adapter
for STM8

SWIM interface connection

5 V power supply

Caution: On the Rlink ICC/SWIM adapter board, the “SWIM” jumper must be set.

If there is no pull-up on the application SWIM line, the “ADAPT” jumper is also set.
In any case, “PW-5V” and “12 MHz” jumpers must not be set.

Doc ID 14217 Rev 3 35/41

Setting up the STM8 development environment AN2677

10.3.4 Starting the debug session

Debug mode can be entered by the command ‘Debug Start Debugging’ (see Figure 25).

Figure 25. STVD: Starting the debug session

36/41 Doc ID 14217 Rev 3

AN2677 Setting up the STM8 development environment

10.3.5 Running the software

After entering debug mode, the software can be started by the run command in the menu
‘Debug Run’ (see Figure 26).

Figure 26. STVD: Run the software

Doc ID 14217 Rev 3 37/41

Setting up the STM8 development environment AN2677

The LCD display on the STM8 evaluation board indicates a successful debug session (see

Figure 27).

Figure 27. STM8 evaluation board

10.3.6 Follow up

Step by step, additional peripherals of STM8A devices can be run, following on from the
initial debug session described above.

38/41 Doc ID 14217 Rev 3

Many features of STM8A devices are supported by dedicated hardware on the STM8
evaluation board. The necessary software drivers (LIN driver, buttons, memory cards,
buzzer, etc) are delivered in the STM8 firmware library.

AN2677 Documentation and online support

11 Documentation and online support

Documentation resources related to tool usage includes:

Application

● STM8A datasheets

● STM8 Flash programming manual (PM0047)

● STM8A microcontroller family reference manual (RM0009)

● STM8 CPU programming manual (PM0044)

Tools

● STM8 firmware library and release note (detailed descriptions of the library are

included as help files)

● STice advanced emulation system for ST microcontrollers data briefing

● STice user manual

● Cosmic C compiler user manual

● STM8/128-EVAL evaluation board user manual (UM0482)

● ST visual develop tutorial (included as help files in the ST-toolchain)

● ST visual develop (STVD) user manual

● STM8 SWIM communication protocol and debug module user manual (UM0470)

The microcontroller discussion forum on www.st.com can be used by developers to
exchange ideas. It is the best place to find different application ideas. In addition, the
website has a knowledge base of FAQs for microcontrollers, which provide answers to many
queries and solutions to many problems.

Doc ID 14217 Rev 3 39/41

Revision history AN2677

12 Revision history

Table 4. Document revision history

Date Revision Changes

03-Mar-2008 1 Initial release

Made small textual changes through the document to improve
readability and clarity.

Section 2.1: Power supply overview on page 7: Added notes

regarding V

DDIO1

, V
OSCIN/OSCOUT crystal/resonator.
Modified Figure 2: External capacitor on page 8 with regard to VDD,

, V

V

SS

DDIO1

, V

DDIO2

Section 2.3: Power-on/power-down reset (POR/PDR) on page 8:

Modified reset voltage and referred reader to the product datasheets
for the reset release voltage.

Figure 5: System clock distribution internal clock on page 12:

Replaced ‘XTAL’ with ‘crystal’.

Section 4.2: Internal clock on page 12: Removed text regarding

frequency of the clock output.

Section 4.3: External clock on page 12: Added a note about the use

of OSCIN and OSCOUT as GPIOs, added a reference to the crystal
manufacturer’s datasheet, and removed a caution concerning the
enabling of an external clock input.

Figure 6: Reset management on page 14: Removed connection

between system reset and OR port. Added external reset to OR port.

Input characteristics on page 15: Changed the valid pulse duration

08-Aug-2008 2

from 450 ns to 500 ns.

Section 5.2: Hardware reset implantation on page 15: Clarified text

regarding the reset circuit.
Modified Figure 10: Reference design on page 20 by replacing +5 V
with V

. Modified footnote 1 regarding pins 22 and 25. Added

DD

footnote 2 concerning the supply voltage range of V

Section 8.2.3: In-circuit programming and debugging on page 25:

Added that the STice is also driven by the STVP.

Figure 16: In-circuit programming and debugging on page 26:

Simplified note 2.

Section 9: STM8 software toolchain on page 27: Clarified that the

firmware library is optional (not required) for writing, compiling and
running the first software of the STM8A.

Section 10.1: Installing the tools on page 30: Added a note regarding

R-link drivers.
Removed section on Project setting adjustment and figures on STVD

project settings and STVD MCU selection.
Section 10.3.3: Connecting the hardware on page 35: Added a

caution concerning jumpers.

Section 10.3.6: Follow up on page 38: Removed CAN driver from list

of software drivers as it is not delivered by the firmware library.

Section 11: Documentation and online support on page 39: Updated

reference material.

Modified Section 2.2: Main operating voltages and Figure 2:

09-Jun-2009 3

changed the sentence from “typical value is 470 nF” to
“minimum value is 470 nF “.

DDIO2

, V

ssIO1

, V

, V

SSIO1

, V

SSIO2

, and analog functions.

ssIO2

, the capacitors, and the

.

DD

40/41 Doc ID 14217 Rev 3

AN2677

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