ST AN2674 Application note
AN2674
Application note
PCB layout guidelines for SPEAr3xx
Introduction
SPEAr3xx is a 15 x15 mm LFBGA289 device family with 0.8 mm ball pitch. The SPEAr3xx
family includes SPEAr300, SPEAr310 and SPEAr320.
SPEAr3xx devices all feature the ARM926 core running at up to 333 MHz, an external
DDR2 memory interface and a configurable set of powerful on-chip peripherals.
This application note provides guidelines for successfully designing the PCB layout for
SPEAr3xx applications. It covers the following main topics:
■ Power integrity
■ DDR memory interface
■ USB signals
■ GPIO/CLD signals
■ External clock
Placement guidelines for the decoupling capacitors are provided in Appendix A.
May 2010 Doc ID 14204 Rev 2 1/22
www.st.com
Contents AN2674
Contents
1 Power integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 PCB stack up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Via padstack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Part orientation and placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Ground and power supply connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 DDR memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 DRAM power decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Data signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Trace length matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Trace length matching, dual DRAM configuration . . . . . . . . . . . . . . . . . . 10
2.5 Return path integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6 Clock routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.7 Vref routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.8 Observability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 USB routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 USB decoupling and reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 USB Device Vbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 GPIO and CLD interface considerations . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Using an external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.0.1 External clock signal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.0.2 Voltage translation of external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.0.3 TDR test traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.0.4 Layer order check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Appendix A Low-inductance decoupling capacitor layout . . . . . . . . . . . . . . . . . 19
A.1 0402 compact land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
A.2 Low inductance layout for decoupling capacitors . . . . . . . . . . . . . . . . . . . 20
2/22 Doc ID 14204 Rev 2
AN2674 Power integrity
1 Power integrity
One of the most important requirements of a reliable high-speed memory interface, and
most commonly underestimated, is a low impedance, wide bandwidth power supply at the
power and ground balls of the devices. Achieving the necessary performance requires the
minimizing of all parasitic inductances found in power delivery and grounding connections,
exploiting various techniques to provide low impedance paths, and attention to controlling
plane resonances.
A solid unbroken ground plane located close to the high-speed devices in the PCB layer
stack is critical. The ground plane must not have large gaps anywhere in the area of the
interface. Be especially aware of overlapping anti-pads that can create an extended gap in
the internal plane layers.
A power plane closely spaced to the ground plane greatly aids the high-frequency
decoupling by providing a low inductance path between a capacitor and the device's power
balls.
All high-frequency decoupling capacitors should utilize a low-inductance layout.
1.1 PCB stack up
Stack up should include a closely spaced power/ground plane pair. A minimum of 6 layers is
necessary.
Recommendation:
Layer 1: signal
Layer 2: ground plane, unbroken
Layer 3: power plane/islands, signals
Layer 4: signal/power routing
Layer 5: ground plane, unbroken
Layer 6: signal
Dielectric thickness should be selected to support required signal trace characteristic
impedances and power plane capacitance/inductance. Resonance analysis should be
performed on all plane cavities.
1.2 Via padstack
Via padstack dimensions should support density requirements. Anti-pad diameter should be
small enough to allow an adequate copper web between clearance holes of adjacent vias,
and still meet PCB fabrication tolerances.
1.3 Part orientation and placement
The DRAM placement and orientation should be given priority over other unassociated
components in order to minimize trace lengths. Closely following the signal trace routing
guidelines allows trace lengths to be reduced.
Doc ID 14204 Rev 2 3/22
Power integrity AN2674
1.4 Ground and power supply connections
For proper operation of devices, it is critical provide a very low impedance wide bandwidth
connection to ground and the voltage supplies. To achieve this it is necessary to minimize
inductance between the device power and ground balls and the PCB ground plane and
decoupling network.
The above guideline also applies to other critical components: termination resistors,
decoupling capacitors, ICs, multiple ground or power pins from the same IC.
Each ground ball should be directly connected to the PCB ground plane with its own via. Do
not share vias between multiple ground balls. An exception to this rule is the center 6x6
ground ball grid, which should have a fully populated ground via grid between the balls and
the surface layers can be filled.
Each power ball should be directly connected to the PCB decoupling network with its own
via. Do not share vias between multiple power balls except when multiple power balls are
adjacent to each other and are connected to the same voltage plane. In any case, use the
maximum number of vias that space allows.
To avoid cross-contamination of ground or power supplies between different devices (for
example, an IC and a termination resistor), multiple ground or power balls should not share
ground connections. Each ball/pin should have their own via to the ground or power plane,
not a shared via. Power and ground connections should not simply be connected to surface
layer copper fill areas - these are not good low impedance paths at high-frequencies.
Ball to via trace: Each ground and power ball should be connected to it's via with a short,
wide trace. It is critical to minimize trace length and maximize trace width. Trace length
should be less than 1 mm in the ball field, 0.25 mm outside a ball field, Trace width should
be wide. Do not simply connect ground or power balls to surface fill areas. A close, direct via
to the ground or power plane is necessary. In cases where it is not possible to achieve this
length, there is a relatively high impedance. Every effort should be made to minimize the
length, and to consider only power connections requiring lower bandwidth for high
impedance power connections.
Ferrite beads and RC filters: The perceived need for ferrite beads and RC filters is very
often the result of poor grounding and power supply decoupling, resulting in excess noise on
power rails. A well-designed power delivery network eliminates the need for these remedies.
4/22 Doc ID 14204 Rev 2
AN2674 DDR memory interface
2 DDR memory interface
2.1 DRAM power decoupling
A low impedance wide bandwidth power delivery network (PDN) is critical for the proper
operation of high-speed ICs such as SPEAr and DDR memory. If the PDN impedance is too
high or does not have sufficient bandwidth, this affects the logic performance, resulting in
ground and rail bounce, slower rise/fall times of both I/O and internal logic, which in turn
result in delayed timing of events. These timing delays, from inadequate ground and power,
subtract directly from the specified timing budget, which in turn can result in failure of the
interface.
To achieve a low impedance, wide bandwidth power delivery network, it is critical to use
appropriate decoupling capacitors and capacitor layout. A large portion of the power
delivery network's frequency spectrum is above the series resonant frequency of the
decoupling capacitors, where they are inductive. The PCB layout for decoupling capacitors
is also inductive, and is a larger inductance than the capacitor itself. It is necessary to select
capacitors with low inherent inductance (small package size), a lossy dielectric, and a PCB
layout that provides the lowest possible inductance. For IC core voltage and high-speed I/O
supplies (like DDR), as many capacitors should be used as can fit in the space available.
This adds many parallel paths, reducing the overall inductance seen by the IC. A small
capacitor package size and a small layout can be used to enable this.
Capacitors: Use 0402 package size to minimize the mounting inductance. The small 0402
package frees more board space, which is essential in high-density areas for more
decoupling capacitors and signal routing. A capacitance value of 100 nF or larger is
recommended, with X7R or X5R dielectric. Do not use Y5V dielectric for decoupling of midfrequency applications. A few capacitors of smaller capacitance value probably may be
necessary to suppress plane resonance. The correct value(s) to use for controlling
resonance is very dependent on the board layout and stack up and must be determined
individually for each unique PC board.
Decoupling capacitor layout: The layout of decoupling capacitors is extremely important
to minimize the induction loop formed between the capacitor and the IC power and ground
balls. The vias should be placed on the side of the capacitor lands, not the ends. The vias
should be located at minimum keepout distance and connected to the capacitor lands with a
wide trace - at least as wide as the via pad. Vias of opposite polarity should be placed as
close together as possible (minimum keepout distance) and vias of the same polarity should
be kept separated as much as possible. Following these layout guidelines can reduce the
capacitor mounting induction loop by 50% or more over a layout with vias at the end of the
capacitor lands. This is a very significant improvement, and is free. If space allows, a second
pair of vias on the opposite side of the capacitor may be added to reduce the inductance
further.
Doc ID 14204 Rev 2 5/22
DDR memory interface AN2674
Figure 1. An example of an effective low-inductance decoupling capacitor location
and mounting layout.
2.2 Data signal routing
Signal trace geometries:
Width: 4 mil to 5mil, 0.1 mm to 0.13 mm
Minimum space: 4 mil to 5 mil, 0.1 mm to 0.13 mm
Trace to trace spacing should be increased where routing density allows to reduce crosstalk.
A minimum separation of 10 mils is recommended, except for BGA escape areas.
All signals should be routed referenced to a ground plane, not a power plane.
Do not route any DDR2 signals on top of split planes or voids of copper.
Do not route any other signals inside or on top of the area reserved for DDR.
Maintain adequate separation between DDR signals and any other signals.
6/22 Doc ID 14204 Rev 2
AN2674 DDR memory interface
Traces routed near the edge of a reference plane should maintain at least 30 mil gap to the
edge of the reference plane.
To minimize the reflection all the traces should have an impedance of 55 Ohm ± 10%.
Data lanes:
DL0: Data Lane 0 includes DQ0-DQ7, LDQS-LDQSn, LDM.
Route these signals on the same layer(s), with similarly located layer transitions if they
exist.
Length/timing skew: This set of signals traces must have their lengths matched to
within 2.5 mm or 100 mils (approximately 15 ps).
DL1: Data Lane 1 includes DQ8-DQ15, UDQS-UDQSn, UDM.
Route these signals on the same layer(s), with similarly located layer transitions if they
exist.
Length/timing skew: This set of signals traces must have their lengths matched to
within 1.5 mm or 60 mils (approximately 10 ps).
Note: Trace lengths for different clock domains are not required to be matched. Trace lengths for
DB0 do not need to match the trace lengths for DB1. Trace lengths for address/command
signals do not need to match trace lengths for DB0 or DB1. Use minimum trace lengths
within each clock domain.
CLK/CLK# and DQS/DQS#
CLK/CLK# and DQS/DQS# signals should be routed as differential pairs, length matched.
GATE_OPEN(0,1)
GATE_OPEN(0,1) must be left unconnected. Do not connect any trace, via, or test point to
balls Y13 and Y17.
2.3 Trace length matching
The SPEAr3xx package substrate does not have equal-length DDR signal traces. To insure
timing alignment for all signals, both the substrate trace length plus the PCB trace length for
each signal must be equalized to meet the trace length skew tolerance for all signals within
the clock domain. A procedure for accomplishing this is provided below, along with a
worksheet to facilitate this process during DRAM interface layout. The procedure may
require an iteration if the initial longest trace must be lengthened to accommodate
serpentine routing of other signals.
To determine trace length matching requirements for each signal, follow these steps,
utilizing the worksheet provided. Ltol (maximum length difference within a clock domain) is
2.5 mm, or 100 mils.
1. Route signals per above guidelines, using the shortest possible length on all signals at
this step (length equalizing is done later).
2. Tabulate the lengths of all traces that were routed in step 1, by filling in worksheet in the
column labeled "INITIAL SHORTEST PCB TRACE LENGTH", and "PCB VIA
LENGTHS".
Doc ID 14204 Rev 2 7/22
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