ST AN2656 Application note

AN2656

Application note

STM32F10xxx

LCD glass driver firmware

Introduction

This application note describes a technique for driving liquid crystal displays (LCD) with STM32F10xxx microcontrollers (MCU), that is without any specific on-chip LCD driver hardware. This technique offers a solution for applications that require a display at low cost together with the versatile capabilities of standard STM32F10xxx MCUs. This application note also provides a technique to control the LCD contrast through firmware.

After an introduction on LCDs, Section 1, Section 2 & Section 3 describe the typical waveforms required to drive an LCD with a multiplexing rate of 1 or 2 (duplex) and 4 (quadruplex). Section 3 presents a solution based on a standard STM32F10xxx MCU directly driving a quadruplex LCD. This solution can be implemented with any STM32F10xxx MCU as it only requires the standard I/O ports and one timer, which are standard features on all STM32F10xxx MCUs. Section 4 describes how to use the STM32F10xxx LCD glass library and gives a brief presentation of the LCD glass demo.

Section 5 describes low-power management using the LCD glass, and gives current and

load CPU measurements. Finally, Section 7 gives an example of the LCD connections to the STM32 MCU (two types of LCDs: 4 digits (64 segments: ref CT4-098-LV) and 8 digits (128 segments: ref: PD-878).

With the STM32F10xxx LCD glass library, the CPU load for controlling the LCD is around

0.05% (at 72 MHz), and the number of external components is kept to the minimum (two external resistors per COM line). The number of I/Os involved is the same as in solutions using an on-chip LCD hardware driver or an external hardware LCD driver. With firmware contrast control, the STM32F10xxx MCU offers a very flexible solution that can be adapted easily to a range of applications.

The measured DC value depends on the used resistors (refer to Section 3) and the user configuration: LCD interruption priority configuration (refer to Section 4.2).

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Contents AN2656

Contents

1 LCD principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 LCD drive signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Single backplane LCD drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Duplexed LCD drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Quadruplex LCD drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3.1 LCD mean voltage calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.2 Contrast calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Example of a quadruplex LCD with STM32F10xxx . . . . . . . . . . . . . . . 13

4 Firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 How to use the LCD library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1.1 How to select the LCD glass by firmware . . . . . . . . . . . . . . . . . . . . . . . 18

4.1.2 How to select GPIOs to connect the LCD glass to STM32F10xxx . . . . 18

4.1.3 How to select the timer interrupt priority that drives the LCD . . . . . . . . 20

4.1.4 LCD contrast control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2 LCD timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2.1 LCD with high interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2.2 LCD with low-high interrupt priority (using boosting priority) . . . . . . . . . 22

4.2.3 LCD interrupt always with lowest priority . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3 Default demo configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5 LCD glass in battery-powered and low-power applications . . . . . . . . 24

5.1 Hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2 LCD glass managed by the timer using the Sleep low-power

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2.1 Some current and CPU load measurements . . . . . . . . . . . . . . . . . . . . . 25

5.3 LCD glass managed by the RTC and using the Stop low-

power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3.1 Some current and CPU load measurements . . . . . . . . . . . . . . . . . . . . . 27

6 Comparison of the timer and RTC methods . . . . . . . . . . . . . . . . . . . . . 29

6.1 Timer method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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AN2656 Contents

6.2 RTC method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7 Hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.2 LCD segment line connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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List of figures AN2656

List of figures

Figure 1. LCD principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Equivalent electrical schematic of an LCD segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. LCD signals for direct drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Basic LCD segment connection in duplexed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. LCD signals for duplexed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. Basic LCD segment connection in quadruplexed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. LCD timing diagram for quadruplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 8. LCD timing diagram for a single segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 9. Hardware connection diagram (1/2 bias control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 10. LCD timing diagram with active and dead time (to decrease Vrms). . . . . . . . . . . . . . . . . . 14

Figure 11. LCD timing diagram with active and dead time (to increase Vrms) . . . . . . . . . . . . . . . . . . 15

Figure 12. Screenshot of Vcom3 and Vsegx (Segment1 of digit2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 13. Screenshot of the four common lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 14. Timing used by the STM32F10xxx LCD library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 15. LCD timing diagram for a single segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 16. Hardware connection diagram (1/2 bias control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 17. Timer method state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 18. Timer method chronogram (in this case duty cycle = 50%) . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 19. RTC method state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 20. RTC method chronogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 21. LCD - STM32F10xxx connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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AN2656 LCD principle

Mean Signal



1 LCD principle

Figure 1. LCD principle

An LCD panel is composed of many layers. A liquid crystal is filled between two of them (glass plates), that are separated by thin spacers coated with transparent electrodes and orientation layers. The orientation layer usually consists of a polymer (e.g. polyimide) that has been unidirectionally rubbed using, for instance, a soft cloth. As a result, the liquid crystal molecules are fixed, with their alignment more or less parallel to the plates, in the direction of rubbing. The crystal alignment directions at the surface of the two plates are perpendicular so that the molecules between the two plates undergo a homogeneous twist deformation in alignment to form a helix. If no electric field is applied, the birefringent liquid crystal molecules keep their helical structure and rotate linearly polarized light waves passing through the plates. The transmitted light wave is then allowed through a crossed exit polarizer. As a result, the modulator has a bright appearance. On the other hand, if an AC voltage of a few volts is applied, the resulting electric field forces the liquid crystal molecules to align themselves along the field direction and the twist deformation (the helix) is unwound. In this case, the polarization of the incident light is not rotated by the crystal molecules and the crossed exit polarizer blocks the light wave. As a result, the modulator appears dark. The inverse switching behavior can be obtained with parallel polarizers. It must also be noted that gray scale modulation is easily achieved by varying the voltage between the crystal molecule reorientation threshold (reorientation is resisted by the elastic properties of liquid crystals) and the saturation field.

LCDs are sensitive to root mean square voltage (Vrms= ) levels. With a low root mean square voltage applied to it, an LCD is practically transparent (the LCD segment is then inactive or off). To turn an LCD segment on, causing the segment to turn dark (from light gray to opaque black), an LCD RMS voltage greater than the LCD threshold voltage is applied to the LCD. The LCD RMS voltage is the RMS voltage across the capacitor C in

Figure 2, which is equal to the potential difference between the SEG and COM values.

The LCD threshold voltage depends on the quality of the liquid used in the LCD and the temperature. The optical contrast is defined by the difference in transparency of an LCD segment that is on (dark) and an LCD segment that is off (transparent). The optical contrast depends on the difference between the RMS voltage on an on segment (V voltage on an off segment (V V

(rms), the higher the optical contrast. The optical contrast also depends on the level of

OFF

versus the LCD threshold voltage. If VON is below or close to the threshold voltage, the

LCD is completely or almost transparent. If V

). The higher the difference between VON(rms) and

OFF

is close or above the threshold voltage, the

OFF

) and the RMS

LCD is completely black.

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LCD principle AN2656

COM

ai14758

In this document, contrast is defined as D = VON(rms) / V

OFF

(rms).

The applied LCD voltage must also alternate to give a zero DC value to prevent the electrolytic process and so, ensure a long LCD lifetime.

The higher the multiplexing rates, the lower the contrast. The signal period also has to be short enough to avoid visible flickering on the display.

Figure 2. Equivalent electrical schematic of an LCD segment

Note: The DC value should never be more than 100 mV (refer to the LCD manufacturer’s

datasheet), otherwise the LCD lifetime may be shortened. The frequency range is 30 Hz to 200 Hz typically. If it is less, the LCD flickers, if it is greater, power consumption increases.

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AN2656 LCD drive signals

COM

ai14759

S1 = COM – S

OFF

S1 = COM – S

–V

2 LCD drive signals

2.1 Single backplane LCD drive

In a single backplane drive, each LCD segment is connected to a segment line (Sx) and to a backplane (common line) common to all the segments. A display using S segments is driven with S+1 MCU output lines. The backplane is driven with a COM signal between 0 and V with a duty cycle of 50%.

When switching a segment on, a signal with opposite polarity to COM is sent to the corresponding Segment pin. When the noninverted COM signal is sent to the Segment pin, the segment is off. Using an MCU, the I/O operates in output mode at either logic 0 or 1.

Figure 3. LCD signals for direct drive

2.2 Duplexed LCD drive

In a duplexed drive, two backplanes are used instead of one. Each LCD segment line (Sx) is connected to two LCD segments, whose other side is connected to one of the two backplanes or common lines (refer to Figure 4). Thus, only (S/2)+2 MCU pins are necessary to drive an LCD with S segments.

Three different voltage levels have to be generated on the backplanes: 0, V The Segment voltage levels are 0 and V and LCD waveforms. The intermediate voltage V voltages. The STM32F10xxx I/O pins selected as backplanes are set by firmware to output mode for 0 or V

is active, the other is neutralized by applying V two resistors of equal value, externally connected to the I/O pin. By using an MCU with

/2 and VDD.

only. Figure 4 shows typical backplane, segment

/2 is only required for the backplane

levels and to high impedance input mode for VDD/2. When one backplane

/2 to it. This VDD/2 voltage is determined by

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LCD drive signals AN2656

S11

COM1

ai14760

S2 S3

COM2

S12 S21 S22

COM1

ai14761

S1 = COM1 – S1

–V

+VDD/2

COM2

+VDD/2

Case 1 Case 2 Case 3 Case 4

+VDD/2

–VDD/2

Segment 1 Off On Off On

S2 = COM2 – S1

–V

+VDD/2

–VDD/2

Segment 2 On On Off Off

flexible I/O pin configuration, a duplexed LCD drive can be implemented with only 2 external resistor bridges (each on two COM lines).

Figure 4. Basic LCD segment connection in duplexed mode

Figure 5. LCD signals for duplexed mode

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AN2656 LCD drive signals

S11

COM1

ai14762

S2 S3

COM2

S14

COM3

COM4

S12

S13

2.3 Quadruplex LCD drive

In a quadruplex LCD drive, four backplanes are used. Each LCD pin is connected to four LCD segments, whose other side is connected to one of the four backplanes. Thus, only (S/4)+4 MCU pins are necessary to drive an LCD with S segments. For example, to drive an LCD with 128 segments (32 ×4), only 36 I/O ports are required (32 I/O ports to drive the segments, 4 I/O ports to drive the backplanes).

Three different voltage levels have to be generated on the common lines: 0, V The Segment line voltage levels are 0 and V

only. The LCD segment is inactive if the

/2, VDD.

RMS voltage is below the LCD threshold voltage, and is active if the LCD RMS voltage is above the threshold. Figure 7 shows typical backplane, Segment and LCD waveforms. The intermediate voltage V selected as backplanes are set by firmware to output mode for 0 or V high-impedance input mode for V

/2 is only required for Backplane voltages. The MCU I/O pins

/2. The VDD/2 voltage is determined by two resistors of

levels and to the

equal value, externally connected to the I/O pins. When one backplane or COM is active, the other ones are neutralized by applying V

/2 to them.

Figure 6. Basic LCD segment connection in quadruplexed mode

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LCD drive signals AN2656

COM1

ai14763

COM

+VDD/2

COM2

Segx_1 On Segx_2 Off Segx_3 On Segx_4 Off

Vseg – V

COM

Vseg – V

COM1

Vseg – V

COM4

T/8 T/4 T/2 3T/4 T

COM3

COM4

Vsegx

Control period

Single-frame period

Figure 7. LCD timing diagram for quadruplex mode

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