ST AN2647 Application note

AN2647

Application note

Using the STR91xFA external memory interface (EMI)

Introduction

The STR91xFA EMI bus is a very flexible bus and is user programmable. The bus can be configured to interface to different types of memory devices, including SRAM, Flash memory, ROM or PSRAM. Some of the programmable features of the EMI bus are:

●Multiplexed or non-multiplexed bus

●Bus width: 8 or 16 bit

●Address lines select: A0-15 or A0-A23

●Read and Write signal timing and wait state insertion

●Asynchronous or synchronous bus access

●Page or burst mode access

●Chip select signals (CS0-3)

●ALE polarity and pulse width

●Bus clock (BCLK) frequency

This application note covers the EMI asynchronous mode configuration for interfacing to standard memory devices in Section 1: Interfacing with asynchronous memory.

It covers also EMI Synchronous mode which has a different bus timing and configuration in

Section 2: Interfacing with synchronous memory.

Software is available with this application note and can be downloaded separately online from www.st.com.

December 2007

Rev 1

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www.st.com

Contents	AN2647

Contents

1	Interfacing with asynchronous memory . . . . . . . . . . . . . . . . . . . . . . . . .	4
	1.1 Multiplexed or non-multiplexed EMI bus selection . . . . . . . . . . . . . . . . . . .	4

1.1.1 Multiplexed EMI bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Read bus cycle timing configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

EMI_ALE signal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

EMI_RD signal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Write bus cycle timing configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

EMI_WR signal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Byte and word access in 16-bit multiplexed mode . . . . . . . . . . . . . . . . . . . . . . . .10

Address shifting in 16-bit multiplexed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.1.2 Non-multiplexed EMI bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read bus cycle timing configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

EMI_RD Signal Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Write bus cycle timing configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

EMI_BWR signal configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Half word and word access in 8-bit non-multiplexed mode . . . . . . . . . . . . . . . . .13

Page mode timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

1.2 Other EMI bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.2.1 Bus control register (BCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.2.2 EMI port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2.3 BCLK clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.2.4 Memory bank read and writing timings . . . . . . . . . . . . . . . . . . . . . . . . . 17

	1.3	EMI bus configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	1.4	Executing code from external SRAM vs. internal Flash . . . . . . . . . . . . . .	18
2	Interfacing with synchronous memory . . . . . . . . . . . . . . . . . . . . . . . . .		19
	2.1	PSRAM overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
		2.1.1 Bus interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	2.2	Connecting the EMI bus to a PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . .	22

2.2.1 PSRAM bus operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Asynchronous mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

EMI bus configuration for asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . .25

EMI read and write asynchronous bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Synchronous burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

PSRAM BCR register configuration for synchronous burst mode . . . . . . . . . . . .28

EMI bus configuration for synchronous burst mode . . . . . . . . . . . . . . . . . . . . . . .28

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EMI burst read bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

EMI burst write bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

DMA for high speed data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

3

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Interfacing with asynchronous memory	AN2647

1 Interfacing with asynchronous memory

1.1Multiplexed or non-multiplexed EMI bus selection

The multiplexed EMI bus is selected if you have a 16-bit system bus or using 16-bit memory device. The multiplexed bus requires a 16-bit address latch, as most memory devices do not accept multiplexed address/data input.

The 8-bit non-multiplexed bus is suitable for 8-bit memory or I/O devices. In this configuration, the EMI memory banks are limited to 64 KB each, as there are only 16 address lines available.

In general the non-multiplexed bus has a shorter bus cycle that can be completed in one bus clock period (tBCLK) while the multiplexed bus takes minimum of 3 BCLK clocks. The multiplexed bus has a 16 bit data bus, and can provide high data transfer rate for memory device like PSRAM that supports burst mode. The DMA Controller can be programmed to perform burst data transfer between the internal SRAM and the EMI bus.

1.1.1Multiplexed EMI bus configuration

The multiplexed bus has different bus signals and port assignments than the nonmultiplexed bus. As shown in Table 1, Ports 8 and 9 provide the multiplexed 16 bit address and data bus (AD0-AD15), the optional higher address A16-A23 are assigned to Port 7. Figure 1. & Figure 2. show a typical EMI multiplexed bus connecting to two 16-bit memory devices: a 4 MB ISSI SRAM and a 4 MB SPANSION Flash memory. The SN74LVC16373A is a high speed 16-bit address latch with maximum tPD delay of 4.2 ns. Note only four pins on Port 7 are address lines, the remaining four pins are for other I/O functions.

Table 1.	Multiplexed bus signals
Signal name		Pin / Port assignment	Signal description
AD0-AD7		Port 8	Multiplexed address/data bus AD0-AD7
AD8-AD15		Port 9	Multiplexed address/data bus AD8-AD15
A16-A23		Port 7	Address A16-A23, pin configurable
ALE		EMI_ALE	Address Latch signal. Polarity and width is programmable
Read		EMI_RDn	Read signal
Write Low		EMI_BWRn	Low Byte (D0-D7) Write signal or
(Low Byte Select)		(EMI_WRLn or EMI_LBn)	Low Byte Select signal.
Write High		EMI_WRHn	High Byte (D8-D15) Write signal or
(High Byte Select)		(EMI_UBn)	High Byte Select signal
Write Enable		EMI_WEn	Write Enable signal, use together with the UB/LB byte
			select signals in synchronous mode.
		Port 0(P0.4-P0.7) or	One chip select for each of the 4 Memory Banks.Can be
CS0-CS3		Port 5 (P5.4-P5.7) or
			assigned to any of the 3 port.
		Port 7 (P7.4-P7.7)

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AN2647	Interfacing with asynchronous memory

Figure 1. 16-bit Flash multiplexed bus connection

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Interfacing with asynchronous memory	AN2647

Figure 2. 16-bit SRAM multiplexed bus connection

Note:	Please note the logic gates used are needed to tolerate the 8-bit data operations.
	After power up or system reset, the EMI bus is default to a very slow, asynchronous,
	multiplexed bus. User need to configure the GPIO ports. The read and write timings listed
	below to set up a memory bus that meets your system's requirement for optimal
	performance.

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AN2647	Interfacing with asynchronous memory

Read bus cycle timing configuration

Figure 3. shows a typical Read Bus Cycle. All bus timings are referenced to the internal BCLK clock signal. BCLK clock is only available on an external pin for various usage on the 144 pin BGA package.

Figure 3. Read bus cycle, 16-bit multiplexed bus

EMI_ALE signal configuration

The EMI_ALE signal is used to latch the address A0-15 by the external address latch, or as a direct input to memory device that have an ALE pin. The EMI_ALE by default is one BCLK period in length with active high polarity. It can be programmed to be 2 BCLK period in asynchronous mode and the polarity can be active low. The ALE length and polarity are defined in the SCU_SCR0 register.

Address A0-A15 are valid at the leading edge of EMI_ALE and are driven for another half BCLK period after the trailing edge. The AD bus is tri-stated after the address phase is over. A16-23 are not multiplexed and remain stable until the end of the bus cycle.

EMI_RD signal configuration

The EMI_RDn timing is controlled by the WSTRD value in the EMI_RCRx register (Read Wait State Control) and the WSTOEN value in the EMI_OECRx register (Output Enable Control).

●WSTOEN: Output Enable. WSTOEN specifies the delay between the assertion of the chip select and the time EMI_RDn signal goes low. The delay is defined in terms of tBCLK.

The minimum WSTOEN value is 2 in a multiplexed bus (for ALE with one BCLK period

width). EMI_RDn becomes active after 2 tBCLK so as not to overlap the address phase of the bus cycle.

●WSTRD: Read wait state. WSTRD specifies the pulse width, or the rising edge of

EMI_RDn. The pulse width is defined in terms of number of tBLCK and is = (WSTRDWSTOEN+1).

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Interfacing with asynchronous memory	AN2647

The choice of the WSTRD value depends on the access time of the memory device, slow memory requires more wait states. Typically, the memory access time must meet the following condition:

Memory Read access time < (tRAS + tRP - tRDS)

Where tRAS is the EMI read address setup time, tRP is the EMI_RDn pulse width and tRDS is the data setup time.

The EMI Bus stops driving address A16-A23 and the CSx signal at the rising edge of EMI_RDn.

The read bus cycle in Figure 3. has the following configuration:

ALE Length = 1

WSTOEN = 2

WSTRD = 3

The above read signal configuration can read a memory device with access time of less

than (4*tBCLK - tRDS)ns, where tRDS is the data setup time as specified in the STR91xFA data sheet.

Write bus cycle timing configuration

In asynchronous bus configuration, the default write signals are EMI_WRLn and EMI_WRHn. The other set of write signal selection, EMI_WEN, EMI_LBn and EMI_UBn, are available in BGA package in synchronous mode only. Figure 4. shows a typical Write Bus Cycle. The write bus cycle timing differs from the read bus cycle in two ways:

–The write signals EMI_WRLn and EMI_WRHn (EMI_WRXn) align with the falling edge of the BCLK

–The write signals are terminated half BCLK period before the CSx signal.

Figure 4. Write bus cycle, 16-bit multiplexed bus

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AN2647	Interfacing with asynchronous memory

EMI_WR signal configuration

The EMI_WRxn timings are controlled by the WSTWR value in the EMI_WCRxn register (Write Wait State Control) and the WSTWEN value in the EMI_WECRx (Write Enable Control) register.

●WSTWEN: Write Enable. WSTWEN specifies the delay period between the assertion of the CSx chip select and the falling edge of EMI_WRxn. The delay is defined in terms of BCLK clock periods which is (WSTWEN + 1/2) for asynchronous write cycles. The minimum WSTWEN value is 1 in a multiplexed bus (for ALE with one BCLK period width).With WSTWEN=1, EMI_WRxn becomes active only after the address phase is over.

●WSTWR: Write wait state. WSTWR specifies the pulse width of EMI_WRx. The pulse width is defined in terms of BLCK periods and is equal to (WSTWR-WSTWEN+1) for asynchronous write cycles.

The choice of the WSTWEN and WSTWR values depend on the address and data setup

time and data hold time of the memory device. The STR9 provides at least 1.5 tBCLK of address setup time with WSTEN=1; and by default 0.5 tBCLK of data and address hold time. The WSTWR or pulse width is then set accordingly to meet the data setup time of the

memory device

The write bus cycle in Figure 4. provides address setup time of 2.5 *tBCLK, data setup time of 1*tBCLK and 0.5*tBCLK of data hold time.

Byte and word access in 16-bit multiplexed mode

The previous sections describe the read and write timings for 16-bit or half word access. The CPU can generate 8-bit or 32-bit access using the assembly instruction of STRB, LDRB or STR, LDR. The 8-bit bus cycle is the same as the 16-bit bus cycles, except AD15-AD8 are not driven during the data phase of the cycle.

For a 32-bit access, the EMI generates two consecutive 16-bit bus cycles. The two bus cycles are identical to the standard 16-bit cycle, the only difference is the EMI_CS chip select signal stays low during the two write cycles. Figure 5. shows the bus timings when the CPU executes a 32-bit STR instruction followed by a LDR instruction. Note the EMI_CS signal stays low in the two write bus cycles, but are separated in the two read bus cycles. The two half words that were read in the two LDR read cycles are combined into one word in the EMI block before being transferred to the CPU.

Figure 5. Word (32-bits) write and read bus cycles in 16-bit multiplexed mode

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Interfacing with asynchronous memory	AN2647

Address shifting in 16-bit multiplexed mode

The internal address (A31-A0) in the ARM core is "byte addressable address", so every address points to a byte location. The internal address is right shifted by one when it is driven to the external 16-bit EMI bus. The resulting EMI address is then pointing to a 16-bit or half word location. There is no need to shift the address by one when connecting the EMI bus to a 16-bit memory device. The EMI A0 address should be connected to the A0 pin of the memory device.

Note: 1 The EMI multiplexed bus can also be configured as an 8-bit bus by setting the memory width bits in the EMI_BCRx register to "00". In this configuration, Port 8 drives the AD7-AD0 address/data bus, while Port 9 drives A15-A8. Please note address A15-A8 must be latched externally as in 16-bit mode.

2 A related software is provided for both SRAM and Flash interfaces already defined.

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1.1.2Non-multiplexed EMI bus configuration

The 8-bit non-multiplexed bus has a different set of bus signal, port assignment and bus timing. Table 2 shows the non-multiplexed bus signal pin assignments.

The non-multiplexed bus has 16 address lines and this limits the memory bank size to no more than 64 KB. Figure 6. shows a typical non-multiplexed bus connection to an 8-bit Cypress SRAM.

Table 2.	Non-multiplexed bus signals
Signal name		Pin / Port assignment	Signal description
D0-D7		Port 8	Data bus D0-D7
A0-A7		Port 7	Address A0-A7
A8-A15		Port 9	Address A8-A15
Read		EMI_RDn	Read signal
Write		EMI_BWRn	Write signal, same as EMI_WRLn
		Port 0(P0.4-P0.7) or	One chip select for each of the 4 Memory
CS0-CS3			Banks.Can be assigned to any of these two
		Port 5 (P5.4-P5.7) or
			ports.

Figure 6. Non-multiplexed bus port connection

Read bus cycle timing configuration

Figure 7 shows a typical Read Bus Cycle. All bus timings are referenced to the internal BCLK clock signal. BCLK clock is only available on an external pin for various usage on the 144 pin BGA package.

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