ST AN2641 Application note

AN2641

Application note

Using the color LCD controller (CLCD) in the SPEAr embedded MPU family

Introduction

The SPEAr embedded MPU family is family of configurable MPUs, based on the ARM926 CPU core. Several members the SPEAr MPU family have an embedded ARM PL-110 ColorLCD controller (CLCD). This Application Note describes how to configure and operate any type of color LCD with the CLCD controller and provides application developers with troubleshooting information on common integration issues.

Color display devices play an important role in any embedded system, since usually displays are the most visible output devices.

In SPEAr, the CLCD is connected internally to the AHB bus and acts as a bus master-slave module. The CLCD performs translation of pixel-coded data into the required formats and timings to drive a variety of single/dual mono and color STN as well as color TFT LCD displays. The CLCD fetches the data for display from a frame buffer and uses its own dedicated DMA controller to transfer the display data to the LCD panel.

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Contents	AN2641

Contents

1	Overview of the CLCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
2	CLCD panel programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . .	7
	2.1 Panel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7

2.1.1 X and Y resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 Synchronization parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.3 Dimension related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Panel clock source and frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.1 Clock related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

	2.3	Panel display type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
		2.3.1 Display related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
3	CLCD controller dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	3.1	Data related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
4	Enabling and disabling the CLCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
5	CLCD interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17

5.1 Interrupt causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 Interrupt related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6	Linux frame buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	6.1	Frame buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	6.2	Kernel level modifications for CLCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	6.3	User level perspective of CLCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23

6.3.1 Data structures for user level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3.2 User level application sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4 More details on the frame buffer in Linux . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4.1 Data structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4.2 A brief look at the source files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7	Touchscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		30
	7.1	Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	7.2	Linux input layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31

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	7.3	Calibration process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 31
8	Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 33
	8.1	Video flickering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 33
	8.2	Video tearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 33
	8.3	White screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 33
9	Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 34
Definitions . . . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 35
10	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 36

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List of tables	AN2641

List of tables

Table 1. Different display types and their properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 2. Palette data storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3. Source code information on frame buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 4. Acronyms used in this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 5. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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AN2641	List of figures

List of figures

Figure 1. A basic CLCD panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. CLCD panel layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. PLL2 connection for CLCD clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. Data flow in CLCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. CLCD OFF/ON sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6. Advantage of using the frame buffer architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. CLCD panel structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. Return CLCD panel structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. Entry of CLCD info for menu config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10. CLCD selection from menu config - 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 11. CLCD selection from menu config - 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 12. Structure fb_var_screeninfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 13. Structure fb_fix_screeninfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14. Structure fb_cmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 15. A sample user application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 16. Structure fb_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 17. Structure fb_ops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 18. Touchscreen state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 19. Sequence of events from touchscreen driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 20. Appearance of calibration tool for touchscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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Overview of the CLCD controller	AN2641

1 Overview of the CLCD controller

Main features:

●Dual 16-deep programmable 32-bit wide FIFOs for buffering incoming display data

●Supports single and dual panel mono Super Twisted Nematic (STN) displays with 4 or 8-bit interfaces

●Supports single and dual-panel color and monochrome STN displays

●Supports Thin Film Transistor (TFT) color displays

●Resolution programmable up to 1024 x 768

●15 gray-level mono, 3375 color STN, and 32K color TFT support

●1, 2, or 4 bits-per-pixel (bpp) palettized displays for mono STN

●1, 2, 4 or 8 bpp palettized color displays for color STN and TFT

●16 bits-per-pixel (bpp) true-color non-palettized, for color STN and TFT

●24 bpp true-color non-palettized, for color TFT

●Programmable timing for different display panels

●256 entry, 16-bit palette RAM, physically arranged as a 128 x 32-bit RAM

●Frame, line and pixel clock signals

●AC bias signal for STN and data enable signal for TFT panels

●Patented gray scale algorithm

●Supports little-endian, big-endian or WinCE data formats

●LCD can support standard panel resolutions such as:

–320 x 200, 320 x 240

–640 x 200, 640 x 240, 640 x 480

–800 x 600

–1024 x 768

Types of LCD panel supported are:

●Active matrix TFT panels with up to 24-bit bus interface

●Single-panel monochrome STN panels (4-bit and 8-bit bus interface)

●Dual-panel monochrome STN panels (4-bit and 8-bit bus interface per panel)

●Single-panel color STN panels, 8-bit bus interface

●Dual-panel color STN panels, 8-bit bus interface per panel

●Compliance to the AMBA Specification (Rev 2.0) onwards for easy integration into the SPEAr MPU device

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2 CLCD panel programmable parameters

To allow the CLCD controller to interface with the CLCD panel you intend to use in your application, you have to program a set of parameters, which varies according to the type of CLCD. For example, some parameters depend upon CLCD dimensions and synchronization, other parameters depend on the CLCD clock source and frequency, or the display panel type.

2.1Panel dimensions

This section describes the parameters and the corresponding registers that depend on the LCD dimensions: X and Y resolution, vertical and horizontal synchronization.

2.1.1X and Y resolution

The entire screen of CLCD is composed of pixels, each pixel a single dot. The number of pixels along the horizontal axis forms the X-resolution and the number of pixels along the vertical axis make up the Y-resolution. X-resolution and Y-resolution are also known respectively as the number of pixels per line and the number of lines per panel.

Figure 1. A basic CLCD panel

(0.0)	X-resolution
	(0.X)
Y-res
olution
(0,Y)	(X,Y)

One common example is a 480 x 272 CLCD panel, which has 480 pixels horizontally and 272 pixels vertically.

2.1.2Synchronization parameters

To draw any image on a CLCD panel, the screen is first scanned left to right is scanned and then the screen is scanned top to bottom. After each scan-line, the electron beam has to move back to the left side of the screen and to the next line, this is called the horizontal retrace. After the whole screen (frame) is painted, the beam moves back to the upper left corner, this is called the vertical retrace.

Since the CLCD panel does not know when a new scan-line starts, the CLCD controller generates a synchronization pulse (Horizontal Sync Width) for each scan-line. Similarly, it supplies a synchronization pulse (Vertical Sync Width) for each new frame. The position of the image on the screen is controlled by the timing of the synchronization pulses.

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Figure 2 summarizes all the synchronization timings. The horizontal retrace time is the sum of the horizontal back porch, the horizontal front porch and the horizontal sync width, while the vertical retrace time is the sum of the vertical back porch, the vertical front porch and the vertical sync width.

The horizontal front porch is the time from picture to sync and horizontal back porch is the time from sync to picture.

The vertical front porch is the time from picture to sync and the vertical back porch is the time from sync to picture.

Figure 2.	CLCD panel layout
	vertical back porch
horiz		horiz	horiz
back	X-res	front	sync
porch		porch	pulse width
	Y-res
	vertical front porch
vertical sync pulse width

2.1.3Dimension related registers

1.HBP, 8-bit [31:24] field in the LCD-Timing1 register: specifies the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been de-asserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles.

2.HFP, 8-bit [23:16] field in the LCD-Timing1 register: sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed.

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When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles.

3.HSW, 8-bit [15:8] field in the LCD-Timing1 register: specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode.

4.PPL, 6-bit [7:2] field in the LCD-Timing1 register: is a value that represents between 16 and 1024 PPL. PPL controls how much data is read from the DMA input buffers through to the gray-scaler as follows:

Actual pixels-per-line = 16 * (PPL + 1)

The Actual pixels-per-line specifies the number of pixels in each line (or row) of the screen.

5.VBP, 8-bit [31:24] field, in the LCD-Timing1 register: specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts just after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates from 0-255 extra line clock cycles.

6.VFP, 8-bit [23:16] field, in the LCD-Timing1 register: specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait.

After the count has elapsed, the CLFP vertical synchronization signal, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit-field in passive mode. VFP generates from G0-255 line clock cycles.

7.VSW, 6-bit [15:10] field, in the LCD-Timing1 register: specifies the pulse width of the vertical synchronization pulse. The register is programmed with the number of line clocks in VSync minus one.

8.LPP, 10-bit [9:0] field, in the LCD-Timing1 register: specifies the total number of lines or rows on the LCD panel being controlled. LPP has an allowed range 1-1024 lines. The register is programmed with the number of lines per LCD panel minus 1. For dual panel displays this register is programmed with the number of lines on each of the upper and lower panels.

2.2Panel clock source and frequency

CLCD_CLK is a free running reference clock (currently 48 MHz), which drives the CLCD controller.

CLCP, the output of the panel clock generator, is the CLCD panel clock frequency which goes from the CLCD controller to the CLCD panel. CLCP can be programmed in the range from CLCD_CLK/2 to CLCD_CLK/33 to match the BPP data rate of the LCD panel.

If the CLCD panel requires a frequency outside this range (CLCD_CLK/2 to CLCD_CLK/33), then an alternative route is to use another clock source (for example PLL2 or AHB) instead of CLCD_CLK and use a prescaler to obtain the desired frequency.

●One choice is to select the AHB as input clock. This can be done just using software modifications. You can select the AHB clock source using the CLKSEL bit and can divide the AHB frequency using the PCD bits. All these registers are described in the

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next section. Using this technique it is possible to generate a frequency of AHB/2, AHB/3, and AHB/4...etc. for CLCP.

●Another choice is to use PLL2. The connection is shown in Figure 3.

–In SPEAr600 the PLL2 output frequency can be taken directly from the clock synthesizer.

–In SPEAr300, an additional connection at board level is required: GPIO (1) must be shorted to PL_CLK3.

Figure 3. PLL2 connection for CLCD clock

	CLCD clock
PL_CLK3	Pll1
	Clock synthesizer
	DDR
	Control
RAS	ler
	Pll2
	ARM
	GPIO(1)

2.2.1Clock related registers

1.CLKSEL, bit [5] in the LCD-timing-2 register, drives CLCDCLKSEL which is the select signal for the external LCD clock multiplexer.

2.Clocks per Line (CPL) field [25:16] in the LCD-Timing2 register, specifies the number of actual CLCP clocks for each line of the LCD panel. This is the number of PPL divided by 1 for TFT displays.

3.Panel Clock Divisor (PCD), bits [31:27] & [4:0] in the LCD-Timing2 register, is used to derive the LCD panel clock frequency CLCP from the CLCDCLK frequency as follows:

CLCP = CLCDCLK / (PCD+2)

For TFT, the PCD can be bypassed by setting the BCD bit.

4.Bypass pixel clock divider (BCD), bit [26] in the LCD-Timing2 register. Setting this to 1 bypasses the PCD logic. This is mainly used for TFT displays.

5.Invert Output Enable (IOE) bit [14] in the LCD-Timing2 register, used to select the active polarity of the output enable signal in TFT mode. In this mode, the CLAC pin is

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used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of CLCP when CLAC is in its active state.

0 = CLAC output pin is active HIGH in TFT mode

1 = CLAC output pin is active LOW in TFT mode

6.Invert panel clock (IPC) bit [13] in the LCD-Timing2 register, used to select the edge of the panel clock on which pixel data is driven out onto the LCD data lines.

0= Data is driven on the LCD data lines on the rising edge of CLCP

1= Data is driven on the LCD data lines on the falling edge of CLCP

7.Invert Horizontal Synchronization (IHS) bit [12] in the LCD-Timing2 register, used to invert the polarity of the CLLP signal.

0= CLLP pin is active HIGH and inactive LOW

1= CLLP pin is active LOW and inactive HIGH

8.Invert Vertical Synchronization (IVS) bit [11] in the LCD-Timing2 register, is used to invert the polarity of the CLFP signal.

0= CLFP pin is active HIGH and inactive LOW

1= CLFP pin is active LOW and inactive HIGH.

9.AC bias pin frequency (ACB) bits [10:6] in the LCD-Timing2 register, applies only to STN displays, which require the pixel voltage polarity to be periodically reversed to prevent damage due to DC charge accumulation. Program this field with the required value minus 1 to apply the number of line clocks between each toggle of the AC bias pin, CLAC. This field has no effect if the CLCD controller is operating in TFT mode when the CLAC pin is used as a data enable signal.

2.3Panel display type

The CLCD controller supports the following types of LCD panels:

●TFT (Thin Film Transistor) display: Active matrix display panels which require a digital color value of each pixel to be applied to the display data inputs.

●STN (Super Twisted Nematic) display: Passive matrix display panels that require algorithmic pixel pattern generation to provide pseudo gray scaling on mono or color creation for display (for which a dedicated hardware element, grey scalar, is provided).

	Table 1.	Different display types and their properties
	LCD type		Single/dual panel	Palettized/non-	Mono/color	BPP
				palettized
	TFT		Single	Non-Palettized	Color	24
	TFT		Single	Non-Palettized	Color	16
	TFT		Single	Palettized	Color	1, 2, 4 and 8
	STN		Single and Dual	Non-Palettized	Color	16
	STN		Single and Dual	Palettized	Color	1, 2, 4 and 8
	STN		Single and Dual	Palettized	Mono	1,2 and 4

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2.3.1Display related registers

1.LCD TFT, bit [5] in the LCD-Control register, selects the display type. For TFT, set to

1.For STN, set to 0.

2.LCD Dual, bit [7] in the LCD-Control register, selects dual or single STN panel. For dual panel STN, set to 1, for single panel STN, set to 0. If TFT panel is used then set to

3.LCD Mono bit [6] in the LCD-Control register, controls whether monochrome STN LCD uses a 4 or 8-bit parallel interface. Set to 0 if mono LCD uses 4-bit interface and set to 1 if mono LCD uses 8-bit interface. This bit has no meaning in other modes and must be programmed to zero.

4.LCD BW bit [4] in the LCD-Control register, selects monochrome or color STN panel. If STN LCD is monochrome (black and white), set to 1. If STN LCD is color, set to 0. This bit has no meaning in TFT mode.

5.The color palette register is described in next section.

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