ST AN2633 Application note

AN2633

Application note

STR91xFA low power management and power consumption

Introduction

Power consumption is a significant issue for developers of embedded systems today. Whether the target application is a cellphone, MP3 player, remote control, bio-medical device or one of a whole new generation of electronic products, it is very likely that efficient power management and low current consumption are on top of the list of design goals. In terms of low power design techniques, more and more embedded designers use dynamic control of clocks and frequencies. For this reason, this application note focuses on this in the context of the STR91xFA microcontroller family.

This application note is intended for system designers who require a hardware implementation overview of the STR91xFA low power modes. It includes details on the power supply circuitry and components, clock systems, register settings and power management. This guideline document is intended to show how to make the best use of the extensive low power features of the STR91xFA microcontroller family,

Software source files can be downloaded with this application note for testing the STR91xFA power modes.

January 2008

Rev 1

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www.st.com

Contents	AN2633

Contents

1	Power supply and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4
	1.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4

1.1.1 Main operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.2 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 5 1.1.3 Battery supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.4 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

		1.3.1	External clock sources: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
		1.3.2	Clock control unit (CCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
		1.3.3	Master clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
		1.3.4	PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 9
		1.3.5	Changing the PLL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
		1.3.6	Clock dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
		1.3.7	Flash memory interface clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
		1.3.8	Baud rate clock (BRCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
		1.3.9	External memory interface (BCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
		1.3.10	USB clock (USBCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
		1.3.11	Ethernet MAC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
		1.3.12	External RTC calibration clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
		1.3.13	Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	1.4	Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
		1.4.1	Normal Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
		1.4.2	Special Interrupt Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
		1.4.3	Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
		1.4.4	Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
		1.4.5	Sleep mode and Idle mode configuration considerations . . . . . . . . . . .	15
2	STR91xFA library low power mode functions . . . . . . . . . . . . . . . . . . .			18
	2.1	SCU_MCLKSourceConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
	2.2	SCU_PLLCmd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	2.3	SCU_RCLKDivisorConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
	2.4	SCU_HCLKDivisorConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21

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	2.5	SCU_PCLKDivisorConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 22
	2.6	SCU_FMICLKDivisorConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 22
	2.7	SCU_APBPeriphClockConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 23
	2.8	SCU_AHBPeriphClockConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 24
	2.9	SCU_APBPeriphIdleConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 24
	2.10	SCU_AHBPeriphIdleConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 25
	2.11	SCU_EnterIdleMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 25
	2.12	SCU_EnterSleepMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 25
	2.13	SCU_SpecIntRunModeConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 26
	2.14	FMI_Config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 27
3	Operating measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 29
	3.1	Board set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 29

3.1.1 Performing measurements with the STR910-EVAL board . . . . . . . . . . . 29 3.1.2 Performing measurements with the Uniboard TQFP128 . . . . . . . . . . . . 29

	3.2	Software provided with this application note . . . . . . . . . . . . . . . . . . . . . .		34
		3.2.1	Source files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
		3.2.2	Hardware environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
		3.2.3	How to use the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
		3.2.4	How to test an example of power modes . . . . . . . . . . . . . . . . . . . . . . . .	35
		3.2.5	Low power mode routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
		3.2.6	Run mode tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
		3.2.7	Sleep mode tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
		3.2.8	Idle mode tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
		3.2.9	Special Interrupt Run mode tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
		3.2.10	Battery supply tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
	3.3	Measurements and typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		41
4	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			47

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1 Power supply and clocks

1.1Power supply

1.1.1Main operating voltages

The STR91xFA requires two separate operating voltage supplies. The CPU and memories operate from a 1.65 V to 2.0 V on the VDD pins, and the I/O ring operates at 2.7 V to 3.6 V on the VDDQ pins.

Figure 1. Power supply overview

128-pin, 144-ball devices

80-pin-devices

AVREF

(VDDQ) AVREF_AVDD

A/D converter

A/D converter

(VDDQ) AVDD

AVSS_VSSQ

AVSS

VDDQ

VSSQ

I/O Ring

(3V or 3.3V) VDDQ

I/O Ring

(3V or 3.3V)

VSSQ

(VDDQ)

VBATT

RTC

(VDDQ) VBATT

RTC

SRAM

SRAM

(1.8V)VDD

(1.8V)

VDD

Core

Core

VSS

VSS

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1.1.2Independent A/D converter supply and reference voltage

The ADC has an isolated power supply which you can separately filter and shield from noise in the PCB.

On 128-pin and 144-ball packages, the ADC unit has an independent analog voltage supply input at pin AVDD (the ADC current consumption is detailed in Section 3.3: Measurements and typical values on page 41) to accept a very clean voltage source. Additionally, an independent supply ground connection is provided on pin AVSS. You can connect a separate external reference voltage input for ADC on the AVREF pin for better accuracy on low voltages inputs. The voltage on AVREF can range from 1.0 V to VDDQ.

On 80-pin/ball packages, the ADC voltage supply is tied internally to the ADC reference voltage pin AVCC_AVREF and the analog ground is shared with the digital ground at a single point, on pin AVSS_VSSQ.

1.1.3Battery supply

	An optional stand-by voltage from a battery or other source may be connected to pin VBATT
	to retain the contents of SRAM in the event of a loss of the main digital supplies (VDD and
	VDDQ). The SRAM will automatically switch its supply from the internal VDD source to the
	VBATT pin when the VDD and VDDQ voltage drops below the LVD threshold (and VBAT
	remains above the threshold).
Note:	In order to use the battery supply, the LVD must be enabled.
	The VBATT pin also supplies power to the RTC unit, allowing the RTC to function even when
	the main digital supplies (VDD and VDDQ) are switched off. By programming the device
	configuration via JTAG, you can select to power only the RTC (by configuring the RTC) or
	both the SRAM (by enabling the PWR bit in the RTC_CR register) and the RTC from VBATT.

1.1.4	Low voltage detector (LVD)
	Voltage dropout: The LVD circuit monitors VDD, and VDDQ supplies and generates a global
	reset whenever either voltage drops below the configured VDD_LVD and VDDQ_LVD levels. If
	the MCU was reset by the LVD, this is flagged in the System status register
	(SCU_SYSSTATUS) and an interrupt request to the VIC is generated if enabled.
	Voltage brownout: You can also program the LVD to generate an Early Warning interrupt
	when either voltage drops below the VDD_BRN and VDDQ_BRN thresholds. The Early Warning
	event signal is connected to the VIC1.7 interrupt channel. Software can manage the Early
	Warning interrupt using the VIC1.7 channel bits in the VIC registers.
Note:	When the LVD is turned off, the VBAT feature is not supported.
	The LVD logic consists of a lower power voltage band gap that provide an accurate voltage
	reference. This voltage reference is used to create the voltage threshold levels that are
	compared with the supply voltages.
	When either voltage supply falls below the threshold for that supply, the LVD generates a
	global reset.

1.2 Power down mode

In STR91xFA low power modes, the Flash automatically reduces its power consumption and can be read immediately after wake-up.

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Power supply and clocks	AN2633

When the STR91xFA is in low power mode, you can also put the Flash in Power Down mode for even lower power consumption. You do this by programming the PWD bit in the Flash Configuration register. The consumption is drastically reduced, but after wake-up from low power, a delay is inserted automatically to ensure the Flash is operational before the CPU starts execution.

1.3Clocks

1.3.1External clock sources:

fOSC: A 4 to 25 MHz oscillator provides the main operating clock for all on-chip functional blocks.

fRTC:The RTC has an independent 32.768 kHz crystal. The RTC keeps on running even when the CPU is in power down or power off mode. This slow RTC clock can also be used in power management.

fUSB: fUSB input clock is not mandatory to generate the 48 MHz for USB clock. It is needed when the PLL is configured to generate a clock that cannot be shared by the USB. The PLL

is able to generate a 48 or 96 MHz clock from the input crystal frequency for internal use by selecting the appropriate multiplier and divider.

fTIMEXT: The TIM Timer/counters can run on the internal peripheral clock or the external TIMEXT input clock. You select this by programming the TIM01SEL and TIM23SEL bits in

the Clock control register (SCU_CLKCNTR). When these pins are not used as clock inputs, they can be configured as GPIO.

1.3.2Clock control unit (CCU)

The CCU generates a master clock of frequency fMSTR. From this master clock the CCU also generates individually scaled and gated clock sources to each of the following

functional blocks within the STR91xFA.

●CPU, fCPUCLK

●Advanced High Performance Bus (AHB), fHCLK

●Advanced Peripheral Bus (APB) fPCLK

●Flash memory interface (FMI), fFMICLK

●UART Baud Rate Generators, fBAUD

●USB, fUSB

1.3.3Master clock sources

The master clock generated by the CCU (Clock Control Unit) has three clock sources that you select using the MCLKSEL[1:0] bits in the Clock control register (SCU_CLKCNTR). Under firmware control, the CPU can switch between the three CCU inputs without introducing any glitches on the master clock output. The clock sources are the PLL output, the oscillator input pin and the RTC clock:

●The PLL takes the 4 to 25 MHz oscillator clock as input and generates a master clock

output up to 96 MHz. The fPLL output frequency is programmable. Typical frequencies are 48 MHz, 66 MHz or 96 PLL MHz (maximum). By default, at power-up the master clock is sourced from the main oscillator until the PLL is ready (locked) and then the CPU may switch to the PLL source under firmware control. The CPU can switch back to

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AN2633	Power supply and clocks

the main oscillator source at any time and turn off the PLL for low-power operation. The PLL is always turned off in Sleep mode.

●The fOSC input clock has a frequency of 4 to 25 MHz. This input clock can be sourced by an external crystal connected to STR91xFA pins X1_CPU and X2_CPU or an external oscillator device connected to X1_CPU.

●RTC is a 32.768 kHz external crystal which can be connected to X1_RTC and X2_RTC or an external oscillator connected to pin X1_RTC to constantly run the real-time clock unit. You can program the application to run from this slow clock when you want to save power.

You can choose the source to match the CPU performance and the power management requirements of your application. Transitions from one clock to another are glitch-free and do not disrupt any on-going activities

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Power supply and clocks	AN2633

Figure 2. Clock control

								EMI_BCLK
							1/2	to External
								memory
								interface
		4 to 25 MHz		AHBDIV		HCLK Peripheral HCLK
X1_CPU	Main						Clock
				(1,2,4)
								to AHB
X2_CPU	OSC	fOSC	RCLKDIV	RCLK			Gating
								peripherals
			(1,2,4,8,16,1024)
MII_PHYCLK		MCLKSEL					Peripheral PCLK
		PHYSEL		APBDIV
						PCLK Clock
		fOSC		(1,2,4,8)			Gating	to APB
		fPLL	fMSTR					peripherals
	PLL
							Peripheral FMICLK
		f			FMICLK
		RTC					Clock
				1/2				to Flash Memory
X1_RTC							Gating
		32.768						Interface
	RTC		to RTC
X2_RTC		kHz
			to WDG (software			Special interrupt
			selectable in WDG			mode control
			register)
								CPUCLK
								to CPU
	32.768 KHz
JRTCLK		RTCSEL
								BRCLK
				1/2			Baud rate clock to UARTs
EXTCLK_T0T1			TIM01CLK
			External clock to TIM0 & TIM1
EXTCLK_T2T3			TIM23CLK
			External clock to TIM2 & TIM3
				1/2			Peripheral 48 MHz USBCLK
							Clock
USB_CLK48M							Gating	to USB block
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1.3.4PLL

As shown in Figure 2, the oscillator input clock (fOSC) is the input clock to the programmable PLL frequency multiplier. When the PLL is active, it generates an output frequency (fPLL) according to the following equation:

fPLL = ( 2 × N × fOSC) ⁄ ( M × 2p)

Where the values of M, N and P must satisfy the following constraints:

1 ≤ M ≤ 255

1 ≤ N ≤ 255

0 ≤ P ≤ 5

1MHz ≤ fOSC ⁄ M ≤ 2MHz

200MHz ≤ ( 2 × N × fOSC) ⁄ M ≤ 622MHz 4MHz ≤ fOSC ≤ 25MHz

You program the M, N and P values by writing to the PLL configuration register (SCU_PLLCONF).

Care is required when programming the PLL multiplier and divider factors, not to exceed the maximum allowed operation frequency (96 MHz).

At power up, the CPU defaults to run on the oscillator clock, as the PLL is not ready (locked). The CPU can switch to the PLL clock only after the LOCK bit in the System status register (SCU_SYSSTATUS) is set. In Sleep mode, the PLL is turned off. When waking up from

sleep mode if the fMSTR is selected to run off the PLL, the CPU waits until the LOCK bit is set before it starts to run.

The LOCK bit is set when the PLL clock has stabilized (locked status) and maintains this

value as long as the PLL is locked. You can select the PLL clock as fMSTR clock source only when the LOCK bit is 1. If the LOCK bit goes to 0 if for any reason, the PLL loses the

programmed frequency in which it was locked. In this case, the LOCK_LOST bit is set and

fMSTR automatically switches back to fOSC. fPLL is restored as the fMSTR source when the LOCK bit becomes 1 again.

The LOCK and LOCK_LOST events can be configured to generate interrupt requests to the VIC.

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1.3.5Changing the PLL configuration

While the CPU is running on the PLL clock, the PLL clock frequency can be changed by updating the SCU_PLLCONF register. You need to follow the steps below to change the clock:

1.Switch the CPU Master Clock source to the OSC by setting bits [1:0] in the SCU_CLKCNTR register to “10”.

2.Write the new configuration to the SCU_PLLCONF register (write the new P, N and M values with the PLL_EN enable bit set to “0”).

3.The SCU_PLLCONF register is updated after the clock has been switched to the OSC.

4.If you need the CPU to run at the new PLL clock frequency, write to the SCU_PLLCONF register again with the new P, N and M values AND the PLL_EN bit set to “1”.

5.Switch the CPU clock source back to the PLL clock by setting bits [1:0] in the SCU_CLKCNTR register to “00”.

6.The CPU Master clock switches automatically from the OSC to the PLL once the LOCK bit is set. Do not initiate another SCU_PLLCONF register change before the LOCK bit is set.

1.3.6Clock dividers

The main clock (fMSTR) can be divided to operate at a slower frequency reference clock (RCLK) for the ARM core and all the peripherals. The RCLK provide the divided clock for the ARM core, and feeds the dividers for the AHB, APB, External Memory Interface, and FMI units.

You program the RCLK divider using the RCLKDIV[2:0] bits in the Clock control register (SCU_CLKCNTR).

The RCLK can be divided by 1, 2 or 4 to generate the AHB clock. The AHB clock is the bus clock for the AHB bus and all bus transfers are synchronized to this clock. The maximum HCLK frequency is 96 MHz.

The RCLK can be divided by 1, 2, 4 or 8 to generate the APB clock. The APB clock is the bus clock for the APB bus and all bus transfers are synchronized to this clock. Many peripherals that are connected to the AHB bus also use the PCLK as the source for the external bus data transfers. The maximum PCLK frequency is 48 MHz.

You program the PCLK and HCLK dividers using the APBDIV[1:0] and AHBDIV[1:0]bits in the Clock control register (SCU_CLKCNTR).

1.3.7Flash memory interface clock

The FMICLK clock is an internal clock derived from RCLK and with the same frequency. You can optionally divide it by 2 by setting the FMI_SEL bit in the Clock control register (SCU_CLKCNTR). FMICLK can be gated through the Peripheral Clock Gating Registers (see Section 1.3.13). The FMICLK determines the bus bandwidth between the ARM core and the flash memory. Typically, codes in the flash memory can be fetched one word per FMICLK clock in burst mode. The maximum FMICLK frequency is 96 MHz.

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1.3.8Baud rate clock (BRCLK)

The baud rate clock is an internal clock derived from fMSTR that is used by the three on-chip UART peripherals for baudrate generation. You can optionally divide the frequency by 2 by

setting the BR_SEL bit in the Clock control register (SCU_CLKCNTR). BRCLK can be gated through the Peripheral Clock Gating Registers (see Section 1.3.13).

1.3.9External memory interface (BCLK)

You can select the frequency of the EMI bus clock (BCLK) to be HCLK or HCLK/2 using the EMIRATIO bit in the Clock control register (SCU_CLKCNTR). By default the frequency is HCLK/2. The BCLK clock is available on the LFBGA package as an output pin. You can disable the BCLK output by setting the BCLK_EN bit in the EMI register (SCU_GPIOEMI).

1.3.10USB clock (USBCLK)

The USB clock can be derived from fMSTR when the frequency is 48 MHz or 96 MHz. If you use another fMSTR frequency, the 48 MHz USBCLK must be sourced from the external pin (GPIO pin). You select this using the USB_SEL [1:0] bits in the Clock control register

(SCU_CLKCNTR). USBCLK can be gated through the Peripheral Clock Gating Registers (see Section 1.3.13).

1.3.11Ethernet MAC clock

Special consideration regarding the Ethernet MAC: The external Ethernet PHY interface device requires it’s own 25 MHz clock source. This clock can come from one of two sources:

●A 25 MHz clock signal coming from a dedicated output pin (P5.2) of the STR91xFA. In this case, the STR91xFA must use a 25 MHz signal on its main oscillator input in order to pass this 25 MHz clock back out to the PHY device through pin P5.2. The advantage here is that an inexpensive 25 MHz crystal may be used to source a clock to both the STR91xFA and the external PHY device.

●An external 25 MHz oscillator connected directly to the external PHY interface device.

In this case, the fOSC input clock doesn't have to be a 25 MHz crystal (from 4 MHz to 25 MHz).

You enable the output clock using the MAC_SEL bit in the Clock control register (SCU_CLKCNTR).

1.3.12External RTC calibration clock

The RTC_CLK can be enabled as an output on the JRTCK pin by setting the Calibration Clock Output Enable bit in the RTC_CR register. The RTC_CLK is used for RTC oscillator calibration. The RTC_CLK is active in Sleep mode and can be used as a system wake-up control clock.

1.3.13Peripheral clock gating

After reset, only the CPU, the Flash memory, the SRAM and a small subset of Peripheral clock gating register 0 (SCU_PCGR0) and Peripheral clock gating register 1 (SCU_PCGR1) registers) of the peripherals start operating. The other parts of the system remain stopped. because the related PCGR bits are reset. To start them, you have to write 1 to the related register bit. You can stop the peripheral again, by writing 0 to the related bit.

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Power supply and clocks	AN2633

This allows you to dynamically control the number of peripherals that are running which allows you to optimize the power used in a very flexible way.

The Idle mode gating mask register 0 (SCU_MGR0) and the Idle mode gating mask register 1 (SCU_MGR1) allow you to define a set of peripherals that are kept running when the microcontroller goes into Idle mode. In Sleep mode, all peripherals except the RTC are turned off.

Clock gating in emulation mode

During emulation mode (debug state of the ARM966E-S processor) the System Controller allows gating the clock of a peripheral or a group of peripherals. The software application can choose to stop the desired peripheral when ARM966E-S enters emulation mode. When you clear the related bit in the Peripheral emulation clock gating register 0 (SCU_PECGR0), or Peripheral emulation clock gating register 1 (SCU_PECGR1), the peripheral clock is gated in emulation mode.

1.4Power modes

The STR91xFA has configurable and flexible power management features that allow you to choose the best power option to fit your application. You can dynamically manage the power consumption or hardware to match the system's requirements. Power management is provided via clock control to the CPU and individual peripherals. The STR91xFA supports the following 4 global power control modes:

	●	Normal Run mode
	● Special Interrupt Run mode
	●	Idle mode
	●	Sleep mode
Note:	In the application development environment, a special mode (Debug state) is active during
	in circuit emulation (ICE). In this mode, the clocks are never switched off when the ICE is in
	use even if the CPU enters Idle or Sleep mode. In Idle mode, the CPU stops fetching
	instructions, but the ICE can override this state in order to run the debugger code. Using

Flash_PD_DBG bit in the Power management register (SCU_PWRMNG) you can configure the Flash to enter power down mode when debug mode is active.

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AN2633					Power supply and clocks
	Table 1.	Comparison of power control modes
	Power State		Clocks	Wake-up event		Description
			- All clocks are ON			- Peripherals active if
	Normal Run mode		- CPU is clocked by RCLK			enabled by the Peripheral
			(divided by RCLKDIV)			Clock Gating Registers
			- CPU is clocked by RCLK
			- While executing interrupt
			service routines, CPU is
			clocked by fMSTR
			(RCLKDIV is bypassed)
	Special Interrupt		in Special Interrupt Run			- Peripherals active if
			mode FIQ.
						enabled by the Peripheral
	Run mode		- In Special Interrupt Run
						Clock Gating Registers
			mode using IRQ,CPU
			operates at full speed,
			when the IRQ service
			routine reads the vector
			address register in the
			VIC.
				-External reset		- CPU off
			-ARMCLK = OFF			- Peripherals active if
				-WDG reset
			-FMICLK = OFF			enabled by the Peripheral
	Idle mode			-Interrupts
						Clock Gating Registers
			-HCLK = ON(1)
				-RTC Alarm		AND the corresponding
			-PCLK = ON(1)
				-External wake-up		bit is set in the Idle Mode
						Gating Mask Registers
						- All clocks off except RTC
			-ARMCLK = OFF	-External reset		- Flash memory in power
			-FMICLK = OFF			down mode
	Sleep mode			-External wake-up
			-HCLK = OFF			- PLL off
				-RTC Alarm
			-PCLK = OFF			- Oscillator pin (4-25 MHz)
						off

(1) The OFF and ON state can be configured in Idle mode gating register 0 (SCU_MGR0) and the mode gating mask register 1 (SCU_MGR1)

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Power supply and clocks						AN2633
	Figure 3. Low power mode state diagram
	Power up reset				Interrupt	Special
						Interrupt
						Run mode
			Normal		Return from
					Interrupt
	Set Idle		Run
	Mode		mode
						Set sleep
						mode
		Interrupt		Reset
		Reset
	Idle			Wake-up
	mode	Wake-up				Sleep
		RTC alarm			RTC alarm
						mode

1.4.1Normal Run mode

This is the default run mode. The CPU executes instructions and any or all of the on-chip peripherals are in active state. You can turn-on or turn-off the clock of any of the peripherals writing to Peripheral clock gating register 0 (SCU_PCGR0) or Peripheral clock gating register 1 (SCU_PCGR1). You can also reduce the frequency (by means of clock dividers) of the various clocks in order to optimize power usage while operating in normal run mode.

1.4.2Special Interrupt Run mode

Special Interrupt mode FIQ

The special interrupt mode using FIQ causes the CPU to temporarily operate at full speed (fMSTR as clock frequency) while servicing one or more interrupts and return back to normal run mode with the speed selected by the clock RCLKDIV divider (see Figure 2) when the interrupt routine is complete. You enable/disable this mode using the CPU_INTR bit in the Power management register (SCU_PWRMNG).

Special Interrupt mode IRQ

The special interrupt mode using IRQ causes the CPU to operate at full speed (fMSTR as clock frequency) when the IRQ service routine reads the vector address register in the VIC

and jumps then to the specified interrupt with the speed selected by the RCLKDIV clock divider. You enable/disable this mode using the CPU_INTR bit in the Power management register (SCU_PWRMNG).

Workarounds

To operate at full speed when servicing the IRQ interrupts, you have to configure the desired clock frequency at the beginning of the interrupt routine. Then, you have to switch the system clock back to the operating frequency after disabling the interrupt.

1.4.3Idle mode

Idle mode is entered under software control, by writing the value ‘001b’ to the PWR_MODE[2:0] bits in the Power management register (SCU_PWRMNG). In this mode,

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AN2633	Power supply and clocks
	the CPU suspends code execution. The CPU and FMI clocks are turned off. The various
	peripherals still continue to operate with their programmed clock rate if they are enabled by
	the related bits of the SCU_PCGRx and the SCU_MGRx registers. If the SCU_MGRx
	register bit is 0, when the system enters Idle mode, the related clock is gated, otherwise the
	peripheral continues to receive the clock if the PCGR bit is set.
	To exit from Idle mode, an interrupt must be generated by one of the active peripherals or
	from an external source:
	● External reset or watchdog reset
	● External or internal peripheral interrupt
	● RTC alarm interrupt
	● Input from EXTINT pins (GPIO pins) via wake-up unit (WIU)
Note:	Before entering Idle mode, you should disable the Prefetch Queue/Branch Cache clock
	(bit 1 in the SCU_MGR0 register) in order to minimize the current consumption.
1.4.4	Sleep mode
	Sleep mode is entered under software control, by writing the value ‘010b’ in the

PWR_MODE[2:0] bits in the Power management register (SCU_PWRMNG). This is the MCU’s lowest power mode. In this mode, all clock circuits (except RTC) and the oscillator pin (4-25 MHz) are turned off. In this mode, the CPU does not execute any instructions. All peripherals except the RTC have their clocks stopped. The ARM Flash Memory is put in power down mode at the same time as the ARM MCU. The ARM MCU when enters into the Power Down mode, generates a PD signal to the Flash Memory. The Flash memory take a recovery time to resume operation on wake-up from sleep mode. The system clock is switched on only after the recovery time is over.

To exit from Sleep mode, one of the following events must occur:

●External reset via the external reset pin

●External interrupt via wake-up unit (WIU)

●RTC Alarm

Note:

In low power modes, the I/O pins keep the same state prior to low power mode entry.

1.4.5Sleep mode and Idle mode configuration considerations

When enabling Sleep or Idle mode, certain requirements must be met to ensure the proper operation of the low power modes. The following sections describe these requirements when entering or exiting Sleep or Idle mode.

Code execution after entering Sleep and Idle mode

Once Idle mode or Sleep mode are entered by writing the PWR_MODE[2:0] bits in the Power management register (SCU_PWRMNG) it takes about 12 crystal oscillator cycles (X1_CPU input frequency) for the device before stopping the execution. In order to avoid executing any valid instructions after the Idle or Sleep bit setting and before entering the mode, it is mandatory to execute a certain number of dummy instructions after the Power management register setting.

The number of dummy instructions to be executed depends on the ratio between the CPU clock frequency and the oscillator input frequency according to the following:

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