ST AN2632 Application note
AN2632
Application note
Communication between small page NAND and
ST72651AR6 using I/O’s
Introduction
This application note presents the practical example of communication between
microcontroller and NAND Flash using general purpose input/output ports (GPIOs).
This document describes the hardware connections and software necessary to
establish
and input/output ports of the ST7 microcontroller. We have used the ST72651AR6 for the
firmware description, but any ST7 MCU can be used as well.
The devices covered by this application note are:
■ NAND128W3A
■ NAND256W3A
■ NAND512W3A
■ NAND01GW3A
communication between the STMicroelectronics small page NAND Flash memory
October 2007 Rev 1 1/12
www.st.com
Contents AN2632
Contents
1 NAND Flash overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Hardware interface with microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 NAND basic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Remaining NAND functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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AN2632 NAND Flash overview
1 NAND Flash overview
The NAND Flash 528 Byte / 264 Word page is a family of non-volatile Flash memories that
uses the Single Level Cell (SLC) NAND cell technology. It is referred to as the small page
family. The devices range from 128 Mbits to 1Gbit and operate with either a 1.8 V or 3 V
voltage supply. The size of a page is either 528 Bytes (512 + 16 spare) or 264 Words (256 +
8 spare) depending on whether the device has an x8 or x16 bus width. The address lines
are multiplexed with the data input/output signals on a multiplexed x8 or x16 input/output
bus.
1.1 Signal description
Ta bl e 1 describes all the small page NAND Flash signals. Figure 1 shows the logical
diagram of NAND Flash.
Ta bl e 3 describes the microcontroller signals used to connect to the small page NAND
devices.
Table 1. Small page NAND Flash signal description
Signal Signal name Description
I/O8-15 Data input/outputs
I/O0-7 Data input/outputs
AL
CL
#E Chip enable
#R Read enable
R/#B Ready/busy
Address latch
enable
Command latch
enable
Input/outputs 8 to 15 are only available in x16 devices. They are used to output the
data during a read operation or input data during a write operation.
Input/outputs 0 to 7 are used to input the selected address output the data during a
read operation or input a command or data during a write operation.
The inputs are latched on the rising edge of write enable. I/O0-I/O7 can be left floating
when the device is deselected or the outputs are disabled.
The address latch enable activates the latching of the address inputs in the command
Interface. When AL is high, the inputs are latched on the rising edge of write enable.
The command latch enable activates the latching of the command inputs in the
Command Interface. When CL is high, the inputs are latched on the rising edge of
write enable.
The chip enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When chip enable is low (VIL) the device is selected.
The Read Enable controls the sequential data output during Read operations. Data is
valid after the falling edge of R. The falling edge of R also increments the internal
column address counter by one.
The Ready/Busy output is an open-drain output that can be used to identify if the
P/E/R controller is currently active.
When ready/busy is low (VOL), a read, program or erase operation is in progress.
When the operation completes, ready/busy goes high (VOH). The use of an opendrain output allows the ready/busy pins from several memories to be connected to a
single pull-up resistor. A low then indicates that one, or more, of the memories is busy.
#W Write enable
#WP Write protect
The write enable input controls writing to the command interface, input address and
data latches. Both addresses and data are latched on the rising edge of write enable.
The write protect pin is input that gives hardware protection against unwanted
program or erase operations. When write protect is low (VIL) the device does not
accept any program or erase operations.
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NAND Flash overview AN2632
Table 1. Small page NAND Flash signal description (continued)
Signal Signal name Description
VCC provides the power supply to the internal core of the memory device. It is the
Vcc Supply voltage
Vss Ground
Figure 1. Logic diagram of NAND Flash
main power supply for all operations (read, program and erase). It is in the range of
1.65-1.95 V for 1.8 V devices and 2.7-3.6 V for 3 V devices.
Ground is the reference for the power supply. It must be connected to the system
ground.
#E
#R
#W
NAND
AL
CL
WP
Flash
AFT
1.2 Memory array organization
The memory array is organized in blocks where each block contains 32 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data, whereas the spare area is typically used to store error correction codes, software
flags or bad block identification.
In x8 devices the pages are split into a main area with two half pages of 256 Bytes each and
a spare area of 16 Bytes. In the x16 devices the pages are split into a 256 Word main area
and an 8 Word spare area.
I/O 8-I/O16, x16
I/O 0-I/O7, x8/x16
R/#B
In this application note the communication with x8 devices is explained. Thus the memory
map is divided as:
BLOCKS each having 32 pages and each page in turn having 528 Bytes. The number of
BLOCKS is decided on the basis of the NAND Flash we are using. This application note
explains the communication using NAND512W3A NAND Flash.
The memory organization for NAND512W3A is as follows:
4096 BLOCKS, 32 pages in each BLOCK, 528 Bytes in each page. Figure 2 shows the
memory arrangement for x8 devices.
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