ST AN2629 Application note

AN2629

Application note

STM32F101xx, STM32F102xx and STM32F103xx

low-power modes

Introduction

This application note is intended for system designers who require a software and hardware implementation overview of the low-power modes of the STM32F101xx, STM32F102xx and STM32F103xx products. It describes how to use the STM32F10xxx product family and details the clock systems, register settings and low-power management in order to optimize the use of STM32F10xxx in applications where low power is key.

This application note should be read in conjunction with the datasheet of the relevant STM32F10xxx product and the STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual.

The STM32F10xxx datasheets, the reference and Flash programming manuals are all available from the STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

The first four sections of this application note introduce the part of the STM32F10xxx devices that is used for low-power configuration. The next sections demonstrate the lowpower feature in an applicative way. Each section refers to software delivered with this document, which give a practical view of power optimization.

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Contents	AN2629

Contents

1	Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7

1.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 7 1.1.2 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

	1.2	Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 8
		1.2.1	Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 9
		1.2.2	Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 9
		1.2.3	Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
		1.2.4	Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
		1.2.5	Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
		1.2.6	Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
		1.2.7	Auto-wakeup (AWU) from low-power mode . . . . . . . . . . . . . . . . . . . . . .	13
2	Clock	. . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
3	Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			16
	3.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
	3.2	Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
	3.3	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16

3.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.2 Resetting RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.3 Reading RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.4 Configuring RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.5 RTC flag assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4	Backup registers (BKP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
	4.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	4.2	Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	4.3	Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	4.4	RTC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21

5	Power and wakeup time measurement . . . . . . . . . . . . . . . . . . . . . . . . .	22
	5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22

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AN2629 Contents

5.2	Power measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22
	5.2.1	Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	5.2.2	Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	5.2.3	Measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25

5.3	Wakeup time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		26
	5.3.1	Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	5.3.2	Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	5.3.3	Measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
	5.3.4	Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29

6	Optimizing power consumption in your application . . . . . . . . . . . . . .		30
	6.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	6.2	Using the advance clock configuration of the STM32F10xxx . . . . . . . . . .	30

6.2.1 Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2.2 Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.3 Typical measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7	Using the Stop and Standby mode in battery-operated applications		35
	7.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
	7.2	Using Wait For Event & Stop Wait For Event . . . . . . . . . . . . . . . . . . . . . .	35

7.2.1 Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2.2 Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.3 Using the Standby mode in an applicative way . . . . . . . . . . . . . . . . . . . . 37

7.3.1 Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.2 Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.4 Typical measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8	Using the Backup domain in very low-power applications . . . . . . . . .			40
	8.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		40
	8.2	Using the Backup domain in an applicative way . . . . . . . . . . . . . . . . . . .		40
		8.2.1	Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
		8.2.2	Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
	8.3	Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		41

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9	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 42

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AN2629	List of tables

List of tables

Table 1. Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2. Sleep-now . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3. Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4. Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. Power measurement results in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 7. Power measurement for Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 8. Wakeup time measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 9. Example measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 10. Example measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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List of figures	AN2629

List of figures

Figure 1. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3. RTC simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 4. RTC second and alarm waveform example with PR=0003, ALARM=00004 . . . . . . . . . . . 19 Figure 5. RTC Overflow waveform example with PR=0003. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 6. HyperTerminal time adjustment interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 7. WFE & STOP WFE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 8. Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 9. HyperTerminal display of time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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AN2629	Power supply

1 Power supply

1.1Introduction

The device requires a 2.0 V to 3.6 V operating voltage supply (VDD). An embedded regulator is used to supply the internal 1.8 V digital power.

The real-time clock (RTC) and backup registers can be powered from the VBAT voltage when the main VDD supply is powered off.

Figure 1. Power supply overview

(VSSA) VREF-		VDDA domain
		A/D converter
(from 2 V up to VDDA) VREF+
		Temp. sensor
(VDD)	VDDA	Reset block
		PLL
	VSSA
		VDD domain	1.8 V domain
	VSS	I/O Ring	Core
(3.3 V)		Standby circuitry	Memories
	VDD	(Wakeup logic,	digital
		IWDG)	peripherals
		Voltage Regulator
		Low voltage detector
		Backup domain
(VDD) VBAT		LSE crystal 32K osc
		BKP registers
		RCC BDCR register
		RTC
			ai14677

1.1.1Independent A/D converter supply and reference voltage

To improve conversion accuracy, the ADC has an independent power supply that can be filtered separately, and shielded from noise on the PCB.

●The ADC voltage supply input is available on a separate VDDA pin

●An isolated supply ground connection is provided on the VSSA pin

When available (depending on package), VREF– must be tied to VSSA.

On 100-pin packages

To ensure a better accuracy on low-voltage inputs, the user can connect a separate external reference voltage ADC input on VREF+. The voltage on VREF+ may range from 2.0 V to VDDA.

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On packages with 64 pins or less

The VREF+ and VREF- pins are not available, they are internally connected to the ADC voltage supply (VDDA) and ground (VSSA).

1.1.2Battery backup

To retain the content of the Backup registers when VDD is turned off, the VBAT pin can be connected to an optional standby voltage supplied by a battery or another source.

The VBAT pin also powers the RTC unit, allowing the RTC to operate even when the main digital supply (VDD) is turned off. Switching to the VBAT supply is controlled by the power

down reset (PDR) circuitry embedded in the Reset block.

If no external battery is used in the application, VBAT must be connected externally to VDD.

1.1.3Voltage regulator

The voltage regulator is always enabled after reset. It works in three different modes depending on the application modes:

●in Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and digital peripherals)

●in Stop mode, the regulator supplies low power to the 1.8 V domain, preserving the contents of the registers and SRAM

●in Standby mode, the regulator is powered off. The contents of the registers and SRAM are lost except for those concerned with the Standby circuitry and the Backup domain.

1.2Low-power modes

By default, the microcontroller is in Run mode after a system or a power Reset. Several lowpower modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources.

The STM32F10xxx devices feature three low-power modes:

●Sleep mode (CPU clock off, all peripherals including Cortex-M3 core peripherals like NVIC, SysTick, etc. are kept running)

●Stop mode (all clocks are stopped)

●Standby mode (1.8V domain powered-off)

In addition, the power consumption in Run mode can be reduce by one of the following means:

●Slowing down the system clocks

●Gating the clocks to the APB and AHB peripherals when they are unused.

Table 1 below summarizes the low-power modes of the STM32F10xxx MCU.

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AN2629						Power supply
	Table 1.	Low-power modes
					Effect on 1.8 V	Effect on	Voltage
	Mode name		Entry	Wakeup		VDD domain
					domain clocks		regulator
						clocks
	Sleep		WFI	Any interrupt	CPU clock OFF
	(Sleep-now				No effect on other	None	ON
	or Sleep-on-		WFE	Wakeup event	clocks or analog
	exit)				clock sources
							ON or in
							low-power
			PDDS and				mode
							(depends
			LPDS bits +	Any EXTI line
							on the
	Stop		SLEEPDEEP	(configured in the EXTI
							Power
			bit + WFI or	registers)		HSI and HSE
					All 1.8 V domain		control
			WFE
						oscillators	register,
					clocks OF
						OFF	PWR_CR
							)
			PDDS bit +	WKUP pin rising edge,
	Standby		SLEEPDEEP	RTC alarm, external			OFF
			bit + WFI or	reset in NRST pin,
			WFE	IWDG reset

1.2.1Slowing down system clocks

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode.

1.2.2Peripheral clock gating

In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption.

To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.

Peripheral clock gating is controlled by the AHB peripheral clock enable register (RCC_AHBENR), the APB1 peripheral clock enable register (RCC_APB1ENR) and the APB2 peripheral clock enable register (RCC_APB2ENR).

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1.2.3Sleep mode

Entering Sleep mode

The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions. Two options are available to select the Sleep mode entry mechanism, depending on the SLEEPONEXIT bit in the Cortex-M3 System Control register:

●Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon as WFI or WFE instruction is executed.

●Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as it exits the lowest priority ISR.

In the Sleep mode, all I/O pins keep the same state as in the Run mode.

Refer to Table 2 and Table 3 for details on how to enter Sleep mode.

Exiting Sleep mode

If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode.

If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as an event occurs. The wakeup event can be generated either by:

●enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex-M3 System Control register. When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

●or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set.

This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit. Refer to Table 2 and Table 3 for more details on how to exit Sleep mode.

Table 2.	Sleep-now
Sleep-now			Description
			WFI (Wait for Interrupt) or WFE (Wait for Event) while:
Mode entry			– SLEEPDEEP = 0 and
			– SLEEPONEXIT = 0
			Refer to the Cortex-M3 System Control register.
Mode exit			If WFI was used for entry ->Interrupt
			If WFE was used for entry ->Wakeup event
Wakeup latency			None.

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	Table 3.	Sleep-on-exit
	Sleep-on-exit		Description

		WFI (wait for interrupt) while:
	Mode entry	SLEEPDEEP = 0 and
		SLEEPONEXIT = 1
		Refer to the Cortex™-M3 System Control register.
	Mode exit	Interrupt.
	Wakeup latency	None.

1.2.4Stop mode

The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. SRAM and register contents are preserved.

In the Stop mode, all I/O pins keep the same state as in the Run mode.

Entering the Stop mode

Refer to Table 4 for details on how to enter the Stop mode.

To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power mode. This is configured by the LPDS bit of the Power control register (PWR_CR).

If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished.

If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB access is finished.

In Stop mode, the following features can be selected by programming individual control bits:

●Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset.

●Real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR)

●Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR).

●External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR).

The ADC or DAC can also consume power during the Stop mode, unless they are disabled before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0.

Exiting the Stop mode

Refer to Table 4 for more details on how to exit the Stop mode.

When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.

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When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.

Table 4.	Stop mode
Stop mode		Description
		WFI (Wait for Interrupt) or WFE (Wait for Event) while:
		– Set SLEEPDEEP bit in Cortex-M3 System Control register
		– Clear PDDS bit in Power Control register (PWR_CR)
Mode entry		– Select the voltage regulator mode by configuring LPDS bit in PWR_CR
		Note: To enter Stop mode, all EXTI Line pending bits (in Pending register
		(EXTI_PR)) and RTC Alarm flag must be reset. Otherwise, the Stop mode entry
		procedure is ignored and program execution continues.
		If WFI was used for entry:
Mode exit		Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt
		vector must be enabled in the NVIC).
		If WFE was used for entry: Any EXTI Line configured in event mode.
Wakeup latency		HSI RC wakeup time + Regulator wakeup time from low-power mode

1.2.5Standby mode

The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry (see Figure 1).

Entering the Standby mode

Refer to Table 5 for more details on how to enter the Standby mode.

In Standby mode, the following features can be selected by programming individual control bits:

●Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset.

●real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR)

●Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR).

●External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR)

Exiting the Standby mode

The microcontroller exits Standby mode when an external Reset (NRST pin), IWDG Reset, a rising edge on WKUP pin or an RTC alarm occurs. All registers are reset after wakeup from Standby except for the Power control/status register (PWR_CSR).

After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Power control/status register (PWR_CSR) indicates that the MCU was in Standby mode.

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Doc ID 13922 Rev 2

AN2629			Power supply
	Table 5.	Standby mode
	Standby mode		Description
			WFI (Wait for Interrupt) or WFE (Wait for Event) while:
			– Set SLEEPDEEP in Cortex-M3 System Control register

Mode entry

–Set PDDS bit in Power Control register (PWR_CR)

–Clear WUF bit in Power Control/Status register (PWR_CSR)

Mode exit

WKUP pin rising edge, RTC alarm, external Reset in NRST pin, IWDG

Reset.

Wakeup latency

Regulator start up + Reset phase

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except:

●Reset pad (still available)

●TAMPER pin if configured for tamper or calibration out

●WKUP pin, if enabled

1.2.6Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex™-M3 core is no longer clocked.

However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively.

1.2.7Auto-wakeup (AWU) from low-power mode

The RTC can be used to wakeup the MCU from low-power mode without depending on an external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR):

●Low-power 32.768 kHz external crystal oscillator (LSE OSC).

This clock source provides a precise time base with very low-power consumption (less than 1µA added consumption in typical conditions)

●Low-power internal RC Oscillator (LSI RC)

This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to add minimum power consumption.

To wakeup from Stop mode with an RTC alarm event, it is necessary to:

●Configure the EXTI Line 17 to be sensitive to rising edge

●Configure the RTC to generate the RTC alarm

To wakeup from Standby mode, there is no need to configure the EXTI Line 17.

Doc ID 13922 Rev 2

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