ST AN2593 Application note

January 2009 Rev 2 1/15

AN2593

Application note

STR91x interrupt management

Introduction

The objective of this application note is to explain the mechanism of the interrupt

management hardware in the STR91x microcontroller family, and also to provide application

developers with software recommendations for interrupt handling.

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Contents AN2593

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1 STR91x vectored interrupt controller VIC . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 VIC architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 VIC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2.1 Interrupt configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.2 FIQ interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2.3 IRQ interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Software recommendations for handling interrupts . . . . . . . . . . . . . . . 7

2.1 Handling FIQ interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Handling IRQ interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3.1 With interrupt nesting support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3.2 Without interrupt nesting support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Daisy-chained vectored interrupt service routine limitation . . . . . . . . 10

3.1 Description of the limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Impact on user applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.3 Daisy-chained interrupt flow sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.4 Workaround using the STR9 firmware library . . . . . . . . . . . . . . . . . . . . . 11

4 Spurious VIC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 Root causes and handling of spurious interrupts . . . . . . . . . . . . . . . . . . . 13

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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1 STR91x vectored interrupt controller VIC

1.1 VIC architecture overview

In the STR91x microcontroller, the Vectored Interrupt Controller VIC is implemented by

daisy-chaining two standard ARM primecells (PL190) VICs.

Figure 1 gives an overview of the hardware connections:

Figure 1. STR91x VIC architecture

As shown in Figure 1, sixteen interrupt lines are connected to each VIC (see datasheet for

information about each interrupt source).

The choice of connecting two VICs in a daisy-chain was made in order to allow vectored

interrupt support for all 32 interrupt lines of the STR91x.

1.2 VIC operation

Figure 2 provides a schematic view of the VIC (single VIC) block diagram:

Figure 2. Overview of the VIC block diagram

VIC0.15

VIC0.0

VIC1.15

VIC1.0

VIC0

VIC1

ARM966

IRQ

FIQ

Daisy

chain

core

Vectored Interrupt 0

Interrupt source 0

Interrupt source 1

Interrupt source 15

Interrupt

Request

Logic

FIQ to CPU

IRQ Priority

IRQ to CPU

Vector Address Register

FIQ Logic

Vectored Interrupt 0 ISR Address

Vectored Interrupt 15

Vectored Interrupt 15 ISR Address

IRQ

FIQ

Logic

FIQ status Register

IRQ status register

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1.2.1 Interrupt configurations

Any interrupt source can be configured as IRQ or as FIQ (Fast Interrupt Request).

IRQ interrupt configuration

In each VIC, an IRQ interrupt can have a priority ranging from 0 to 15 (priority 0 is the

highest priority and 15 is the lowest).

In order to assign a priority level to an IRQ interrupt, using the following procedure:

1. Assign one of the vectored interrupts (from 0 to 15) to the interrupt source by

configuring the selected VIC Vector Control i register VICx_VCiR.

2. Program the address of the interrupt service routine (ISR) in the selected vectored

interrupt Vector Address i register VIC_VAiR.

3. Enable the IRQ interrupt by setting the corresponding bit in the VIC Interrupt Enable

4. Enable the selected vectored interrupt in the VICx_VCiR register.

Caution: Due to the VIC daisy-chained implementation, IRQ interrupts from VIC0 have always higher

priority than VIC1 interrupts (hardwired priority), this means for example that an interrupt

from VIC1 configured with a priority level 0 has a lower priority than a VIC0 interrupt

configured with a priority level 15.

FIQ interrupt configuration

In order to configure a VIC interrupt source as FIQ, you have to set the corresponding bit in

the VIC Interrupt Select register VICx_INTSR, and then enable the interrupt by setting the

corresponding bit in the VIC Interrupt Enable register VICx_INTER.

Note: FIQ interrupts have the highest interrupt priority level. Unlike IRQ interrupts, FIQ interrupts

have no vectored interrupt support or priority management.

Ta bl e 1 summarizes the interrupt priority levels in the VICs:

Table 1. Summary of the interrupt priorities in the VICs

Interrupt Configured priority level in the VICs Priority

VIC0/VIC1 FIQ NA

VIC0 IRQ

...

VIC1 IRQ

...

Highest

Lowest

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1.2.2 FIQ interrupt management

For FIQ there are no priority levels. When an enabled FIQ interrupt occurs, the VIC signals it

directly to the ARM core by asserting the FIQ interrupt line.

Then the ARM core switches to FIQ mode, and goes to address 0x1C where you must

implement the FIQ interrupt handler.

Normally in order to lower FIQ interrupt latency only one interrupt should be configured as

FIQ. But it is possible to configure several interrupts as FIQ, and in this case the application

software must read the FIQ status registers of both VIC0 and VIC1 in order to determine the

source of the FIQ interrupt.

When the interrupt flag is cleared in the peripheral(s) that generated the interrupt, the VIC

then will stop asserting the FIQ interrupt to CPU and the flag will be cleared in the VIC FIQ

status register.

1.2.3 IRQ interrupt management

There are two possible ways for handling IRQ interrupts in the VIC:

1. Vectored handling

2. Simple (Non vectored) handling

Vectored handling ensures the best interrupt latency because it takes advantage of the

vectored support in the VIC.

Simple handling does not use the hardware priority management of the VIC, but it uses a

software priority management. Although this method increases the interrupt latency, it can

be useful in special cases where a VIC1 interrupt has to be configured with a higher priority

level than a VIC0 interrupt, this is not possible when using the hardware priority

management due to the hardwired priority between VIC0 and VIC1 (see Section 1.2.1).

Vectored handling of IRQ interrupts

When an IRQ interrupt from VIC0 or from VIC1 occurs, then depending on its priority level,

two cases are possible:

– If the interrupt has a lower priority than the current interrupt being processed, then it

remains pending in the VIC until it becomes the higher priority interrupt.

– If the interrupt has the highest priority level then the VIC0 Vector Address register

VIC0_VAR will be loaded with the address of the interrupt service routine and an IRQ

interrupt will be signalled to CPU.

Note: The VIC0_VAR will be loaded with the ISR address of the interrupt independently from the

origin of the interrupt either from VIC0 or from VIC1.

The vectored flow for handling an IRQ interrupt is the following:

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