ST AN2592 Application note
AN2592
Application note
How to achieve 32-bit timer resolution using the link system
in STM32F10x microcontrollers
Introduction
In many applications, 32-bit resolution is required to measure external signal periods of up
to several hundreds of seconds or, to generate delays or periodic signals with large periods.
The STM32F10x microcontrollers offer the possibility of chaining two 16-bit timers to obtain
a 32-bit resolution based on a specific configuration of the timers and on the use of the timer
link system.
This application note gives general guidelines to emulate a 32-bit timer. The two basic
operating modes, that is the input capture mode and the output compare mode, are
presented. Each mode is treated independently and, each time, examples of applications
are provided.
January 2011 Doc ID 13711 Rev 2 1/17
www.st.com
Contents AN2592
Contents
1 STM32F10x timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Timer link system presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 How to synchronize two timers using the link system . . . . . . . . . . . . . . . . 5
2 32-bit input capture timer resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.1 TIM3 master configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2 TIM2 slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.3 Master and slave synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 32-bit output compare timer resolution . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Principle and timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Output compare mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 Output compare active mode example . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.2 Output compare toggle mode example . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17 Doc ID 13711 Rev 2
AN2592 List of tables
List of tables
Table 1. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Doc ID 13711 Rev 2 3/17
List of figures AN2592
List of figures
Figure 1. Simplified TIM2 trigger controller block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Timer synchronization in input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Timer synchronization in output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. TIM2 output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. TIM2 output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. TIM2 Channel1 output signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4/17 Doc ID 13711 Rev 2
AN2592 STM32F10x timer synchronization
TIMxCLK
ETR
TRG01
TRG03
TRG04
ITR0
ITR2
ITR3
TIM2
Trigger
controller
TRG0 TRG02
TI1FP1
TI2FP2
ai14603
1 STM32F10x timer synchronization
1.1 Timer link system presentation
In the STM32F10x microcontrollers, the embedded timers can be linked together for timer
synchronization or chaining purposes.
Using the timer link system, a timer configured in Master mode can:
● reset the counter of the slave timer
● start and/or stop the slave timer counter
● clock the slave timer counter
1.2 How to synchronize two timers using the link system
In addition to the TIMx_CHx pins, timers have several internal triggers that are
indispensable for linking and chaining operation.
Figure 1 shows a simplified representation of the timer block, that highlights the internal
triggers. TIM2 is used as an example.
Figure 1. Simplified TIM2 trigger controller block
The internal triggers (ITR0, ITR2 and ITR3) are used when TIM2 is configured in the Slave
mode. They then determine which master controls TIM2.
Doc ID 13711 Rev 2 5/17
STM32F10x timer synchronization AN2592
For example, if TIM2 uses ITR2 as an internal trigger, this means that TIM2 is synchronized
with TIM3.
These triggers can be easily redirected to the master by setting the right combination of TS
bits in the SMCR register.
The trigger output, TRGO, is used when TIM2 is configured in the Master mode. It then
determines which events or signals is sent to the slave timers for synchronization.
Different events or signals can be transmitted to the slave, as listed below. They are selected
using the MMS bits in the CR2 register.
● reset event
● enable event
● update event
● compare pulse
● OCxREF where x is 1, 2, 3 or 4.
Once the master trigger output, TRGO, and the slave’s internal triggers, ITRx, are
configured, the two timers are chained.
There are four different slave modes that are selected using the SMS bits in the SMCR
register. They are the following:
● Reset mode: in this mode, the rising edge of the trigger signal reinitializes the counter
and generates an update of the registers.
● Gated mode: the slave counter start and stop are both controlled by the high level on
the trigger input.
● Trigger mode: the start of the slave counter is controlled by the rising edge of the trigger
input signal.
● External clock mode1: the slave counter is clocked by the rising edges of the selected
trigger input signal.
6/17 Doc ID 13711 Rev 2
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