ST AN2559 Application note

AN2559

Application note

System power supply board for digital solutions

Introduction

This document describes a power supply reference board designed for powering digital applications, such as CPUs, FPGAs, memories, etc. The main purpose of the board is to illustrate the basic principles used for the design of the power supply and to give designers a usable prototype for testing and use.

The trend in recent years in the supplying of power to MCUs, CPUs, memories, FPGAs, etc. is to reduce the supply voltage, increase the supply current and provide different voltage levels for different devices in one platform. A typical example of this situation is the FPGA. The FPGA contains a core part which works at a low level voltage, the interface part placed between the core and the output, the system part, etc. It is important to note that each FPGA family has a slightly different voltage level and the trend is to decrease the voltage for each new family. The lowest operating voltage currently available is 1 V, and this can be expected to decrease to 0.9 V or 0.8 V in the near future. A similar situation exists with other digital applications. Typically, the main CPU, memory and interfaces require different supply voltage levels. Low operating voltages also present another challenge - transient. Digital devices are typically sensitive to voltage level. If the voltage drops below or crosses over a specific limit, the device is reset. This limit is typically ± 3 or ± 5%. On the other hand, digital device consumption can change very quickly (several amps in a few hundred nanoseconds). A power supply must be able to react very quickly with a minimum of over (or under) voltage, especially in cases where very low output voltage is required. There is additional stress placed on power supplies for digital applications in the industrial environment.

The industrial standard bus is 24 V, but this voltage fluctuates and the maximum input voltage level required can reach 36 V. Additional surge protection is also a mandatory part of power supply input for industrial applications.

The goal of the board described in this application note is to cover all of the issues outlined above. It is intended mainly to satisfy industrial input requirements (operating voltages up to 36 V) and generate several output voltages for mid-range power applications (up to several amps). The main output voltage level can simply be set.

September 2007 Rev 1 1/35

www.st.com

Contents AN2559

Contents

1 Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Input part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 PM6680A block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.0.1 Power management block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.0.2 Start-up/enable block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.0.3 Step-down parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 DC-DC converters based on the L5970AD . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1 PM6680A block - measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1.1 Efficiency and light load consumption modes . . . . . . . . . . . . . . . . . . . . 23

6.1.2 Output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1.3 Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.4 Transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.2 L5970AD blocks - measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2.1 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2.2 Output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2.3 Transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2/35

AN2559 List of figures

List of figures

Figure 1. The STEVAL-PSQ001V1 demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Block diagram of System Supply board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Schematic of input part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. Location and correct polarity of the input supply connector on the board . . . . . . . . . . . . . . 6

Figure 5. Electrical diagram of the PM6680A section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. The placement of the jumpers for start-up/enable settings. . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. Skip mode connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 8. Output connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 9. Jumper placement for V Figure 10. Jumper placement for V

Figure 11. Output voltages of L5970A parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 12. Schematic of the two SMPS’s based on the L5970AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 13. Jumper placement for enable/disable function of analog output and output3 . . . . . . . . . . 16

Figure 14. Schematic of the reset circuit and board placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 15. PCB top layer layout and first internal layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 16. PCB second internal layer and bottom layer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 17. Efficiency of the dual step-down converter at full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 18. PM6680A consumption at no load condition, in the different modes . . . . . . . . . . . . . . . . . 24

Figure 19. Output voltage ripple in different modes of light load operation . . . . . . . . . . . . . . . . . . . . . 24

Figure 20. Output voltage ripple of V Figure 21. Output voltage ripple of V Figure 22. Output voltage ripple of V Figure 23. Output voltage ripple of V

Figure 24. Start-up without setting the sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 25. Start-up with a set sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 26. Load transient response on V Figure 27. Load transient response on V

Figure 28. Efficiency of output 3, by input voltage level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 29. Efficiency of analog output, by input voltage level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 30. Analog 5 V - output voltage ripple. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 31. V

- output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

SYS

Figure 32. Analog 3.3 V - output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 33. V

2.5 V - output voltage ripple. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

AUX

Figure 34. Transient response of V Figure 35. Transient response of V

voltage level setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CORE

voltage level setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

I/O

at the minimum input voltage (5 V) . . . . . . . . . . . . . . . . . . 25

CORE

at the maximum output voltage (36 V) . . . . . . . . . . . . . . . 25

CORE

at the minimum input voltage (5 V) . . . . . . . . . . . . . . . . . . . . 25

I/O

at the maximum input voltage (36 V). . . . . . . . . . . . . . . . . . . 26

I/O

output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

CORE

output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

I/O

based on the L5970AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SYS

generated by the LDO KF25 . . . . . . . . . . . . . . . . . . . . . . . . . 33

AUX

3/35

Main characteristics AN2559

1 Main characteristics

The main characteristics of the SMPS are listed below:

● Input: 5 V - 36 V DC, surge protection

● Outputs: the performance of the 6 outputs are described in Tab le 1 below.

Table 1. Output voltages (positive version)

Label V

Output1 (V

) Selectable from:

CORE

0.9, 1.0, 1.2, 1.5, 1.8 or 2.5 V

Output2 (V

) Selectable from:

I/O

1.0, 1.2, 1.5, 1.8, 2.5 V or 3.3 V

Output3 V

SYS

AUX

3.3 V 0.4 A (0.8 A peak) 4%

2.5 V 0.4 A 2%

OUT

4 A continuous 6 A peak

2 A continuous 3 A peak

max Tolerance

OUT

Analog 5 V 5 V 0.8 A 4%

Analog 3.3 V 3.3 V 0.15 A 2%

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AN2559 Description

2 Description

The System Supply board described in this application note is a dedicated design which illustrates a typical solution for complete system supply, and can also be used as a direct supply for customer solutions during the design process.

Figure 1. The STEVAL-PSQ001V1 demo board

The block diagram of the System Supply board is shown in Figure 2. There are four DC-DC converters, two linear regulators and a reset circuit. These parts are split into five relatively independent units: the input part, a dual DC-DC converter based on the PM6680A and generating 2 outputs (Output 1 and Output 2), two single DC-DC converters based on the L5970A (Output 3 and Output 4) with linear regulator, and the reset circuit.

Figure 2. Block diagram of System Supply board

Reset signal

Analog 5 V analog 500 mA

3.3 V analog 150 mA

Output 3 V

3.3 V 400 mA

sys

2.5 V 400 mA

aux

Output 2 V

1.0 - 3.3 V 2 A

i/o

voltage settings

i/o

Output 1 V

0.9 - 2.5 V 4 A

core

voltage settings

core

AI12693

Input 5 - 36 V

Input

protection

Skip mode settings

PM6680A

core

Vi/o

E/D + start up sequence settings

E/D analog

L5970AD

E/D V

FB V

sys

i/o

core

STM6719

LK112

M33

KF25

+ V

aux

5/35

Description AN2559

2.1 Input part

The input part shown in Figure 3 consists of the input connectors (industrial - J16 or power jack - J3), input storage capacitor (C1) and transil (D1). The input electrolytic capacitor and transil serve to reduce input voltage spikes (surge).

Figure 3. Schematic of input part

Vin

J16

Figure 4 displays the placement of the input connectors on the board. The board can be

supplied either from the jack connector (J3) or the industrial removable terminal plate (J16). The polarity of the input voltage must be correctly applied in accordance with the illustration in Figure 4. If the connection is made incorrectly, the input protection D1 shorts the input voltage. It should be pointed out that the total input current is about 4 A at maximum output power and minimum input voltage.

1 2 3

D1 SM6T39AC147 µF / 50 V

AI12691

Figure 4. Location and correct polarity of the input supply connector on the board

6/35

AN2559 PM6680A block

3 PM6680A block

Figure 5. Electrical diagram of the PM6680A section

core

S13

1 V

S14

1.2 V

S15

1.5 V

S16

1.8 V

S17

2.5 V

R206

6.8 kΩ R205 200R

C29

330 µF /

6.3 V

C24

4.7µF / 50 V / X7R

C34 12 nF

R38 3.3 kΩ

L4 3.8 µH / 6 A

C23

R2762 kΩ

4.7µF / 50 V / X7R

Vin

SHDN

STS7NF60L

D10

4V7

51 kΩ

R29

C17

100 nF

C16

3.3 Ω

Vin

VLDO

3.3 µF / 35 V

C15

470 nF

C14

4.7 µF / 10 V

C25

100nF

BAW56/SOT

R37 47R

Vin

R210R

R26

10R

BOOT1

Vin

LDO5

BOOT2

R25

10R

C31

220 nF

R230R

100 nF

C19

STS4DNF60

C18

4.7 µF / 50 V/X7R

C41

4.7 µF / 50 V/X7R

STPS1L40

STS7NF60L

R220R

R19 1 kΩ

PGND

LGATE1

HGATE122PHASE1

CSENSE1

HGATE210PHASE211LGATE213CSENSE212V5SW17OUT28COMP22PGOOD227FB27SHDN

R240R

R10 1.8 kΩ

138

STPS1L40

R40100 kΩ

L3 5.0 µH / 3 A

C35 10 nF

R39 3.3 kΩ

R110

4.7 kΩ R105

2.5 V R109 3.3 kΩ

S12

1.8 V

S11

1.5 V

S10

1.2 V

1 V

R208

820 kΩ

R201

1 kΩ

2 kΩ

9.1 kΩ

R202

R207

R203

3 kΩ

R204

3 kΩ

22 µF / 6.3 V

C40

330 µF / 6.3 V

C28

R20 680R

C27

C26 2.2 nF

OUT1

R11 560R

200R

120 pF

VLDO

R3210 kΩ

VLDO

FB1

COMP1

R28 10 kΩ

VLDO

C20 1.8 nF

C22

330 µF / 6.3 V

C39

22 µF / 6.3 V

R104

R106

R103

R102

R101

SGND11SGND2

PGOOD1

3 kΩ

6.8 kΩ

3 kΩ

2 kΩ

1 kΩ

FSEL

SKIP

VREF

EN1

EN2

SHDN

PM6680

VLDO

C21

91 pF

R108

820 kΩ

R107

9.1 kΩ

C30

100 nF

SKIP mode

R36

51 kΩ

CH1 EN/SUS

R35

51 kΩ

CH2 EN/SUS

R31 10 kΩ

R3410 kΩ

AI14512

7/35

PM6680A block AN2559

The PM6680A block is most important part of board. It contains two DC-DC converters. Each output has a selectable output voltage level. The first converter is capable of delivering up to 4 A for each voltage level, while the second converter can deliver up to 2 A on the output.

Both converters are controlled by the PM6680A device. The PM6680A is a dual step-down controller specifically designed to provide extremely high efficiency conversion, with lossless current sensing. The constant on-time architecture assures fast load transient response and the embedded voltage feed-forward provides nearly constant switching frequency operation. An embedded integrator control loop compensates the DC voltage error due to the output ripple. The pulse skipping technique increases efficiency at very light loads. Moreover, a minimum switching frequency of 33 kHz is selectable to avoid audio noise issues. The PM6680A provides a selectable switching frequency, allowing either 200 / 300 kHz, 300 / 400 kHz or 400 / 500 kHz operation of the two switching sections. The output voltages OUT1 and OUT2 can be adjusted from 0.9 V to 5 V and from 0.9 V to 3.3 V, respectively. A detailed description of this device can be found in the datasheet.

Figure 5 shows the full electrical diagram of the block with the PM6680A that controls the

two DC-DC converters. The components around the PM6680A form several functional blocks: the power management block, V

step down block, V

CORE

step down block and

I/O

start-up/enable control system block.

3.0.1 Power management block

The PM6680A has two supply voltage inputs - VCC and VIN. The VCC pin should be connected to the 5 V bus (maximum input voltage is 6 V, minimum 4.5 V) and it is dedicated for the supply of the chip itself. The V it is used inside the chip for two reasons. The first is to supply the integrated LDO. The second is the fact that the controller must sense the converter input voltage level for proper functioning of the converter.

The V

pin is supplied from the integrated LDO (connected output of LDO and VCC) on the

reference board. The V5SW feature of the LDO is disabled.

The power management block consists of components C14 - C17, C31, R9, R29, R37 and D10. The important parts of the power management block of the device are the low pass filters (R9, C16, C17 and R37, C31) applied to reduce the influence of transience on the device V

and VIN main power inputs. The resistor R29 and the diode D10 generate the

SHDN (shut down) signal, which is active in low level. This signal activates the PM6680A immediately after V

is connected to the input. The V

simultaneously with activation of the SHDN pin.

3.0.2 Start-up/enable block

The PM6680A has several inputs and outputs dedicated to the control of each channel. Each channel has an independent Enable signal (EN - active in high level) and "power good" signal (PGOOD - open collector) activated by channel in cases where the output voltage is within 10% tolerance. These control pins can be used either for simple enabling/disabling or for delaying the start-up of one channel rather than another.

pin should be connected to the input power bus and

and LDO signals start to work

REF

The jumpers S3 and S4 with resistors R28, R31, R32, R34, R35 and R36 are used for systems independently allowing either enabling or disabling of each channel or setting up a different start-up sequence of both channels. Figure 6 displays the placement of jumpers S3 and S4 on the board, and the settings are shown in Ta b le 2 .

8/35

AN2559 PM6680A block

Figure 6. The placement of the jumpers for start-up/enable settings

Table 2. Start-up/enable jumper settings

Jumper settings Function

Vi/o

1st

Vi/o

Vcore

1st

Both channels are disabled. An open connector for each channel means

that the channel is disabled.

core

1st

Vi/o

1st

core

1st

Both channels are disabled.

Both channels are enabled and start at same time.

core

1st

Vi/o

core

1st

Vi/o

voltage starts first, and V

CORE

voltage starts first, and V

I/O

starts second.

I/O

starts second.

CORE

The Skip mode connector (shown in the schematic as S5 - S7) is dedicated for the control of Skip mode. This connector setting is common for both channels. Figure 7 shows the placement of the Skip mode connector, while the settings are shown in Tabl e 3 . There are three possible settings. Standard Skip mode, No Audible mode or PWM mode. In Standard Skip mode the converter reduces the switching frequency at light load to maintain good efficiency even in this condition. There is no lower limit for switching frequency. In No Audible mode the converter reduces switching frequency at light load, but this frequency never drops below 30 kHz to avoid possible audible noise caused by the mechanical

9/35

PM6680A block AN2559

construction of passive components (inductors or ceramic capacitors). In PWM mode the converter maintains a constant switching frequency independently on the load.

The FSEL pin the PM6680A dedicated for operating frequency setting is connected to GND. This means that the switching frequency of the V frequency of V

is 300 kHz.

I/O

branch is 200 kHz and switching

CORE

Figure 7. Skip mode connector

Table 3. Skip mode connector jumper settings

Jumper settings Function

Audio

Skip PWM

Audio

Skip PWM

Audio

Skip PWM

3.0.3 Step-down parts

The PM6680A is a dual step-down controller and drives two step-down converters. The schematic of both channels are almost identical, with only a few small differences. Since each channel is for a different output power, the main difference is in the components’ values. Figure 8 displays the output connector polarities of the PM6680A section.

Skip mode at light load.

No Audible Skip mode at light load (frequency never drops below 30 kHz).

PWM mode. Constant frequency even at light or zero load.

10/35

AN2559 PM6680A block

Figure 8. Output connector

The power components of the step-down part are input capacitors (C23, C24 or C18, C41), the half bridge driver containing two N-channel MOSFETs (Q2, Q3 or Q1), inductors (L4 or L3) and output capacitors (C28, C29, C40 or C22, C39).

Ceramic high-capacitance capacitors are used as input capacitors. 60 V MOSFETs are used for the half bridge driver. A relatively high breakdown voltage is used to guarantee operation in industrial applications. Because the V

output is designed for lower currents

I/O

(2 A), both MOSFETs are integrated in one SO-8 package (Q1 - STS4NF60). This helps to reduce the size on the PCB. Two discrete MOSFETs (STS7NF60) are used for the V

CORE

higher power output (4 A). Schottky diodes are also used in each channel (D9 or D8). These diodes work mainly during dead time and are not mandatory for proper functioning, but their application increases efficiency.

The 5 µH inductor (L3) is used for the V

output with saturation current at 3 A. The inductor

I/O

L4 has value of 3.8 µH with saturation current at 6 A.

A combination of tantalum low ESR and ceramic type are used as output capacitors. Ceramic capacitors help to reduce total output ESR and reduce total output voltage ripple.

The PM6680A includes a half bridge driver for each channel. The external bootstrap diode and capacitor must be applied (D7, C19 or C25) in order to drive the gates of the high side MOSFETs.

The feedback signal is generated by the output voltage divider (R10x or R20x). The board allows the setting of different output voltages for both channels. Figure 9 and Figure 10 display the output voltage connector placement on the board for each channel. The jumper settings are shown in Tabl e 4 and Tab l e 5, respectively.

In classic Constant On Time control, the system regulates the valley value of the output voltage and not the average value. In this condition, the output voltage ripple is a source of DC static error. To compensate for this error, an integrator network is introduced in the control loop by connecting the signal output voltage to the COMP1/COMP2 pin through a capacitor (C20 or C26). An additional R-C network (R11 and C21 or R20 and C27) is implemented as a low pass filter to reduce noise on the input of the COMP pin.

Since the feedback signal of the SMPS working in Constant On Time control is directly connected to the PWM comparator, the stability of the SMPS is more sensitive to noise injected into the FB signal. It is possible to attenuate the affect of the noise to stabilize the SMPS by implementing the so called "Virtual ESR" network, which increases the amplitude of the feedback ripple voltage and improves signal-to-noise ratio. The Virtual ESR network does not increase the output ripple voltage. It is recommended to use the Virtual ESR network in cases where the output voltage ripple is below 30 mV. However, it is necessary to

11/35

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