ST AN2556 Application note

AN2556

Application note

Porting an application from the ST10F269Zx to the ST10F273Z4

Introduction

The ST10F273Z4 is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers and is functionally upwardly compatible with the ST10F269Zx.

The goal of this document is to highlight the differences between the ST10F269Zx and the ST10F273Z4 devices. It is intended for hardware or software designers who are adapting an existing application based on the ST10F269Zx to the ST10F273Z4.

This document first presents the modified functionalities of the ST10F273Z4, and then presents the new functionalities before looking at the modified and the new registers. In each section of the document, differences with the ST10F269Zx that may have an impact are stressed and some advice is given on how best to handle these differences and impacts.

July 2007 Rev 1 1/35

www.st.com

Table of contents AN2556

Table of contents

1 Modified features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1.1 Pinout modification summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1.2 Pin 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1.3 Pin 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.4 Pin 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.5 Pins 143 and 144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4.1 Hardware/software impacts: conversion timing control . . . . . . . . . . . . . 10

1.4.2 Hardware impacts: electrical characteristics . . . . . . . . . . . . . . . . . . . . . 11

1.4.3 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.5 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.5.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.5.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.6 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.6.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.6.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.7 Ports input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.7.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.7.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.8 Ports output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.8.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.8.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.9 PLL and on-chip main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.9.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.9.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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AN2556 Table of contents

2 New features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1 Additional XPeripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.2 Programmable divider on CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.2.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3 New multiplexer for X-Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.4 Additional ports input control: XPICON register . . . . . . . . . . . . . . . . . . . . 23

2.4.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.4.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3 Modified registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1 XPERCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4 New registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1 XADRS3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2 XPEREMU register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.3 Emulation dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.4 XMISC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.4.1 Hardware impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.4.2 Software impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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Table of contents AN2556

5.1.2 Overview of the DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2 AC characteristics at 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2.1 External memory bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2.2 Hi-speed synchronous serial interface (SSC) . . . . . . . . . . . . . . . . . . . . 33

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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AN2556 Modified features

1 Modified features

1.1 Pinout

1.1.1 Pinout modification summary

Ta bl e 1 below summarizes the modifications made in the pinout.

Table 1. Pinout modifications table

Pin No.

17 DC2

56 DC1

99 EA

143 V

144 V

Name Function Name Function

1.1.2 Pin 17

ST10F269Zx ST10F273Z4

Internal voltage regulator decoupling. Connect to nearest V capacitor.

Internal voltage regulator decoupling. Connect to nearest VSS via a 330nF capacitor.

Selects code execution out of internal Flash or external memory according to level during reset

Ground pin XTAL3

5V power supply pin XTAL4

via a 330nF

EA-V

5V power supply pin

Internal voltage regulator decoupling. Connect to nearest V

capacitor.

Selects code execution out of internal Flash or external memory according to

STBY

level during reset. Power supply input for standby mode.

Input to the 32 kHz oscillator amplifier circuit. If not used should be tied to ground to avoid consumption. In addition, bit OFF32 in RTCCON register should be set.

Output of the 32 kHz oscillator amplifier circuit. If not used should be left open to avoid spurious consumption.

via a 10 - 100nF

In the ST10F269Zx, a decoupling capacitor of 330nF minimum has to be connected between pin 17 (named DC2) and the nearest V

This is no longer the case in the ST10F273Z4 device where pin 17 is a V

pin.

Hardware impacts

PCB must be adapted.

Software impacts

None.

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Modified features AN2556

1.1.3 Pin 56

In the ST10F269Zx, a decoupling capacitor of 330nF minimum has to be connected between pin 56 (named DC1) and the nearest V

In the ST10F273Z4, pin 56 is named V

and a capacitor with a value between 10nF

minimum and 100nF maximum must be connected between it and the nearest V

pin.

Hardware impacts

The capacitor value may need to be changed. As the value is much lower, the footprint of the capacitor might be smaller and thus a modification of the PCB may be needed.

Software impacts

None.

1.1.4 Pin 99

In the ST10F269Zx, pin 99 is named EA and when it is reset it is used to select the start from internal Flash or external memory.

Pin 99 now has an additional function in the ST10F273Z4 which is to provide the 5V power supply to the device in standby mode (new power saving mode). It is therefore named EA V

STBY

Hardware impacts

Modification depends on the previous use of the ST10F269Zx and on the use or non-use of Standby mode.

For an application that does not use Standby mode, no change is required on the PCB. If the new application uses the Standby mode, the EA common 5V and have a specific supply path.

Software impacts

None.

1.1.5 Pins 143 and 144

These pins are a VSS-VDD pair in the ST10F269Zx. In the ST10F273Z4, they are now used as an XTAL3-XTAL4 pair for connection to an optional 32 kHz crystal to clock the Real Time Clock during Power-Down.

Hardware impacts

The PCB must be redesigned.

In case the optional 32 kHz is not used:

● XTAL3 must be linked to Ground as was previously the case for ST10F269Zx.

● XTAL4 can be left open or it may be connected to Ground via a capacitor to reduce the

potential effect of RF noise which could be propagated inside the device if it is left floating.

-V

pin must be separated from the

STBY

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AN2556 Modified features

Software impacts

If the optional 32 kHz is not used, but the RTC is used, bit OFF32 of the RTCCON register should be set. Prior to setting the OFF32 bit in RTCCON register, the RTC must be enabled by setting RTCEN, bit 4 of XPERCON, and XPEN, bit 2 of SYSCON.

1.2 XRAM

The XRAM of the ST10F269Zx and ST10F273Z4 devices is not the same size. Each configuration is detailed below.

The ST10F269Zx has 10 Kbytes of extension RAM whereas the ST10F273Z4 has 34 Kbytes.

The XRAM of the ST10F269Zx is divided into two ranges, namely, XRAM1 with 2 Kbytes and XRAM2 with 8 Kbytes:

● The XRAM1 address range is 00’E000h - 00’E7FFh if enabled.

● The XRAM2 address range is 00’C000h - 00’DFFFh if enabled.

The XRAM of the ST10F273Z4 is divided into two ranges, namely, XRAM1 with 2 Kbytes (compatible with the ST10F269Zx) and XRAM2 with 32 Kbytes (which has a user reprogrammable address range):

● The XRAM1 address range is 00’E000h - 00’E7FFh if enabled (XPEN set - bit 2 of

SYSCON register - AND XRAM1EN set - bit 2 of XPERCON register).

● The XRAM2 address range is 0F’0000h - 0F’7FFFh, by default (compatible with

ST10F273Z4 superset) if enabled (XPEN set - bit 2 of SYSCON register - AND XRAM2EN set - bit 3 of XPERCON register).

1.2.1 Hardware impacts

None.

1.2.2 Software impacts

There is no change when enabling the XRAM blocks: The XPERCON register is still used to enable them via the XRAM1EN and XRAM2EN bits and the XPEN bit of SYSCON.

In the ST10 F273Z4 the memory mapping of the application is impacted by the difference in XRAM size and by the location of XRAM2 in segment 15. In the ST10F269Zx the whole XRAM is in page 3 of segment 0.

Variables and PEC transfers

For architectural reasons, the PEC destination and source pointers must be in segment 0. Therefore all RAM variables and arrays that will be PEC addressed must be located within either the DPRAM (00’F600h - 00’FDFFh) or the XRAM1 (00’E000h - 00’E7FFh).

About Toolchain memory model

A change in the Toolchain configuration is needed to take into account the new location of XRAM2. In the ST10F269Zx, all the XRAM is in page 3 which is then automatically addressed using DPP3 that points to page 3 (in order to access the DPRAM and the SFR/ESFR). In the ST10F273Z4, it is necessary to dedicate a DPP to access some of the XRAM2.

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Modified features AN2556

Example in case of Small Memory Model with Tasking toolchain:

The Small Memory Model allows a total code size from 16 Mbytes up to 64 Kbytes of fast accessible 'normal user data' in three different memory configurations with the possibility to access more data, if more than 64 Kbytes of data is needed.

The three memory configurations possible for this 64K of 'normal user data' are:

● Default

Four DPP registers are assumed to contain their system startup value (0-3), providing one linear data area of 64 Kbytes in the first segment (00’0000h - 00’FFFFh).

● Linear Address

DPP3 contains page number 3, allowing access to SYSTEM (extended) SFR registers and a bit-addressable memory. DPP0 - DPP2 provides a linear data area of 48 Kbytes anywhere in the memory.

● Paged

DPP3 contains page number 3, allowing access to SYSTEM (extended) SFR registers and a bit-addressable memory. DPP0, DPP1 and DPP2 contain a page number of a data area of 16 Kbytes anywhere in the memory.

The Default configuration can no longer be used. The other configurations offer the following possibilities:

● Using Linear Address configuration, nearly all the XRAM2 block is covered with DPPs

but then access to constants must be made via EXTP instructions.

● Paged configuration allows the user to assign up to two DPPs to XRAM2 and one DPP

for constants.

1.3 Flash EEPROM

Table 2. Flash memories key characteristics

Characteristic ST10F269Zx ST10F273Z4

Flash size 256 Kbytes 512 Kbytes

Flash organization 7 blocks 10 blocks

Programming voltage 5 volts 5 volts

Programming method Write/Erase Controller Write/Erase Controller

Program/Erase cycles 100000 100000

Table 3: Flash memories mapping on page 9 shows the differences between the

ST10F273Z4 and the ST10F269Zx.

1.3.1 Hardware impacts

None.

1.3.2 Software impacts

Mapping of the applications is impacted because in the ST10F273Z4 the first 32 Kbytes of Flash are divided into four sectors of 8 Kbytes each, whereas the ST10F269Zx has only three sectors.

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AN2556 Modified features

Moreover, the Flash Write/Erase controller is different and therefore the programming routines must be updated.

When the XPEN bit of the SYSCON register and the XRAM2EN bit of XPERCON register are set, access to the address range 09’0000h - 0D’FFFFh is not redirected to the external memory. The linker-locator configuration of the toolchain should be checked in order to prevent use of this memory range.

Note: This range can be redirected to the external memory by changing the value of the register

XADRS3. Refer to Section 4.1: XADRS3 register for more details.

Table 3. Flash memories mapping

Segment

number

14 0E’0000 - 0E’FFFF

8 08’0000 - 08’FFFF IBank 1, Block 1: 64 Kbytes

7 07’0000 - 07’FFFF IBank 1, Block 0: 64 Kbytes

6 06’0000 - 06’FFFF IBank 0, Block 9: 64 Kbytes

5 05’0000 - 05’FFFF IBank 0, Block 8: 64 Kbytes

4 04’0000 - 04’FFFF Block 6: 64 Kbytes 04’0000 - 04’FFFF IBank 0, Block 7: 64 Kbytes

3 03’0000 - 03’FFFF Block 5: 64 Kbytes 03’0000 - 03’FFFF IBank 0, Block 6: 64 Kbytes

2 02’0000 - 02’FFFF Block 4: 64 Kbytes 02’0000 - 02’FFFF IBank 0, Block 5: 64 Kbytes

ST10F269Zx Flash mapping ST10F273Z4 Flash mapping

0E’0000 - 0E’FFFF Flash registers

09’0000 - 0D’FFFF Reserved

05’0000 - 0D’FFFF

01’8000 - 01’FFFF Block 3: 32 Kbytes 01’8000 - 01’FFFF IBank 0, Block 4: 32 Kbytes

01’0000 - 01’7FFF External memory 01’0000 - 01’7FFF External memory

00’8000 - 00’FFFF

External memory

Internal RAM

00’8000 -00’FFFF

External memory

Internal RAM

00’6000 - 00’7FFF Block 2: 8 Kbytes 00’6000 - 00’7FFF IBank 0, Block 3: 8 Kbytes

00’4000 - 00’5FFF Block 1: 8 Kbytes 00’4000 - 00’5FFF IBank 0, Block 2: 8 Kbytes

00’0000 - 00’3FFF Block 0: 16 Kbytes

1.4 A/D converter

The Analog Digital converter has been redesigned in the ST10F273Z4. The ST10F273Z4 still provides an Analog/Digital converter with 10-bit resolution and a sample & hold circuit on-chip.

00’2000 - 00’3FFF IBank 0, Block 1: 8 Kbytes

00’0000 - 00’1FFF IBank 0, Block 0: 8 Kbytes

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Modified features AN2556

1.4.1 Hardware/software impacts: conversion timing control

The A/D Converter is not fully compatible with the ST10F269Zx (timing and programming model). In the ST10F269Zx, the sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry. The total conversion time is compatible with the formula used for the ST10F269Zx, but the meaning of the field bits ADCTC and ADSTC are no longer compatible

Table 4. ST10F273Z4 conversion timing table

ADCTC ADSTC Sample Comparison Extra Total conversion

00 00 TCL * 120 TCL * 240 TCL * 28 TCL * 388

00 01 TCL * 140 TCL * 280 TCL * 16 TCL * 436

00 10 TCL * 200 TCL * 280 TCL * 52 TCL * 532

00 11 TCL * 400 TCL * 280 TCL * 44 TCL * 724

11 00 TCL * 240 TCL * 120 TCL * 52 TCL * 772

11 01 TCL * 280 TCL * 560 TCL * 28 TCL * 868

11 10 TCL * 400 TCL * 560 TCL * 100 TCL * 1060

11 11 TCL * 800 TCL * 560 TCL * 52 TCL * 1444

10 00 TCL * 480 TCL * 960 TCL * 100 TCL * 1540

10 01 TCL * 560 TCL * 1120 TCL * 52 TCL * 1732

10 10 TCL * 800 TCL * 1120 TCL * 196 TCL * 2116

10 11 TCL * 1600 TCL * 1120 TCL * 164 TCL * 2884

The user should take care of the sample time parameter: This is the time where the capacitances of the converter are loaded via the respective analog input pin. Tab le 5 : ST10F273Z4 vs. ST10F269Zx sample time comparison table shows the differences in sample time.

Table 5. ST10F273Z4 vs. ST10F269Zx sample time comparison table

ADCTC ADSTC

00 00 TCL * 48 TCL * 120 2.5 00

00 01 TCL * 96 TCL * 140 1.46 00

00 10 TCL * 192 TCL * 200 1.04 00

00 11 TCL * 384 TCL * 400 1.04 00

11 00 TCL * 96 TCL * 240 2.5 11

11 01 TCL * 192 TCL * 280 1.46 11

11 10 TCL * 384 TCL * 400 1.04 11

11 11 TCL * 768 TCL * 800 1.04 11

ST10F269Zx sample time

ST10F273Z4 sample time

Ratio

F273Z4_time /

F269_time

ADCTC

10 00 TCL * 192 TCL * 480 2.08 10

10 01 TCL * 384 TCL * 560 1.46 10

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AN2556 Modified features

Table 5. ST10F273Z4 vs. ST10F269Zx sample time comparison table (continued)

ADCTC ADSTC

ST10F269Zx sample time

ST10F273Z4 sample time

10 10 TCL * 768 TCL * 800 1.04 10

10 11 TCL * 1536 TCL * 1600 1.04 10

In the default configuration, the sample time of the ST10F273Z4 is 2.5 times longer compared to the ST10F269Zx. This has an impact on the frequency of the input signal that can be applied to the ST10F273Z4.

1.4.2 Hardware impacts: electrical characteristics

Table 6: ADC differences lists the differences in the DC characteristics of the two devices.

Table 6. ADC differences

Limit values for

Parameter Symbol

Analog reference voltage V

Analog input voltage V

AREF

AIN

(1)

ADC input capacitance

Port5, not sampling - 10 - 7

Port5, sampling - 15 - 10.5

AIN

Port1, not sampling - N.A. - 9

ST10F269Zx

Min Max Min Max

4.0 VDD + 0.1 4.5 V

AGND

AREF

Ratio

F273Z4_time /

F269_time

Limit values for

ST10F273Z4

AGND

CP1 + CP2 +C

AREF

ADCTC

Unit

Port1, sampling - N.A. - 12.5

Sample time t

Conversion time t

48TCL 1536TCL

388TCL 2884TCL 388TCL 2884TCL

1µs

120TCL

1600TCL

Total unadjusted error

Port5 -2.0 +2.0 -2.0 +2.0

TUE LSB

Port1 - no overload - - -5.0 +5.0

Port1 - overload - - -7.0 +7.0

Internal resistance of analog source

ASRC

tS[ns]/150 - 0.25 kΩ

Port5 - 600

Analog switch resistance

N.A. N.A. Ω

Port1 - 1000

-1300

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