ST AN2549 Application note

AN2549

Application note

Porting an application from the ST10F269Zx to the ST10F272Z2

Introduction

The ST10F272Z2 is a new member of the STMicroelectronics ST10 family of 16-bit singlechip CMOS microcontrollers. It is functionally upward compatible with the ST10F269Zx.

The goal of this document is to highlight the differences between ST10F269Zx and ST10F272Z2 devices. It is intended for hardware or software designers who are adapting an existing application based on the ST10F269Zx to the ST10F272Z2.

This document presents the ST10F272Z2’s modified functionalities and the new ones, and goes on to describe the modified and the new registers. For each part, the differences with the ST10F269Zx that may have an impact when replacing the ST10F269Zx by the ST10F272Z2 are stressed and some advice is given on the way they can be handled.

July 2007 Rev 1 1/33

www.st.com

AN2549 Contents

Contents

1 Modified features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.5 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.6 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.7 Port input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.8 Ports output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.9 PLL and main on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 New features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1 Additional XPeripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2 Programmable divider on CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3 New multiplexer for X-Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4 Additional ports input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 Modified registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1 XPERCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4 New registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1 XADRS3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2 XPEREMU register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3 Emulation-dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.4 XMISC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.1 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.2 AC characteristics at 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2/33

AN2549 Modified features

1 Modified features

1.1 Pinout

1.1.1 Pinout modification summary

Ta bl e 1 summarizes the modifications made to the pinout.

Table 1. Pinout modifications

number

17 DC2

56 DC1

99 EA

143 V

144 V

ST10F269Zx ST10F272Z2

Name Function Name Function

Internal voltage regulator decoupling.

Connect to nearest V capacitor.

Internal voltage regulator decoupling. Connect to nearest VSS via a 330nF capacitor.

Selects code execution out of internal Flash memory or external memory according to level during reset.

Ground pin XTAL3

5V power supply pin XTAL4

via a 330nF

EA-V

STBY

5V power supply pin

Internal voltage regulator decoupling. Connect to nearest V 10 - 100nF capacitor.

Selects code execution out of internal Flash memory or external memory according to level during reset. Power supply input for the standby mode.

Input to the 32 kHz oscillator amplifier circuit. When not used, must be tied to ground to avoid consumption. Additionally, bit OFF32 in RTCCON register must be set.

Output of the 32 kHz oscillator amplifier circuit. When not used, must be left open to avoid spurious consumption.

via a

1.1.2 Pin 17

On the ST10F269Zx, a decoupling capacitor of 330nF minimum has to be connected between the pin 17 (named DC2) and the nearest V

This is no longer the case for the ST10F272Z2 device where pin 17 is a V

Hardware impact

PCB must be adapted.

Software impact

None.

pin.

3/33

AN2549 Modified features

1.1.3 Pin 56

On the ST10F269Zx, a decoupling capacitor of 330nF minimum has to be connected between the pin 56 (named DC1) and the nearest V

On the ST10F272Z2, pin 56 is named V

and a capacitor of value between 10nF minimum

and 100nF maximum must be connected between it and the nearest V

pin.

Hardware impact

Change on the capacitor value. As the value is much lower, the footprint of the capacitor might be smaller and then a modification of the PCB is needed.

Software impact

None.

1.1.4 Pin 99

On the ST10F269Zx, pin 99 is EA and used upon reset to select the start from the internal Flash memory or the external memory.

On the ST10F272Z2, pin 99 has the additional function of providing the 5V power supply to the device in standby mode (new power-saving mode), it is called EA

-V

STBY

Hardware impact

The modification depends on the previous use of the ST10F269Zx and on whether the Standby mode is used or not.

For an application where the Standby mode is not used, no change to the PCB is required. If the new application uses the Standby mode, the EA common 5V and have a specific supply path.

Software impact

None.

1.1.5 Pins 143 and 144

These pins are VSS and VDD, respectively, in the ST10F269Zx. On the ST10F272Z2 they are used as XTAL3 and XTAL4 for connection to an optional 32 kHz crystal to clock the Real Time Clock during power-down.

Hardware impact

PCB must be redesigned.

If the optional 32 kHz is not used:

● Pin 143 (XTAL3) must be linked to ground like on the ST10F269Zx

● Pin 144 (XTAL4) must be left open. It can also be connected to ground via a capacitor

to reduce the potential RF noise that might be propagated inside the device if the pin is left floating.

-V

pin must be separated from the

STBY

4/33

AN2549 Modified features

Software impact

In case the optional 32 kHz is not used, the OFF32 bit of the RTCCON register must be set. Prior to setting the OFF32 bit in the RTCCON register, the RTC must be enabled by setting RTCEN, bit 4 of XPERCON, and XPEN, bit 2 of SYSCON.

1.2 XRAM

The ST10F269Zx has 10 Kbytes of extension RAM whereas the ST10F272Z2 has 18 Kbytes.

The XRAM of the ST10F269Zx is divided into two ranges being XRAM1 of 2 Kbytes and XRAM2 of 8 Kbytes:

● The XRAM1 address range is 00’E000h - 00’E7FFh if enabled.

● The XRAM2 address range is 00’C000h - 00’DFFFh if enabled.

The XRAM of the ST10F272Z2 is divided into two ranges being XRAM1 of 2 Kbytes (compatible with the ST10F269Zx) and XRAM2 of 16 Kbytes with a user reprogrammable address range:

● The XRAM1 address range is 00’E000h - 00’E7FFh if enabled (XPEN and XRAM1EN,

bit 2 of SYSCON register and bit 2 of XPERCON register, respectively, must be set).

● The XRAM2 address range is 09’0000h - 09’3FFFh, by default (mirrored every

16 Kbytes in the range 09’0000h -0F’FFFFh), if enabled (XPEN and XRAM2EN, bit 2 of SYSCON register and bit 3 of XPERCON register, respectively, must be set).

Hardware impact

None.

Software impact

There is no change in the enabling of the XRAM blocks: XPERCON register bits, XRAM1EN and XRAM2EN, and SYSCON register bit, XPEN, are used to enable them.

The memory mapping of the application is impacted by the difference in XRAM size and by the location of XRAM2. A new register has been created in order to allow the user to remap the XRAM2 (please refer to Section 4.1: XADRS3 register on page 23 for details).

1.3 Flash EEPROM

Table 2. Flash memory key characteristics

Characteristic ST10F269Zx ST10F272Z2

Flash size 256 Kbytes 256 Kbytes

Flash organization 7 blocks 8 blocks

Programming voltage 5 volts 5 volts

Programming method Write/Erase Controller Write/Erase Controller

Program / Erase cycles 100000 cycles 100000 cycles

5/33

AN2549 Modified features

Table 3. Flash memory mapping

Segment ST10F269Zx Flash mapping ST10F272 Flash mapping

8 08’0000-08’FFFF External memory 08’0000-08’FFFF Flash registers

7..5 05’0000-07’FFFF External memory 05’0000-07’FFFF Reserved

4 04’0000-04’FFFF Block6: 64 Kbytes 04’0000-04’FFFF Block7: 64 Kbytes

3 03’0000-03’FFFF Block5: 64 Kbytes 03’0000-03’FFFF Block6: 64 Kbytes

2 02’0000-02’FFFF Block4: 64 Kbytes 02’0000-02’FFFF Block5: 64 Kbytes

01’8000-01’FFFF Block3: 32 Kbytes 01’8000-01’FFFF Block4: 32 Kbytes

01’0000-01’7FFF

00’8000 - 00’FFFF

00’6000 - 00’7FFF Block 2: 8 Kbytes 00’6000 - 00’7FFF Block3: 8 Kbytes

00’4000 - 00’5FFF Block 1: 8 Kbytes 00’4000 - 00’5FFF Block2: 8 Kbytes

00’0000 - 00’3FFF Block 0: 16 Kbytes

External memory or remap of Blocks 0-2

External memory Internal RAM and Registers

01’0000-01’7FFF

00’8000 - 00’FFFF

00’2000 - 00’3FFF Block1: 8 Kbytes

00’0000 - 00’1FFF Block0: 8 Kbytes

External memory or remap of Blocks 0-3

External memory Internal RAM and Registers

1.3.1 Hardware impact

None.

1.3.2 Software impact

As the first 32 Kbytes of Flash memory are now divided into four sectors of 8 Kbytes each in the ST10F272Z2 whereas the ST10F269Zx had only three sectors, the mapping of the application is impacted.

Moreover, the Flash memory Write/Erase controller is different and therefore the programming routines must be updated.

When the bit ROMEN of the SYSCON register is set, that is, when the internal Flash memory is enabled, accesses to the address range 05’0000h - 07’FFFFh are not redirected to external memory. The linker-locator configuration of the toolchain should be checked in order to prevent any use of this memory range.

6/33

AN2549 Modified features

1.4 A/D converter

In the ST10F272Z2, the analog/digital converter has been redesigned (compared to the A/D converter in the ST10F269Zx). The ST10F272Z2 still provides an analog/digital converter with 10-bit resolution and an on-chip sample and hold circuit.

1.4.1 Hardware / Software impact: conversion timing control

The A/D converter in the ST10F272Z2 is not fully compatible with that of the ST10F269Zx (timing and programming model).

In the ST10F269Zx, the sample time (to charge the capacitors) and the conversion time are programmable and can be adjusted to the external circuitry. The total conversion time is compatible with the formula used for ST10F269Zx, whereas the meanings of the ADCTC and ADSTC bit fields are no longer compatible.

Table 4. ST10F272Z2 conversion timing table

ADCTC ADSTC Sample Comparison Extra Total conversion

00 00 TCL * 120 TCL * 240 TCL * 28 TCL * 388

00 01 TCL * 140 TCL * 280 TCL * 16 TCL * 436

00 10 TCL * 200 TCL * 280 TCL * 52 TCL * 532

00 11 TCL * 400 TCL * 280 TCL * 44 TCL * 724

11 00 TCL * 240 TCL * 120 TCL * 52 TCL * 772

11 01 TCL * 280 TCL * 560 TCL * 28 TCL * 868

11 10 TCL * 400 TCL * 560 TCL * 100 TCL * 1060

11 11 TCL * 800 TCL * 560 TCL * 52 TCL * 1444

10 00 TCL * 480 TCL * 960 TCL * 100 TCL * 1540

10 01 TCL * 560 TCL * 1120 TCL * 52 TCL * 1732

10 10 TCL * 800 TCL * 1120 TCL * 196 TCL * 2116

10 11 TCL * 1600 TCL * 1120 TCL * 164 TCL * 2884

The user should take care of the Sample time parameter: This is the time during which the capacitances of the converter are charged via the respective analog input pins. Ta bl e 5 shows the differences in sample time.

7/33

AN2549 Modified features

Table 5. ST10F272Z2 vs ST10F269Zx sample time comparison table

ADCTC ADSTC

ST10F269Zx Sample time

ST10F272Z2 Sample time

00 00 TCL * 48 TCL * 120 2.5

00 01 TCL * 96 TCL * 140 1.46

00 10 TCL * 192 TCL * 200 1.04

00 11 TCL * 384 TCL * 400 1.04

11 00 TCL * 96 TCL * 240 2.5

11 01 TCL * 192 TCL * 280 1.46

11 10 TCL * 384 TCL * 400 1.04

11 11 TCL * 768 TCL * 800 1.04

10 00 TCL * 192 TCL * 480 2.08

10 01 TCL * 384 TCL * 560 1.46

10 10 TCL * 768 TCL * 800 1.04

10 11 TCL * 1536 TCL * 1600 1.04

In the default configuration the sample time of the ST10F272Z2 is 2.5 times longer compared to that of the ST10F269Zx. This has an impact on the frequency of the input signal that can be applied to the ST10F272Z2.

1.4.2 Hardware impact: electrical characteristics

Ratio

F272Z2_time / F269_time

Ta bl e 6 lists the differences in the DC characteristics of the two devices.

Table 6. ADC differences

Symbol Parameter

AREF

AIN

TUE

ASRC

Analog reference voltage

Analog input voltage V

ADC input capacitance (Port 5)

Not sampling Sampling

Sample time 48TCL 1536TCL

Conversion time 388TCL 2884TCL 388TCL 2884TCL

Total Unadjusted Error (Port5)

Internal resistance of analog source

Limit values for ST10F269Zx Limit values for ST10F272Z2

Min Max Min Max

4.0 V

AGND

+ 0.1 4.5 V

AREF

10 15

AGND

1µs

120TCL

+ CP2 +C

1600TCL

AREF

10.5

-2.0 +2.0 -2.0 +2.0 LSB

[ns]/150-0.25 kΩ

Unit

8/33

AN2549 Modified features

Table 6. ADC differences (continued)

Limit values for ST10F269Zx Limit values for ST10F272Z2

Symbol Parameter

Min Max Min Max

Reference supply

AREF

current Running mode Power-down mode

500

5000

DNL Differential nonlinearity -0.5 +0.5 -1 +1 LSB

INL Integral nonlinearity -1.5 +1.5 -1.5 +1.5 LSB

OFS Offset error -1.0 +1.0 -1.5 +1.5 LSB

Unit

µA µA

Note: The V

pin is also used as a supply pin for the ADC module. As there is a higher current

AREF

sink on this pin on the ST10F272Z2 compared to the ST10F269Zx, it is recommended not to connect a resistor (for example, because of an RC filter), to prevent creating an offset in the reference.

1.4.3 Software impact

Self-calibration and ADC initialization routine

An automatic self-calibration adjusts the ADC module to process parameter variations at each reset event. After reset, the busy flag (read-only) ADBSY is set because the selfcalibration is ongoing. The duration of self-calibration depends on the CPU clock: It may take up to 40.629 ± 1 clock pulses. The user must poll this bit to know when self-calibration is complete in order to initialize the ADC module.

This self-calibration is seen by the ST10F272Z2 as a conversion and thus bit ADCIR is set. The software should perform a dummy read of the ADDAT register and clear the ADCIR and ADCEIR flags before configuring the ADC module and starting the first conversion.

New bit ADOFF, bit 6 of ADCON register

ADCON (FFA0h / A0h) SFR Reset value: 0000h

15 14 13 12 11 10 9 8 76543210

ADCTC ADSTC

R/W R/W R/W R/W R/W RO R/W R/W R/W R/W

Table 7. ADCON register description

CRQADCINADWRADBSYADSTADOFF

ADM ADCH

Bit Function Comment

ADOFF

ADC Disable

0: Analog circuitry of A/D converter is on 1: Analog circuitry of A/D converter is turned off

New bit valid only for the ST10F272Z2. Reserved on ST10F269Zx.

The bit 6 of the ADCON register, reserved in previous ST10 devices, is now used to enable and disable the ADC. By default this bit is cleared and the ST10F272Z2 is compatible with the ST10F269Zx. Therefore, there is no impact on the software, provided that this bit is not written to.

9/33

AN2549 Modified features

Additional channels on Port1

A new multiplexer selects one out of up to 16 + 8 analog input channels (alternate functions of Port 5 and Port1). The selection of Port1 or Port5 as the input of the ADC is made via bit ADCMUX, bit 0 of the XMISC register. By default the multiplexer selects Port5, so there is no impact on the software as compared to an ST10F269Zx implementation. Note that XMISCEN, bit 10 of the XPERCON register, must be set to have access to the XMISC register.

XMISC (EB46h) XREG Reset value: --00h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VREG

CAN

Reserved

- R/W R/W R/W R/W

Table 8. XMISC register description

Bit Function

ADC Multiplexer

ADCMUX

0: Default configuration, analog inputs on port P5.y can be converted 1: Analog inputs on port P1.z can be converted, only 8 channels can be managed

OFF

CK2

PA R

ADC MUX

1.5 Real time clock

The RTC module can be clocked by two different sources: the main oscillator (pins XTAL1 and XTAL2) or the 32 kHz oscillator (pins XTAL3 and XTAL4). The selection of the clocking can be made via an additional bit in the RTCCON register.

1.5.1 Hardware impact

Check the usage of pins XTAL3 and XTAL4 (pins 143 and 144, respectively).

1.5.2 Software impact

The address range of the RTC registers has been modified from 00’EC00h - 00’ECFFh on the ST10F269Zx, to 00’ED00h - 00’EDFFh on the ST10F272Z2. This relocation has no impact if the software uses register names defined by the toolchain and if the CPU selection is changed to ST10F272Z2. If the software was directly using the address of the RTC register, it must be modified according to the new mapping.

ST10F269Zx: RTCCON (F1C4h / E2h) ESFR Reset value: --00h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

ST10F272Z2: RTCCON (F1C4h / E2h) ESFR Reset value: 0000h

15 14 13 12 11 10 9 8 7654 3 2 1 0

RTC OFF

- R/W - R/W R/W R/W R/W

Reserved

RTC AEN

RTC

AIR

RTC SEN

RTC

SIR

10/33

+ 23 hidden pages