ST AN2548 Application note

AN2548

Application note

Using the STM32F101xx and STM32F103xx DMA controller

1 Introduction

This application note describes how to use the STM32F101xx and STM32F103xx direct memory access (DMA) controller. The STM32F101xx and STM32F103xx DMA controller, the Cortex™-M3 core, the advanced microcontroller bus architecture (AMBA) bus and the memory system contribute to provide a high data bandwidth and to develop very-low latency response time software.

This application note also describes how to take full advantage of these features and ensure correct response times for different peripherals and subsystems.

The STM32F101xx and STM32F103xx will be referred to as STM32F10xxx, and the DMA controller as DMA throughout the document.

April 2009

Doc ID 13529 Rev 3

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Contents	AN2548

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		1
2	DMA controller description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		3
	2.1	Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3
3	Performance considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6

3.1 Round robin priority scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Multi-layer structure and bus stealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 DMA latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.4 Databus bandwidth limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.5 Choosing channel priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.5.1 Application requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5.2 Internal data bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4	DMA programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	4.1	Example of ADC continuous data acquisition with SPI transfer . . . . . . . .	11
	4.2	ADC continuous data acquisition with direct SPI transfer . . . . . . . . . . . .	11
	4.3	GPIO fast data transfer with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
5	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13

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AN2548	DMA controller description

2 DMA controller description

The DMA is an AMBA advanced high-performance bus (AHB) module that features two AHB ports: a slave port for DMA programming and a master port that allows the DMA to initiate data transfers between different slave modules.

The DMA allows data transfers to take place in the background, without the intervention of the Cortex-M3 processor. During this operation, the main processor can execute other tasks and it is only interrupted when a whole data block is available for processing. Large amounts of data can be transferred with no major impact on the system performance.

The DMA is mainly used to implement central data buffer storage (usually in system SRAM) for different peripheral modules. This solution is less expensive in terms of silicon and power consumption compared to a distributed solution where each peripheral needs to implement it own local data storage.

The STM32F10xxx DMA controller takes full advantage of the Cortex-M3 Harvard architecture and the multilayer bus system in order to ensure very low latency both for DMA transfers and for CPU execution/interrupt event detection/service.

Depending on the sales type used, one or two DMA controllers are implemented.

2.1Main features

The DMA(s) offer(s):

●Twelve DMA channels (7 for DMA1 and 5 for DMA2) supporting unidirectional data transfers from source to destination

●Hardwareand software-programmable channel priority for each DMA

●Memory-to-memory, memory-to-peripheral, peripheral-to-memory and peripheral-to- peripheral transfers (memory can be SRAM or Flash)

●Control of hardware/software transfers

●Automatic increment of peripheral and memory pointers

●Programmable data size

●Automatic bus-error management

●Non-circular/circular mode

●Transfer of up to 65536 data tokens

The DMA aims to offer a relatively large data buffer to all peripherals. This buffer is usually located in system SRAM.

Each channel is assigned to a unique peripheral (data channel) at a given time. Peripherals connected to the same DMA channel (CH1 to CH7 in Table 1, CH1 to CH5 in Table 2) cannot be used simultaneously with active DMA (DMA function active in the peripheral register).

The different peripherals supporting DMA transfers are shown in Table 1 and Table 2. The peripherals served by the DMA and the bus system structure are represented in Figure 1.

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DMA controller description								AN2548
Table 1.	Peripherals served by DMA1 and channel allocation
Peripherals		CH1	CH2	CH3	CH4	CH5	CH6	CH7
ADC	ADC1	ADC1
SPI	SPI1		SPI1_RX	SPI1_TX
	SPI2				SPI2_RX	SPI2_TX
	USART1				USART1_	USART1_RX
					TX
USART
	USART2						USART2_RX	USART2_TX
	USART3		USART3_TX	USART3_RX
I2C	I2C1						I2C1_TX	I2C1_RX
	I2C2				I2C2_TX	I2C2_RX
					TIM1_CH4
	TIM1		TIM1_CH1	TIM1_CH2	TIM1_TRIG	TIM1_UP	TIM1_CH3
					TIM1_COM
TIM	TIM2	TIM2_CH3	TIM2_UP			TIM2_CH1		TIM2_CH2
								TIM2_CH4
	TIM3		TIM3_CH3	TIM3_CH4			TIM3_CH1
				TIM3_UP			TIM3_TRIG
	TIM4	TIM4_CH1			TIM4_CH2	TIM4_CH3		TIM4_UP

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AN2548						DMA controller description
	Table 2.	Peripherals served by DMA2 and channel allocation
	Peripherals		CH1	CH2	CH3	CH4	CH5
	ADC	ADC3					ADC3
	SPI	SPI/I2S3	SPI/I2S3_RX	SPI/I2S3_TX
	USART	USART4			USART1_TX		USART1_RX
	SDIO	SDIO				SDIO
		TIM5	TIM5_CH4	TIM5_CH3		TIM5_CH2	TIM5_CH1
			TIM5_TRIG	TIM5_UP
		TIM6			TIM6_UP/
					DAC_Channel1
	TIM
		TIM7				TIM7_UP/
						DAC_Channel2
			TIM8_CH3	TIM8_CH4
		TIM8		TIM8_TRIG		TIM8_CH1	TIM8_CH2
			TIM8_UP
				TIM8_COM

Figure 1. Bus system and peripherals supporting DMA

Cortex-M3

DMA1

Ch.1

Ch.2

Ch.7

DMA2

Ch.1

Ch.2

Ch.5

ICode

FLITF

Flash

DCode

Sys tem

matrixBus

SRAM

SDIO

DMA

FSMC

	AHB system bus	Bridge	2
		Bridge	1	APB 1
DMA	Reset & clock			APB2
	control (RCC)

					ADC1	GPIOC	DAC		SPI3/I2S
					ADC2	GPIOD	PWR		SPI2/I2S
	DMA Request				ADC3	GPIOE	BKP			IWDG
					USART1	GPIOF	bxCAN WWDG
					SPI1	GPIOG	USB			RTC
					TIM1	EXTI	I2C2			TIM7
					TIM8	AFIO	I2C1			TIM6
					GPIOA		UART5			TIM5
					GPIOB
							UART4			TIM4
							USART3			TIM3
							USART2			TIM2

DMA request

ai14800c

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