This note describes the performances of a 400W reference board, with wide-range mains
operation and power-factor-correction (PFC) and presents the results of its bench
evaluation. The electrical specification refers to a power supply for general purpose
application, with two main output voltages (200 V and 75 V).
The main features of this design are the very low no-load input consumption (<0.5 W) and
the very high global efficiency, better than 90% at full load and n ominal mains v o ltage (115 230 V
The circuit consists of three main bloc ks. The first is a front-end PFC pre-re gulator based on
the L6563 PFC controller. The second stage is a multi-resonant half-bridge converter with
two output volta ges of +200 V/300 W a nd 75 V/75 W, whose control is implemented through
the L6599 resonant controller. A further auxiliary flyback converter based on the VIPer12A
off-line primary switcher completes the architecture. This third block, deliv ering a total power
of 7 W on two output voltages (+3.3 V and +5 V), is mainly intended for microprocessor
supply and display power management operations
Figure 20.Thermal map @115 V
Figure 21.Thermal map at 230 V
Figure 22.Peak measurement on LINE at 115 V
Figure 23.Peak measurement on Neutral at 115 V
Figure 24.Peak measurement on LINE at 230 V
Figure 25.Peak measurement on Neutral at 230 V
Main characteristics and circuit descriptionAN2509
1 Main characteristics and circuit description
●The main characteristics of the SMPS are listed below:
●Universal input mains range: 90 to 264 V
●Output voltages: 200 V @ 1.5 A - 75 V @ 1 A - 3.3 V @ 0.7 A - 5 V @ 1 A
●Mains harmonics: compliance with EN61000-3-2 specifications
●Standby mains consumption: less than 0.5 W @230 V
●
Overall efficiency: better than 87% at full load, 90-264 V
●
EMI: Compliance with EN55022-class B specifications
●Safety: Compliance with EN60950 specifications
●PCB single layer: 132x265 mm, mixed PTH/SMT technologies
The circuit consists of three stages. A front-end PFC pre-regulator implemented by the
controller L6563 (Figure 1), a half-bridge resonant DC/DC conve rter based on the reson ant
controller L6599 (Figure 2), and a 7 W flyback converter intended for standby management
(Figure 3) utilizing the VIPer12A off-line primary switcher.
The PFC stage delivers a stable 400 VDC supply to the do wnstream con v erters (resonant +
flyback) and provides for the reduction of the current harmonics drawn from the mains, in
order to meet the requirements of the Euro pe a n no rm EN61000-3-2 and the JEIDA-MITI
norm for Japan.
- 45 to 65 Hz:
AC
AC
AC
The PFC controller is the L6563 (U1), integrating all functions needed to operate the PFC
and interface the downstream resonant converter. Although this controller chip is designed
for Transition-Mode (TM) operation, where the boost inductor wo rks next to the boundary
between Continuous (CCM) and Discontin uous Conduction Mode (DCM), by adding a
simple external circuit, it can be operated in LM-FOT (line-modulated fixed off-time). This
mode allows for CCM o perat ion, normally achie v ab le with more e x pensiv e contro l chips and
more complex architectures . The LM-F O T mode allows the use of a lo w-cost de vice lik e the
L6563 at a high power level, usually covered by CCM topologies. For a detailed and
complete description of the LM-FOT operating mode see the application note AN1792. The
external components to configure the circuit in LM-FOT mode are: C15, C17, D5, Q3, R14,
R17 and R29.
The power stage of the PFC is a conventional boost converter, connected to the output of
the rectifier bridge through a differential mode filtering cell (C5, C6 and L3) for EMI
reduction. It includes a coil (L4), a diode (D3) and two capacitors (C7 and C8). The boost
switch consists of two power MOSFETs (Q1 and Q2), connected in parallel, which are
directly driven by the L6563 output drive thanks to the high current capability of the IC.
The divider (R30, R31 and R32), connected to MULT pin 3, providesthe information of the
instantaneous voltage that is used to modulate the boost current and to derive further
information like the average value of the AC line used by the V
(voltage feed-forward)
FF
function. This function is used to keep the output voltage almost independent of the mains.
The divider (R3, R6, R8, R10 and R11) is dedicated to detecting the output voltage while a
further divider (R5, R7, R9, R16 and R25) is used to protect the circuit in case of voltage
loop failure.
The second stage is an LLC resonant converter, with half-bridge topology implementation,
working in ZVS (zero voltage switching) mode.
4/37
AN2509Main characteristics and circuit description
The controller is the L6599 integrated circuit that incorporates the necessary functions to
properly drive the two half-bridge MOSFETs b y a 50 % fix ed duty cycle with fixed dead-time,
changing the frequency according to the feedback signal in order to regulate the output
voltages against load and input voltage variations. The main features of the L6599 are a
non-linear soft-start, a current protection mode used to program the hiccup mode timing, a
dedicated pin for sequencing or brown-out (LINE) and a standby pin (STBY) for burst mode
operation at light loads (not used in this design).
The transformer (T1) uses the magne tic integration approach, incorporating the resonant
series and shunt inductances of the LLC resonant tank. Thus, no additional external coils
are needed for the r esonance. F or a detaile d analysis of the LLC r esonant con v erter , please
refer to the application note AN2450.
The secondary side power circuit is configured with center- tap windings and two diodes
rectification for each outpu t (diod es D8A, D8B, D10A, D10B). The two center tap windings
are connected in series on the DC side (r efer to Figure 2). The +75 V rail is connected to
the center tap of the higher voltage winding (the one connected to the anodes of D8A and
D8B diodes). Therefore the higher v oltage windin g only has to provide a v oltage equal to the
difference of the two output voltages: 200 V - 75 V = 125 V. This winding arrangement has
the advantage of a better cross regulation with respect to the case of two completely
separated outputs. F urthermore, due to the fact that the +200 V diodes only have to
withstand a voltage of about 25 0 V (2 x 125 V), inst ead of about 400 V in case of complet ely
separated windings, the designer can select a diode with a lower junction capacitance
minimizing the effect of this capacitance refle ct ed at transformer primary side. This may
affect the behavior of the resonant tank, changing the circuit from LLC to LLCC type, with
the risk that the conv erter, in light-load/n o-load condition ( when the f e edbac k loop increa ses
the operating frequency), can no longer control the output voltage.
The feedbac k loop is implemented b y means of a classical con figuration using a TL431 (U4)
to adjust the current in the optocoupler diode (U3). The optocoupler transistor modu lates the
current from controller Pin 4, so the frequency will change accordingly, thus achieving the
output voltage regulation. Resistors R46 and R54 set the maximum operat ing frequency.
In case of a short circuit, the current entering the primary winding is detected by the lossless
circuit (C34, C39, D11, D12, R43, and R45) and the resulting signal is fed into L6599 Pin 6.
In case of overload, the voltage on Pin 6 exceeds an internal threshold that triggers a
protection sequence via Pin 2, keeping the current flowing in the circuit at a safe level.
The third stage is a small flyback converter based on the VIPer12A, a current mode
controller with integrated power MOSFET, capable of delivering about 7 W total output
power on the output voltages (5 V and 3.3 V). The regulated output voltage is the 3.3V
output and, also in this case, the feedback loop uses the TL431 (U7) and optocoupler (U6)
to control the output volta ge.
This converter is able to operate in the whole mains voltage range, even when the PFC
stage is not working. From the auxiliary winding on the primary side of the flyback
transformer (T2), a voltage Vs is available, intended to supply the other controllers (L6563
and L6599) in addition to the VIPer12A itself.
The PFC stage and the resonant converter can be switched on and off through the circuit
based mainly on components Q7, Q8, D22 and U8, which, depending on the level of the
signal ST-BY, supplies or removes the auxiliary voltage (VAUX) necessary to start-up the
controllers of the PFC and resonant stages. When the AC input voltage is applied to the
power supply, the small flyback converter switches on first. Then, when the ST-BY signal is
asserted low, the PFC p re-regulator becomes oper ative , and last the resonant conv erter can
deliver the output power to the load. Note that if Pin 9 of Connector J3 is left floati ng (no
5/37
Main characteristics and circuit descriptionAN2509
signal ST-BY present), the PFC and resonant converter will not operate, and only +5 V and
+3.3 V supplies are availa ble on the output. In order to enable the +200 V and +75 V
outputs, Pin 9 of Connector J3 must be pulled down to ground.
Figure 1.PFC pre-regulator electrical diagram
Vdc
+400V
C9
2nF2-Y 1
330uF/450V
C8
R2
NTC 2R5-S237
C7
470nF/630V
D3
STTH8R06
1-2
D1
1N5406
L4
PQ40-500uH
5-6
D4
LL4148
Q2
STP12NM50FP
Q1
STP12NM50FP
D6
LL4148
R18
R15
6R8
6R8
R24
0R39
R23
0R39
R22
0R39
R21
0R39
R19
1k0
C18
330pF
Vrect
C6
470nF/630V
L3
DM-51uH-6A
C5
470nF/630V
Vaux
+
-
D2
D15XB60
~
~
C11
2
680nF-X2
Jumper
330nF-X2
470nF-X2
1M5
2nF2-Y2
C10
2nF2-Y2
CON2-IN
C4
Jumper
C3
L1
CM-1.5mH-5A
C2
R1
F1
8A/250V
1
J1
R4
47
C13
10uF/50V
C12
100nF
R6
680kR8680k
R3
680k
R5
Vdc
2M2
R11
R10
R7
2M2
R9
D5
C15
100pF
R14
3k3
R17
C17
15k
U1
L6563
100k
R13
56k
C14
100nF
C16
1uF
2M2
CSCS
LL4148
15k
220pF
GD
VCC
INV
COMP
ZCD
GND
MULTCSVFF
PWM-Latch
R29
1k5
Q3
BC857C
R20
1k0
C21
2nF2
R28
RUN
PWM-STOP
TBO
PFC-OK PWM-LATCH
R16
5k1
LINE
240k
R26
150k
C20
470nF
C19
10nF
R25
30k
C22
10nF
R32
10k
R31
620k
R30
620k
Vrect
6/37
AN2509Main characteristics and circuit description
Figure 2.Resonant converter electrical diagram
1234567
J2
+200V
L5
T1
8
CON8
C25
22uF/250V
C29
10uH
C30
D8A
T-RE S-ER 49- 400 W
D8B
BYT08P-400
BYT08P-400
C28
47nF/630V
+75V
C38
C35
100uF/250V
JP
100uF/250V
47uF/100V
L6
22uH
D10B
D10A
STTH1002C
STTH1002C
220uF/100V
C37
220uF/100V
R50
56k
R49
56k
R48
56k
R86
C59
R53
C41
D13
R52
470R
47nF
R61
75k
R58
75k
10uF/50V
C-12V
R56
1k0
3k3
U3A
SFH617A-2
2k7
R60
6k2
R59
1k0
C44
47nF
U4
TL431
R43
150
C34
220pF/630V
Vdc
Q5
R33
D7
R88
560k
Q12
BC557
C61
470nF
Q6
STP14NK50Z
0R
R35
47
LL4148
C23
100nF
STP14NK50Z
R39
0R
R40
47
D9
LL4148
C27 100nF
U2
L6599
R36
0R
R34
2k7
C24
470nF
R37
2M2
VBOOT
CSS
C26
OUT
HVG
DELAYCFRFMIN
270pF
R41
Vaux
C32
100nF
R38
47
C31
10uF/50V
NC
LVG
VCC
STBY
ISEN
LINEGND
DISPFC-STOP
C33
4nF7
R42
10
16k
D11
LL4148
D12
LL4148
R45
100R
C39
1uF0
U3B
C40
10nF
R47
10k
R46
1k5
SFH617A-2
R87
220R
C60
470nF
R54
1k5
LINE
PWM-Latch
7/37
Main characteristics and circuit descriptionAN2509
Q10
BC847C
C54
100nF
U7
TL431
C53
2nF2
U6A
SFH617A-2
U6B
SFH617A-2
Vs
+200V
R67
1k0
SSFB
Vdd D
D
D
D
U5
VIPER-12A
R82
100k
R79
2k2
D15
1N5822
D16
1N5821
D20
BAV103
C56
100nF
C45
1000uF/10V
C47
1000uF/10V
C50
10uF/50V
C46
100uF/10V
C49
100uF/10V
Q9
BC857C
C48
10uF/50V
R76
150k
U8A
SFH617A-2
R75
150k
U8B
SFH617A-2
R74
10k
R77
4k7
D19
C-30V
St-By
D18
B-10V
123456789
10
J3
CON10
R69
0R
Vdc
C52
47nF
R68
22k
C51
100nF
R71
10k
Q8
BC847C
R72
10k
C55
10uF/50V
R66
1k0
T2
T-FLY -AUX-E20
+400V
R70
22R
Vdc
+400V
R83
1M0
R84
150k
C58
10nF
Q11
BC557C
+5Vst -by
R81
30k
R80
30k
+3V3
+5Vst-by
Q7
BC547C
D22
C-15V
L7
33uH
L8
33uH
D17
LL4148
+75V
D21
B-15V
D23
B-15V
R62
47
R64
1k6
C57
1nF0
Vs
Vaux
+5Vst -by
D14
PKC-136
St-By
R73
8k2
Figure 3.Auxiliary converter electrical diagram
8/37
AN2509Electrical test results
2 Electrical test results
2.1 Harmonic content measurement
The current harmonics drawn from the mains have been measured according to the
European rule EN61000-3-2 Class-D and Japanese rule JEIDA-MITI Class-D, at full load
and 70 W output power, at both nominal input voltages (230 V
in Figure 4 to Figure 7 show that the measured current harmonics are well below the limits
imposed by the regulations , both at full-load and at 70 W load.
and 100 VAC). The graphs
AC
Figure 4.Compliance to EN61000 -3 -2
standard for harmonic reductio n :
10
1
0.1
0.01
0.001
0.0001
full load
Measurements @ 230Vac Full load EN61000-3-2 class D limit s
1234567891011121314151617181920
Harmoni c Order (n)
Figure 6.Compliance to JEIDA-MITI standard
10
for harmonic reduction: full load
Measurements @ 100Vac Full load J EIDA- M ITI c la ss D l im it s
Figure 5.Compliance to EN61000-3-2
standard for harmonic reduction:
70 W load
Measurement s @ 230Vac 70W EN61 000-3-2 cl ass D limits
Measurement s @ 100V ac 70W JEI DA -MIT I cla s s D limits
1
1
0.1
0.01
0.001
0.0001
1234567891011121314151617181920
Harmoni c Order (n)
The Power Factor (PF) and the Total Harmonic Distortion (THD) are reported in Figure 8
and Figure 9. It is evident from the graph that th e PF stays close to unity in the whole mains
voltage range at full load and at half load, while it decreases at high mains at low load
(70 W). The THD has similar behavior, remaining within 25% overall the mains voltage
range and increasing at low load (70 W) at high mains voltage.
0.1
0.01
0.001
0.0001
1234567891011121314151617181920
Harmoni c Orde r (n )
9/37
Electrical test resultsAN2509
Figure 8.Power factor vs. Vin & loadFigure 9.Total harmonic distortion vs. Vin &
PF
1.00
0.98
0.95
0.93
0.90
0.88
0.85
80120160200240280
400W
200W
70W
Vin [Vrms]
THD [%]
25.00
20.00
15.00
10.00
5.00
0.00
80120160200240280
load
400W
200W
70W
Vin [Vrms]
2.2 Efficiency measurements
Table 1 and Table 2 show the output voltage measurements at the nominal mains voltages
of 115 V
load and at light load operations, the input power is measured using a Yokogawa WT-210
digital power meter. Particular attention has to be paid when measuring input power at full
load in order to avoid measurement errors due to the voltage drop on cables and
connections.
and 230 VAC, with different load condi tions. For all measurements, both at full
AC
Figure 10 shows the overall circuit efficiency, measured at each load condition, at both
nominal input mains voltages of 115 V
and 230 VAC. The values were measured af ter 30
AC
minutes of warm-up at maximum load. The high efficiency of the PFC pre-regulator working
in FOT mode and the very high efficiency of the resonant stage working in ZVS (i.e. with
negligible switching losses), provides for an overall efficiency better than 87% at full load in
the complete mains voltag e r a ng e. This is a significant high value for a two-stage converter ,
especially at low input mains voltage where the PFC conduction losses increase. Even at
lower loads, the efficiency still remains high.
Table 1.Efficiency measurements @VIN = 115 V
+200 V @load(A)+75 V@load(A)+5 V @load(A)+3.3 V@load(A)POUT(W)PIN(W)Eff. %
The global efficiency at full load has been measured even at the limits of the input voltage
range, with good results:
At VIN = 90 V
At VIN = 264 V
- full load, the efficiency is 87.27%
AC
- full load, the efficiency is 93.49%
AC
Also at light load, at an output power of about 10% of the maximum level, the overall
efficiency is very good, reaching a v alue of about 75% a t nominal main s v oltag es. Figure 11
shows the efficiency measured at various output power levels versus input mains voltage.
The cross regulation of the resonant converter stage is very good as shown in Table 3,
where the +200 V and +75 V output v o ltages are measur ed in different load conditions, with
minimum output current equa l to 10% of maximum current for both the output volta ges.
Figure 10. Overall efficiency versus output power at nominal mains voltages
230Vac115Vac
95%
90%
85%
Eff. (%)
80%
75%
70%
050100150200250300350400450
Output Power (W)
Figure 11. Overall efficiency versus input mains voltage at various output power
levels
400W200W70W
Eff[%]
94%
93%
92%
91%
90%
89%
88%
87%
86%
85%
80120160200240280
Vin [Vrms]
2.3 Resonant stage operating waveforms
Figure 12 shows some waveforms during steady state operation of the resonant circuit at full
load. The Ch1 waveform is the half-bridge square voltage on Pin 14 of L6599, driving the
resonant circuit. In the picture it is not e vident, but the switching frequency is normally
slightly modulated following the PFC pre-regulator 100-Hz ripple that is rejected by the
12/37
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