ST AN2503 APPLICATION NOTE

AN2503

Application note

PDP Power Devices

Introduction

This application note discusses how to select o ptimal po we r de vices a nd contro l circuitry fo r
alternating plasma display panel applications, concentrating on power circuits used to
sustain plasma discharge on the panel.

Plasma Display Panels (PDP) are emerging as the leading candidate for large area wall­hanging color TVs and HDTVs [1.]. Its large scr een, wide viewing angle, and thinness have
given it the edge over conventional displays. Scan, Energy Recovery (ERC) and Sustain
(discharge) circuits are important blocks that fulfill important energy saving requirements.

May 2007 Rev 1 1/30

www.st.com

Contents AN2503

Contents

1 PDP Module structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 PDP basic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 PDP cell structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Panel memory characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3 PDP driving sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 PDP Sustain circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Sustain circuit operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1.1 Positive pulse of Vyx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1.2 Positive discharge and clamping phase . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1.3 Vyx back to zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1.4 Clamping to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Symmetrical Y - X phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3 Reset phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 PDP Power Devices characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 Power devices from ST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1.1 Measurement set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1.2 Energy recovery section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1.3 Discharge section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.4 Path section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.5 Set - reset section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2 Driving section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3 Gate driver devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.1 Totem pole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4 Input buffer section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Bill of material and schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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AN2503 List of figures

List of figures

Figure 1. PDP module structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Cell structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Memory effect - no charges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. Memory effect - address phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. Memory effect - Wall charges deposit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 6. Memory effect - discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 7. Memory effect - wall charges deposit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 8. Memory effect - discharge with reverse polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 9. Subfield structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 10. Subfield structure – expression of gray level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 11. Sustain circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 12. Circuit scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 13. Circuit scheme – positive pulse of V

Figure 14. Equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 15. Circuit scheme – positive discharge and clamping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 16. Circuit scheme – V

back to zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

yx

Figure 17. Circuit scheme – clamping to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 18. Circuit scheme – negative pulse of V

Figure 19. Circuit scheme – negative discharge and clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 20. Circuit scheme – V

back to zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

yx

Figure 21. Circuit scheme – clamping to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 22. Circuit scheme – set and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 23. Inductor current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 24. Gate driver topology with L6385. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 25. Gate driver topology – L6388 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 26. STS01DTP06 Totem pole. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 27. Board schematic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 28. Board schematic 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

yx

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

yx

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PDP Module structure AN2503

1 PDP Module structure

Po wer supply, address buffer, logic and scan buff er boards are the fundamental blocks of a
PDP. In particular, the energy recovery and sustain function are performed by the Y and X
drive boards. Power MOSFETs, IGBTs, Diodes and Drivers are key products for ERC and
sustain both in X and in Y drive boards. These products are also used for the path, set-reset
function in the Y drive board only. Path switches are mandatory to isolate ERC and Sustain
switches from the negative voltage applied to the display during the scan phase, while, set
and reset switches determine identical initial condition of the plasma cells before each
address cycle.

Figure 1. PDP module structure

ST's extensive portfolio covers the whole solutio n for an energy recovery circuit (ERC),
sustain circuit, path circuit, and set-reset circuit, both from a power device and IC driver
perspective.

The ST solution takes into account all fundamental requirements like cost, component
count, reliability and power consumption.

Reduced power losses and higher switching frequency are the main benefits of ST's
advanced technology.

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AN2503 PDP basic

2 PDP basic

Basic knowledge on Plasma Display Panel encompasses manufacturing issues in cell
structure, physics principle in the memo ry effect, and display algorithms needed to create a
range of colors.

2.1 PDP cell structure

Figure 2 shows the structure of a plasma display glass panel, [2.].

Figure 2. Cell structure

An AC PDP displa y is composed of front and rear glass substrates sandwiche d together and
then sealed. The air is vacuumed out and a mixture of inert gases (Ne and Xe) is injected
between the glass substrates . The separation between the two opp osing substrates is about
100um and the space between them is filled with a gas mixture of Ne and Xe. The front
glass substrate has a first electrode (X electrode) and a second electrode (Y electrode)
which operate as sustain electrodes. The X and Y electrodes are coated with bus
electrodes, dielectric layer, and MgO layer in sequence. The MgO protects the dielectric
from plasma damage and also aids the plasma in sustaini ng a discharge through secondary
electron emission from its surface. In addition, equivalent capacitor exists between the X
and Y electrodes. On the surface of the rear glass substrate, as opposed to the front glass
substrate, a third electrode operating as an address electrode (A electrode) is formed to be
orthogonal to the X and Y electrodes. Electrically, the entire assembly can now be
considered as a three-electrode capacitor. A cross point is formed where the X, Y and A
electrodes meet. Three adjacent red, blue and green cross points form a color picture
element (pixel) of the panel. In operation, an AC voltage sufficiently high will ionize the gas
to create the plasma. Then, the ultraviolet light from the plasma excites the phosphor to
create the color image.

Each pixel can be independently controlled and can assume different color gradations. The
number of pixels available determines the resolution of the glass panel vertically and
horizontally.

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PDP basic AN2503

3

3

2.2 Panel memory characteristic

The AC PDPs provide inheren t memory characteristics [3.], [4.], as explained in the
following figures.

In general, the AC sustain square pulse voltage (V

), whose voltage Vs is smaller than the

xy

gas breakdown voltage Vbd, cannot initiate a discharge, as shown in Figure 3.

Figure 3. Memory effect - no charges

X = Vs Y = GND

Address = Vs/2

If data pulses Vd are applied to the address electrodes, while scan pulses -Vy are
sequentially applied to each Y electrode, the voltage (Vd + Vy) is higher than Vbd and a
weak discharge ignites, as shown in Figure 4.

Figure 4. Memory effect - address phase

X = Vk Y = -Vy

Charges, called wall charges (or w all voltage Vw), deposit on the dielectric lay er and reduce
the effective voltage across the gap. Then, the discharge ceases after a short time, as
shown in Figure 5.

Figure 5. Memory effect - Wall charges deposit

X = Vk Y = -Vy

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Address = Vd

Address = Vd

AN2503 PDP basic

3

When the polarity of the sustain pulse is reversed, the potential difference across the gap
becomes larger than Vbd by an amou nt determined by the wall charges, and a new large
discharge of different polarity occurs, as shown in Figure 6.

Figure 6. Memory effect - discharge

X = GND Y = Vs

Address = Vs/2

The build-up of wall charges again terminates the discharge, as shown in Figure 7.

Figure 7. Memory effect - wall charges deposit

X = GND Y = Vs

Address = Vs/2

The next discharge starts as the polarity of the sustain pulse is reversed, as shown in

Figure 8.

Figure 8. Memory effect - discharge with reverse polarity

X = Vs Y = GND

Address = Vs/2

Once the discharge is initiated, it continues as long as the sustain pulse is applied. Due to
this memory characteristic of AC PDPs, lower sustain voltage (< Vbd) pulses can maintain
the ac PDPs to light.

In other words, the p rocess of panel image d ispla ying depends on a f ormer process of panel
addressing. In fact, during the address phase a small amount of charges (wall charges)
deposit on the selected electrodes without any visible light emission. This reduces the

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PDP basic AN2503

threshold voltage for discharge, and consequently, during sustain phase only selected cells
ignite and emit light.

2.3 PDP driving sequence

The most common method of displaying one picture field is using the Address Display­Separation method (ASD).

All X electrodes are bused together and connected to a sustain driver, while the Y
electrodes are connected to susta in driver through seve ral scan ICs. One TV field is divided
into 10 subfields (SFs) in a 10-bit codification case, and each consists of a reset period, an
address period, and a display period (Figure 9).

On every subfield, each cell is addressed, sustained and erase d.

Figure 9. Subfield structure

During the reset period a slow ramping positive voltage up to 400 V followed by slow
ramping negative v oltage do wn to -150 V is applied across t he X and Y electrodes to put out
ionization and to set an identical initial condition for all the panel cells . In the address period,
the Y electrodes receive scan pulses, al ong with data pulses on the address electrodes, in
order to control wall charges in appropriate cells according to the image to be displayed .
Note that reset period and address period hav e the same dur ation in each subf ield, only the
number of sustain pulses varies among different subfields.

During sustain period, selected cells are sustained in order to display the whole image on
the panel. Gray scales are expressed by using the binary-coded light-emission-p e riod
method. The display periods are filled with trains of constant width and constant period
pulses, and their lengths are arranged according to the binary sequence, 1: 2: 4: 8: 16: 32:
64: 128: 256: 512. Therefore, gray levels of 2
expressed with an 10-bit sequence. This means that each color element has 1024 color
possible graduations and each pixel has 1024 x 1024 x 1024 = 1 billion colors. Figure 10
shows a simplified 8-bit system with 8 subfields. The subfields are weighted according to
their binary values and a typical TV field is 1/50 of a second.

10

for each color (R, G, and B) can be

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AN2503 PDP Sustain circuit

Figure 10. Subfield structure – expression of gray level

3 PDP Sustain circuit

In a Plasma Display Panel, frequent discharges are made to occur by alternately charging
each side of the panel to a critical voltage, allowing images to be displayed. This alternating
voltage is called the sustain voltage, and the sustain circuit (or sustainer) is needed to
provide it to the display [5.].

If a pixel has been driven "ON" during address period, the sustainer maintains the "ON"
state of that pixel by repeatedly discharging that pixel cell during the whole sustain period. If
a pixel has been driven "OFF" b y an a ddress driver, the voltage across the cell is nev er high
enough to cause a discharge, and the cell remains "OFF" during the sustain period.

The sustain circuit must drive all panel pixels at once. This means that the capacitance as
seen by the sustainer is typically v ery large. In a 42-inch panel with 852x480 pix e ls, th e total
capacitance of all the pixel cells, Cp, could be as much as 80 nF.

The key parameters in the sustainer study are:

● Cp - Panel equivalent capacitance

● Vs - Sustain Voltage

● f - Sustainer Switching frequency

● f

Conventional sustain circuit (half bridge topology) drives the panel directly, and thus
1/2C
ground.

- average sustainer switching frequency

av

2

f

PVS

is dissipated in the sustainer when the panel is subsequently discharged to

av

In a complete sustain cycle, each side of the panel is charged to Vs and subsequently
discharged to ground. Therefore, a total of 2CpVs

2

fav power is dissipated in a complete

sustain cycle.

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