Universal input voltage power supply for ESBT based
breaker and metering applications
Introduction
This document describes how to design a 3-phase power supply with the UC3845B PWM
driver and the new STC04IE170 ESBT as main switch. It is associated with the release of
the STEVAL-IPB001V1 demo board (see figure below). The design is a complete solution
for the 2 W single output SMPS, which is widely used as a power supply in breaker
applications. However, the design method can also be applied to an SMPS suitable for 3phase power metering applications, as it can easily be upgraded for higher output power.
In this report particular attention has been paid to the ESBT base driving circuit, where
some useful methods have been investigated to better optimize power dissipation (see
Section 6: Base driving circuit design).
The influence of the parasitic capacitances of the transformer on the ESBT is also explained
in detail (seeSection 3: Parasitic capacitances and related issues). In addition, an active
start-up circuit has been implemented on the demo board to optimize the converter
efficiency, is also described (seeSection 7: Active start-up circuit). A dedicated active
component (the Darlington Q3) has been developed to support the very high voltage
required (seeFigure 1).
Finally, the most important waveforms and thermal results are given inSection 8:
Experimental results: waveforms and Section 9: Experimental results: efficiency and special
considerations. They demonstrate the benefits of using this solution with the start-up circuit.
Refer to AN1889 for the overall design of an auxiliary power supply using an ESBT.
Ta bl e 1 lists the converter specifications and main parameters of the STEVAL-IPB001V1
demo board.
Table 1.Converter specifications and main parameters of the STEVAL-IPB001V1
demo board
SymbolDescriptionValues
V
inmin
V
inmax
V
P
out max
P
out min
out
Rectified minimum input voltage150
Rectified maximum input voltage1200
Output voltage 24V/83mA
Maximum output power2W
Minimum output power0.2W
ηConverter efficiency60%
FSwitching frequency≅ 50kHz
V
V
fl
spike
Max over voltage limited by clamping circuit150V
Reflected flyback voltage150V
A schematic diagram of the SMPS is given inFigure 1 The most relevant components are:
●HV ESBT main switch and simple driving circuit (seeSection 6: Base driving circuit
design).
●Active start-up circuit with HV bipolar Darlington (see Section 7: Active start-up circuit).
●A specially constructed transformer, with very low parasitic capacitance.
4/24
AN2454Design specifications and schematic diagram
Figure 1. Schematic diagram of the SMPS
J1
CON3
7
8
2
1
R22
10k
D1
STTH110
D2
STTH110
R26 10
C7
10nF
+
R3 1
4
2
4
R17 22
R19 1k
C9
820pF
T1
5
R15 3.3k
D4
STTH110
1
2
3
R14
18k
R20
100k
C2
+
33uF450V
C5
+
33uF 450V
C6
+
33uF 450V
C8 100p
R16 150k
R21
3.9K
R1
1M 1/8W
R4
1M 1/8W
R7
1M 1/8W
R9
1M 1/8W
R18 2.2k
R11
1M 1/8W
C10
12nF
R12
1M 1/8W
2
R13
680k
31
Q2
PN2222A
U1
2
VFB
1
COMP
8
VREF
4
RT/CT
UC3845B
7
VCC
SENSE
GND
5
OUT
1
100nF
C11
6
3
R2
10k 1/4W
R5
10k 1/4W
R8
10k 1/4W
R10
10k 1/4W
R24
10k 1/4W
R25
10k 1/4W
23
Q3
STP03D200
C1
220uF 35V
R6
10k
13
Q4
STC04IE170HP
R23
6.8
CON2
2
1
J2
C4
+
47uF 25V
D3
1N4148
+
C3
330uF 25V
D5
20V
5/24
Flyback stageAN2454
2 Flyback stage
In this section, only the main steps of the flyback stage are given. For more detailed
guidelines on Discontinuous Conduction Mode (DCM) flyback converter design, refer to
AN1889.
First, the transformer turn ratio, N
, must be calculated. NP and NS are the respective
P/NS
number of primary and secondary windings. Calculation of the turn ratio is correlated to the
maximum voltage rating of the transistor which is used as the primary switch. The voltage of
the power switch collector, V
, for flyback operation is given by:
T
Equation 1
N
P
-------
N
+()•Vfl==
V
oVFdiode,
+()V
V
oVF diode,
S
where
minarg+++=
spike
the flyback voltage
where V
VTV
is the over voltage limited by the clamp network. It must be chosen so that the
spike
N
-------
N
dcmax
P
S
total voltage across the power switch does not exceed the maximum breakdown voltage of
the power switch device (see Equation 1).
Once the V
voltage is fixed, the designer must choose the flyback voltage taking
spike
account of various voltage capabilities available from standard transistors. The higher the
flyback voltage the higher the exploitable maximum duty cycle i.e. a higher duty cycle at
fixed output power leads to a lower I
current. This improves overall efficiency of the
RMS
primary side, leading to easier design of wide input range voltage converters.
ESBTs, which have breakdown voltage capabilities as high as 2200V, offer designers a
valuable tool to simplify projects from an early stage.
For the STEVAL-IPB001V1 demo board using the STC04IE170HP switch, the following
parameters must be set:
●Margin = 200V.
●V
From Equation 1, the flyback vlotage (V
spike
= 150V.
) gives a result of 150 V. The transformer turn ratio
Once the turn ratio is calculated, the system must be stabilized to ensure that the converter
operates in discontinuous mode. Equation 3guarantees that the energy on the primary coil
will be completely transferred to the secondary coil before the next cycle occurs.
Equation 3
N
P
V
dcminTonmax
-------
N
V
S
+()T
oVF diode,
==
resetVflTreset
A safety margin of 20% is recommended to guarantee the complete demagnetization of the
primary side (see Equation 4).
Equation 4
T
–0.8T
onmaxTreset
=
S
where T
transformer inductance, and T
Combining Equation 3 and Equation 4 , T
is the maximum power-on time, T
onmax
the switching time.
S
the time needed to demagnetize the
reset
, may be calculated using Equation 5:
onmax
Equation 5
Vfl0.8T
T
onmax
------------------------------ -=
V
S
+
dcminVfl
Once output power has been set to 2 W and the desired efficiency to 60%, the operating
switching frequency must be chosen. To do this, a value of 50 kHz should be selected. It is
then necessary to calculate the primary inductance (L
6, input power (P
) may be calculated to give an approximate value which does not account
IN
) of the transformer. Using Equation
P
for losses due to the power switch, the input bridge and the rectified network.
Equation 6
UsingEquation 7, L
1
-- -
2
P
1.66P
IN
may be calculated as follows:
P
OUT
------------------------
2
LPI
•
T
1
-- -
V
P
2
------------------------- -===
S
onmax
LPT
2
S
Equation 7
V
dcmin
------------------------------------------ -
L
P
3.33TSP
2
T
onmax
2
11m H≈=
OUT
Peak current, (I
) on the primary side may be calculated usingEquation 8.
P
Equation 8
V
dcminTonmax
-------------------------------------
I
P
L
P
110mA≈=
It is also important to determine the maximum primary current, I
and maximum secondary current, I
rms(secondary)
, (seeEquation 10)to obtain correct
dimensions for the wire size of the primary windings.
rms(primary)
, (see Equation 9)
7/24
Parasitic capacitances and related issuesAN2454
)
)
Equation 9
I
T
P
onmax
I
rms primary()
-------
------------------ -40m A≈=
T
3
S
Equation 10
I
T
S
reset
I
rmsondarysec()
-------
---------------240mA≈=
T
3
S
3 Parasitic capacitances and related issues
In a flyback converter stage it is important to take into account the parasitic capacitances
since their influence may affect the correct operation of the converter itself. Figure 1 shows
the main schematic diagram of a flyback converter and Figure 2 shows the small signal
equivalentmodel.
The parasitic capacitances between the ESBT collector and ground are mainly due to three
components (see Figure 2):
●C
●C
●C
Usually transistors are mounted on a heat-sink by interposing an insulation layer. The heatsink has to be grounded either for safety reasons, or to minimize the RFI so that C
are in the same range as C
C
power dissipation. Large parasitic capacitances may produce noise problems (origin
ringing). Parasitic capacitance are worse at higher input voltages, like those observed in 3phase power supply.
, the primary inter-winding capacitance;
1
, the intrinsic capacitance of the ESBT between its collector and source;
2
, the parasitic capacitance between the collector of the ESBT and the heat-sink.
3
results
and C2. The resulting total parasitic capacitance (C) is equal to
+ C2 + C3. C may be large enough to produce additional and non-negligible switch-on
1
1
3
Figure 2.Small signal equivalent circuit
T
I nsula ion Pad
Heatsink
ESBT
+
Cbus
ESBT
a
The flyback converter of the demo is operated in DCM, thus, before the end of the off-time
the secondary of the transformer has discharged all energy stored in the primary inductance
during the previous cycle.
8/24
C1
C3
C2
T
Ic1
T
C1
Heatsink
ESBT
Ic
b
Ic2 Ic3
C2
C3
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