ST AN2423 APPLICATION NOTE
April 2007 Rev 1 1/22
AN2423
Application note
STMPE2401 - Port expander
keypad controller
Introduction
STMPE2401 is the first in the family of STMicroelectronic’s expander logic products. The
principle of a basic expander logic is the provision of additional I/Os that can be used by the
host processor to implement additional features such as expanding the number of control
signals and mixed signal lines or controlling numerous peripherals.
In addition to the above mentioned basic features, STMPE2401 comes with integrated
intelligence to implement advanced features like Keypad scanning and PWM control. This
application note details the setup and programming of the integrated keypad matrix
controller in STMPE2401.
STMPE2401 can be widely used in the fields of Mobile Communications, Portable media
players, Game console, Mobile Phones, Smart Phones, Consumer Electronics and
computer peripherals like state-of-the-art printers, and Advanced embedded systems.
This application note explains the setup and programming of the integrated keypad matrix
controller in STMPE2401. This document also includes a brief description of the timing
constraints and an example of the programming sequence to illustrate the keypad register
configuration for effective functioning of the Keypad controller.
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Contents AN2423
2/22
Contents
1 Advantages of a STMPE2401 keypad matrix controller . . . . . . . . . . . . . 4
2 Device setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Operation modes and clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Keypad controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 Interrupt Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2 Interrupt enable mask register (IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3 Interrupt status register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7 Driving and sensing of keypad matrix . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1 Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 Timing constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.1 Decoding of multiple keys (keypad matrix) . . . . . . . . . . . . . . . . . . . . . . . . 18
8.2 Ghost key handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.3 Programming sequence example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.4 Interrupt servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AN2423 List of tables
3/22
List of tables
Table 1. Valid STMPE2401 slave address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. SYSCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. SYSCON description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Register map for keypad controller module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. KPC_col register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. KPC_col description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. KPC_row_msb register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. KPC_row_msb description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. KPC_row_Isb register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. KPC_row_Isb description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 11. KPC_ctrl_msb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 12. KPC_ctrl_msb description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 13. KPC_ctrl_lsb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 14. KPC_ctrl_lsb description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 15. KPC_data_byte0_register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 16. KPC_data_byte0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 17. KPC_data_byte1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 18. KPC_data_byte1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 19. KPC_data_byte2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 20. KPC_data_byte2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 21. Interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 22. Interrupt control description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 23. Interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 24. Interrupt enable description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 25. Interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 26. Interrupt status description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 27. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Advantages of a STMPE2401 keypad matrix controller AN2423
4/22
1 Advantages of a STMPE2401 keypad matrix
controller
● Low CPU utilization (no polling)
● Low power consumption
● Wake-up feature from sleep mode to reduce power consumption
● Simple driver software
● Simple connection to CPU for configuration and communication
● Combinational keys to enhance gaming experience
● Application: mobile phone keypads, all-in-one printers, embedded systems, etc.
2 Device setup and configuration
The device operates at 1.8 V VCC. The clock can be generated through a 32 KHz crystal
connected across XTALIN, XTALOUT pins or through an external clock on XTALIN pin. The
clock frequency for normal operation should not exceed 32 KHz. The Reset pin should be
pulled high for the device to come out of reset and operate in the normal operating mode.
The device can be accessed through the I
2
C interface and up to four STMPE2401 devices
can be connected to the same I
2
C bus. STMPE2401 supports 7-bit addressing as per the
Philip I
2
C specification Ver2.1. The slave address is selected by the state of two pins
(GPIO15 and GPIO23). The state of the pins is latched into STMPE2401 at power on and
these address settings are retained until the power is switched off. The slave address can
be changed and latched in again using the soft_reset option in the SYSCON register.
The I
2
C Read/Write is done byte by byte. The R/W bit is added as the LSB to the 7-bit slave
address to make up one byte to be sent through the I
2
C interface from the Master.
Table 1. Valid STMPE2401 slave address
ADDR1
(GPIO23)
ADDR0
(GPIO15)
7-bit slave
addressing
8-bit format to be
used (including R/W
bit in LSB)
0 0 42h (1000010b) 84h
0 1 43h (1000011b) 86h
1 0 44h (1000100b) 88h
1 1 45h (1000101b) 8Ah
AN2423 Keypad controller
5/22
Figure 1. I
2
C Read/Write protocol
Once the slave address is configured and responds correctly, the internal registers can be
accessed through I
2
C read and write commands.
At power-up all GPIOs function as inputs and by default the interrupt is configured as an
Active Low Level interrupt. The interrupt pin will remain low irrespective of the Interrupt
settings until the Global Interrupt bit (ICR register) is set to '1'.
3 Keypad controller
STMPE2401 comes with an integrated Keypad controller that can control a maximum of
12x8 key matrix. A key press interrupt is generated when a new set of key data is loaded. In
this way, precious CPU resources can be saved by using interrupt servicing instead of
polling.
The main operations of the keypad controller are regulated by four dedicated-key controllers
that support up to four simultaneous dedicated key presses, a key scan controller, and two
normal key controllers. These devices support a maximum of 12x8 key matrix with detection
of two simultaneous key presses.The scanning of each individual row output and column
input can be enabled or masked to support a key matrix of variable size from 1x1 to 12x8.
The first four column inputs can be configured as dedicated keys. If less than 12 columns or
8 rows are used, the rest of the pins can be used for alternate functions like CLKOUT,
Rotator, or GPIO functions.
The operation of the keypad controller is enabled by the SCAN bit of KPC_ctrl register. The
key detection operation always starts with the "any-key" detection whereby the row outputs
are all driven 'LOW' to allow any key press to be sensed.
Master
Slave
One Byte
Read
Multiple
Byte Read
One Byte
Write
Multiple
Byte Write
Keypad controller AN2423
6/22
Every key activity detected will be de-bounced for a period that can be set through the
KPC_ctrl register before a key press or key release is confirmed and updated into the output
FIFO. The key data, indicating the key coordinates and its status (up or down), is loaded into
the FIFO at the end of a specified number of scanning cycles (set through the
KPC_row_msb register). An interrupt will be generated when a new set of key data is
loaded. The FIFO has a capacity of four sets of key data. Each set of key data consists of
three bytes of information when any of the four dedicated keys is enabled. It is reduced to
two bytes when no dedicated key is enabled. If the FIFO is filled up before its contents are
read, a FIFO overflow interrupt is generated. The FIFO continues to hold its contents but
forbids loading of any new key data until the old data is read.
Figure 2. Block diagram of key pad controller
The block diagram shows the various inputs to the Keypad Controller block and outputs from
the Keypad controller. The flowchart in Figure 3 describes the Key scan, key press detection
and output FIFO loading operations in the Keypad controller.
Clk_32KH z
KPC_COL
KPC_ROW
DKey0~3
(KPC_CTRL)
In pu t S e le cto r
Key Scan
Controller
SCAN & HOTKEY
(K PC _ C TR L )
Dedicated K ey
Controller 0
Dedicated K ey
Controller 1
Dedicated K ey
Controller 2
Dedicated K ey
Controller 3
Normal Key
Controller 0
Normal Key
Controller 2
Output Data FIFO
row_output[1 1:0]
DB_0~7
(K PC _ C TR L )
column_input[7:0]
kp c _ in t
kpc_of
i2c
_
rd
_
strobe i2c
_
rd
_
data[7:0]
: Control Register
i2c_w r_data[7:0]
i2c _w r_ strob e
Int_C lk
kpc_wakeup
AN2423 Keypad controller
7/22
Figure 3. Flowchart of key scan controller operation
Reset
Increm ent
scan count
A ny data ready
for w rite?
Y
Scan count =
register setting?
Y
N
W rite ready data
to o u tpu t F IF O
A cknow ledge data w rite
& generate interrupt
N
A ny key dow n?
Y
Is norm al key
de-bounce buffer 1
em pty?
Y
Is norm al key
de-bounce buffer 3
em pty?
Y
N
W rite d ata to d e -
bo un ce b uffer 1
N
C o lu m n in p u t
detection
N
Start
Is the key
recorded in the de-
bo un ce b uffer
alread
y
?
Y
W rite d ata to de -
b oun ce b uffer 3
A ny m ore key
down?
Y
End
N
Y
T ran sitio n to
sleep m ode
SCAN = ‘1’?
N
Y
Set scan
count = 0
N
Drive row
outputs
A ny key down?
Drive one
row o ut
p
ut
C o lu m n in pu t
detection
Next row?
A ny row output
to d riv e?
N
Y
Y
N
N
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