ST AN2282 Application note
AN2282
APPLICATION NOTE
TCP/IP Over Ethernet Connectivity
with the STR710
Introduction
With the ever-increasing success of the Internet, many applications with networking features
are being developed making the TCP/IP protocol a global standard for communication both
for the Internet and local area networks. In a normal scenario, a microcontroller inside a
home appliance or process controller of an industrial distributed control system is not
directly connected to the Internet but instead is a host of a home or industrial local area
network using an Ethernet protocol.
This application note describes a method to provide TCP/IP over Ethernet connectivity to an
STR710-based solution and, as an example, an application layer has been included in the
solution firmware. The application is a server that waits for a Client request. The successful
or unsuccessful processing notification is sent back to the Client. The solution block diagram
is showed in Figure 1. The MAC layer is implemented using the third part CIRRUS LOGIC
Crystal LANTM CS8900A 10-baseT Ethernet controller because of its ISA bus interface.
The STR7 EMI interface can be interfaced with an ISA bus by simple Glue Logic.
®
Figure 1. Solution block diagram
EMI ISA
STR7
RS232 USB
Glue
Logic
CS8900A
RJ45
February 2006 Rev 1 1/19
www.st.com
Contents AN2282
Contents
1 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 The STR710 microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 EMI-ISA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Ethernet controller driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 Low Level Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.2 Initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.3 Ethernet packet management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Device driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 TCP/IP layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Application layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
AN2282 Hardware
1 Hardware
The target microcontroller for the solution is the STR710 with TQFP144 package to have the
EMI bus available for Ethernet controller interfacing. The hardware includes also a RS232
interface for SLIP implementation.
1.1 The STR710 microcontroller
The STR710 is a 16-/32-bit microcontroller based on the ARM7TDMI RISC microprocessor.
It combines the high performance of the ARM® CPU with an extensive range of peripheral
functions and enhanced I/O capabilities. The microcontroller has on-chip high-speed single
voltage FLASH memory and high-speed RAM, since both memories are mounted on an
ARM® CPU native bus the STR710 maximizes the CPU calculation speed. The STR710
has an embedded ARM® core and is therefore compatible with all ARM tools and software.
The 144-pin version (used for the solution in the present AN) has a non-multiplexed 16-bit
data/24-bit address bus available that supports four 16-Mbyte banks of external memory
(EMI). Wait states are programmable individually for each bank allowing different memory
types (Flash, EPROM, ROM, SRAM etc.) to be used to store programs or data. Later on, the
way of interfacing the EMI with an ISA Ethernet controller will be shown.
3/19
Hardware AN2282
The STR710 main features are as follows [1]:
● Memories:
– Up to 272 KB (256+16) FLASH program memory
– Up to 64 KB RAM
– EMI for up to 4 banks with 16MB of addressing space each (64MB total)
– Multi-boot capability
● Clock, Reset and Supply Management:
– 3.3V supply and I/O interface
– Embedded 1.8V voltage regulator for core supply
– Up to 50 MHz CPU operating frequency with external clock source and internal
PLL
– Real-time clock for clock-calendar function
– 4 power saving modes: SLOW, WAIT, STOP and STANDBY
● Nested Interrupt Controller:
– Fast interrupt handling with multiple vectors
– 32 vectors with 16 IRQ priority levels
– 2 maskable FIQ sources
● I/O Ports:
– Up to 48 I/O ports
● 5 Timers:
– 16-bit watchdog timer
– Four 16-bit timers each with: 2 input captures, 2 output compares, PWM and
pulses counter mode
● 10 Communication Interfaces:
– 2 I2C interfaces (1 multiplexed with SPI)
–4 UART
– Smart card ISO7816-3 interface on UART1
– 2 BSPI
– CAN interface (2.0B Active)
– Full speed USB (12Mbits/sec)
– HDLC interface
● 4 Channel 12-bit A/D Converter:
– Sampling frequency up to 1 KHz
– Conversion range: 0 to 2.5V
● Development Tools Support:
– JTAG with debug mode trigger request
4/19
AN2282 Hardware
1.2 EMI-ISA Interface
The CS8900A Ethernet controller includes a direct interface to the ISA bus. The ISA bus
(Industry Standard Architecture) has been the first standard in the IBM PC architecture;
detailed information and specification can be found in the following documents:
● EISA Specification, Version 3.12. This document includes specifications for ISA as well
as the "Extended Industry Standard Architecture" that defines a 32-bit extension to the
ISA [2].
● PS/2 Technical Reference - AT Bus Systems. This document includes signal definitions
and timing diagrams for the ISA bus used in some IBM computers [3].
At the same time, the CS8900A can be used for cost-effective, full-duplex Ethernet solutions
for non-ISA architectures as referenced in the application note AN83 from CIRRUS LOGIC®
Crystal LANTM CS8900A ETHERNET CONTROLLER TECHNICAL REFERENCE
MANUAL [4].
The reference schematic of the hardware interface between EMI and the ISA bus is shown
in Figure 2. The Chip Select 2 of EMI is used to address the Ethernet Controller; moreover
address line A23 of EMI is used together with CS.2 to enable read/write operations on
CS8900A. From a firmware point of view, this means that the Ethernet Controller is mapped
at base address 0x64800000; in this way the CS.2 is not committed only by the CS8900A
but it also can be used to address other devices.
Figure 2. EMI-ISA glue logic reference schematic
STR7 EMI Control Bus
STR7 EMI Address Bus
STR7 EMI Data Bus
CS.2
nRD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
nWR
WE0
WE1
U15
NOT
U7
+3V3 +3V3
1
14
1
VDD
2
13
2
13
3
12
3
12
4
11
4
11
5
10
5
10
6
9
6
9
7 8
GND 8
M74HC08TTR-TTSOP14
12
nA23
IC5
nA23
1
2
CS.2 IOR
3
4
nAE
5
nWR
6
MEMW
7 8
GND
A0
A1
A2
A3
A4
A5
A6
A7
GND
GND
A8
A9
A10
A11
A12
GND
14
1A
vcc
1B
13
1Y
4B
12
4A
11
2A
4Y
2B
10
2Y
3B
9
A12
3A
GND 3Y
10
10
IOW
74LVC32ATTR-TSSOP14
IC101
1
VCC
OE
2
D0
Q0
3
D1
Q1
4
D2
Q2
5
D3
Q3
6
D4
Q4
7
D5
Q5
8
D6
Q6
9
D7LEQ7
GND
74LVX573T
IC100
1
VCC
OE
2
D0
Q0
3
D1
Q1
4
D2
Q2
5
D3
Q3
6
D4
Q4
7
D5
Q5
8
D6
Q6
9
D7LEQ7
GND
74LVX573T
nRD
nAE
MEMR
20
+3.3V
19
QA0
18
QA1
17
QA2
16
QA3
QA4
15
QA5
14
QA6
13
12
QA7
CS.2
11
20
+3.3V
19
QA8
18
QA9
17
QA10
16
QA11
15
QA12
14
13
12
11
CS.2
MEMR
A12
IC6
1
1A
vcc
2
1B
3
1Y
4B
4A
4
2A
4Y
5
2B
6
2Y
3B
3A
7 8
GND 3Y
74LVC32ATTR-TSSOP14
NIC SA13 to SA19, AEN,
CHIPSEL Grounded
+3V3
MEMW
14
13
12
11
10
9
IOW
MEMR
IOR
NIC ISA Control Bus
NIC nSBHE
NIC ISA Address Bus
NIC ISA Data Bus
The CS8900A can be accessed both in ISA IO mode and ISA memory mode; the glue logic
is designed to allow both access modes. The Address line A12 separates IO address space
and memory address space. When A12 is low the Ethernet Controller is accessed in IO
5/19
Hardware AN2282
mode and when A12 is high it is accessed in memory mode, so memory mode base
address register of Ethernet controller must be programmed with a value 0x1000. The IO
mode default value of CS8900A (0x0300) is used as IO mode base address. The
corresponding firmware addresses are 0x64800300 for IO mode operations and
0x64801000 for memory mode operations. For a detailed description of IO and memory
access modes refer to the CS8900A datasheet [5].
ISA Bus timing constraints must be satisfied to guarantee correct access to Ethernet
controller registers; Figures 3 and 4 show the CS8900A bus timing diagrams. Configuring
the MCLK of STR7 with the value 48 MHz, the EMI CS.2 must be configured with at least 7
wait states; Figures 5 and 6 show the STR7 EMI bus timing diagrams. 8 wait states are used
to guarantee a safe access.
Figure 3. CS8900A read timing diagram
DIRECTION:
IN or OUT of chip
SA [15:0],
AEN, SBHE
IOCS16
10 nSec
IOR
SD [15:0]
Valid Address
t
IOR1
135 nSec
Figure 4. CS8900A write timing diagram
SA [15:0],
AEN, SBHE
IOCS16
20 nSec
IOW
SD [15:0]
Valid Address
t
IOW1
10 nSec
110 nSec
0 nSec
30 nSec
Valid Data
0 nSec
Valid Data In
t
IOW7
t
IOR5
t
IOW6
t
IOW4
IN
OUT
IN
OUT
DIRECTION:
IN or OUT of chip
IN
OUT
IN
IN
6/19
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