ST AN2269 APPLICATION NOTE

AN2269

Application Note

Using the ST8024 Smartcard Interface

Introduction

This application note provides information and suggestions for the optimal use and
performance of the ST8024 Smartcard Interface, including PCB layout, external component
placement, and connections (see

The ST8024 is a smart card interface designed to minimize microprocessor hardware and
software complexity in all applications that require a smar t card (e.g., Set Top Box,
Electronic Payment, Pay TV, and Identification cards). It was devel oped in accordance with
New Digital Systems (NDS) conditional access requirements, and implements all of the
blocks and procedures for card activation/deactivation and checking (see

Figure 1. ST8024 Internal Block Diagram

ST8024 Application Hardware Guidelines on page 16

Figure 1

).

).

PORADJ

OFF

RSTIN

CMDV

CC

5V/3V

CLKDIV1

CLKDIV2

XTAL1
XTAL2

AUX1UC

AUX2UC

I/O UC

V

DD

21 6 7

Supply

Internal

Reference

Voltage

Supervisor

Clock

Circuitry

Oscillator

Alarm

En4

CLK

18
23

20
19

3

1

2

24
25

27

28

26

V

REF

Sequencer

En3

V

DDP

ST8024

Oscillator 2.5MHz

En1

Thermal

Protection

S1

Step-up

Converter

Internal

CLKUP

En2

Generator

PV

CC

En5

RST

Buffer

En4

Clock
Buffer

I/O T ransceiver

I/O T ransceiver

I/O T ransceiver

S2

5

P

4

GND

V

8

UP

V

17

V

CC

CC

CGND

14

RST

16

CLK

15

PRES

10

PRES

9

AUX1

13

AUX2

12

I/O

11

22
GND

AI11884

February 2006 Rev 1 1/25

www.st.com

Table of Contents AN2269 - Application Note

Table of Contents

1 Activation/Deactivation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Card Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Emergency Deactivation/Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 PORAD J VDD Undervoltage without External Resistor Bridge . . . . . . . . . 7

3.2 PORAD J V

3.3 Fault On Card Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 V

3.5 V

3.6 Over-Temperature Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Short Circuit Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

CC

Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DDP

Undervoltage with External Divider . . . . . . . . . . . . . . . . . . . 9

DD

4 ST8024 Application Hardware Guidelines . . . . . . . . . . . . . . . . . . . . . . 16

4.1 Power Supply Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2 Clock Section Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3 Smart Card Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2/25

AN2269 - Application Note List of Figures

List of Figures

Figure 1. ST8024 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. ST8024 Activation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Deactivation Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. CLKDIV Change Clock Duty Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. ST8024 Automatic Deactivation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. External Resistor Bridge Applied to PORADJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. V
Figure 8. V

TH(ext) rise
TH(ext) fall

Figure 9. Card Extraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 10. ST8024 Activation Sequence (after t

Figure 11. ST8024 Current Supply Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 12. I

Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

SC

Figure 13. Deactivation Caused By V

Figure 14. ST8024 Application PCB Top Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 15. ST8024 Application PCB Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 16. Step-up Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 17. ST8024 Application PCB Storage and Pumping Capacitors . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 18. ST8024 Application PCB Crystal (XTAL) Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 19. ST8024 Application PCB Smart Card Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 20. Ripple on V

Figure 21. ST8024 Application PCB Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

(External Rising Threshold Voltage on VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . 10

(External Falling Thres hold on VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

debounce

Drop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DDP

Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

CC

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3/25

Activation/Deactivation Sequence AN2269 - Application Note

1 Activation/Deactivation Sequence

The core of the ST8024 is the sequencer (shown in
coordinate the Enable signals for the activation and deactivation sequence as well as check
for possible fault conditions. This because the smart card is basically a microcontroller and
needs to be activated/deactivated by a correct sequence as required by the ISO/IEC7816
standard. The ST8024 activation and deactivation sequences are shown in

Figure 3 on page 5
Figure 2

goes low. The activation sequence starts and the first block to be enabled is the step-up
converter (V
allows the card software to start.

Figure 3

executes an automatic deactivation sequence, finishing in the inactive state after t
(deactivation time).

Figure 2. ST8024 Activation Sequence

shows that the PRES condition is true (PRES = low or PRES = high), and CM DVcc

shows the deactivation sequence (when the CMDVcc goes high). The circuit

, respectively. Please refer to the ST8024 datasheet for details.

), linked to En1 (see

UP

Figure 1

), while the last enabled signal is the RST that

Figure 1 on page 1

) that must

Figure 2

de

and

4/25

AN2269 - Application Note Activation/Deactivation Sequence

Figure 3. Deactivation Sequence

5/25

Card Clock AN2269 - Application Note

2 Card Clock

The card clock signal (CLK) is present on the CLK pin when the ST8024 is activated; it is
linked with the internal En4 signal (see
according to the settings in

Table 1

According to the ISO/IEC7816 specifications, the CLK duty cycle must be guaranteed
between 45% and 55%, even when the status of CLOCKDIV1 or CLOCKDIV2 changes.

Figure 4

shows how the ST8024 ensures duty cycle accuracy by waiting for completion of a

whole clock cycle before changing the frequency (CLKDIV1 change, rising edge of CH2).
The output Duty Cycle is 50%±5%, even if the Clock Division changes.

The card clock signal (CLK) can be obtained by connecting a crystal (“XTAL”) between the
XTAL1 and XTAL2 pins, or by an external signal applied to the XTAL1 pin. In this case the
XTAL2 pin must be left floating. The external signal voltage level must be limited between
GND and V

Table 1. CLK Division Factor

voltage.

DD

Figure 1 on page 1

.

) and its frequency is obtained

CLKDIV1 CLKDIV2 f

0 0 1/8 f
011/4 f
1 1 1/2 f
10f

Figure 4. CLKDIV Change Clock Duty Cycle

clk

Xtal

XtalL

Xtal

Xtal

Legend:

1. CH1 = Output CLK Waveform

2. CH2 = CLKDIV1 Pin

3. Conditions: V

4. Mode: ACTIVE

5. f

= 10MHz; CLKDIV2 = 0V

XTAL

= 3.3V; V

DD

6/25

= 5V; 5/3V = H

DDP

AN2269 - Application Note Emergency Deactivation/Fault Detection

3 Emergency Deactivation/Fault Detection

ST8024 is equipped with a fault detection circuitry which monitors the following conditions
(see

Figure 1 on page 1

● V

● Fault on card removal,

● V

● V

● Over-Temperature protection.

undervoltage,

DD

Short circuit protection,

CC

drop, and

DDP

3.1 PORADJ VDD Underv oltage without External Resistor Br idge

The ST8024 logic circuitry is supplied by VDD. In order to avoid voltage spikes that could
cause damage, or malfunction of the device and/or card, a voltage supervisor block is
embedded (see
(Falling Threshold Voltage on V
deactivation sequence and V

As V

goes higher than V

DD

100mV, typ), after a certain amount of time (t
reset pulse width, 8ms typ, see
sequence starts and V
to GND to avoid noise capture is recommended.

Figure 1

):

). This block monitors VDD and when it gets lower than V

, 2.45V, typ), the supervisor immediately starts the

DD

goes low.

CC

+ V

TH2

Figure 5 on page 8

goes high. The PORADJ pin can be left floating, but connecting it

CC

HYS2

, (V

is the Hysteresis of threshold voltage,

HYS2

+ t

w

debounce

, where tw is the internal power-on

), CMDVcc goes low. The activation

TH2

Note: See

Fault On Card Removal on page 12

for t

debounce

feature details.

7/25

Emergency Deactivation/Fault Detection AN2269 - Application Note

Figure 5. ST8024 Automatic Deactivation Sequence

Note: Deactivation: V

Activation: As V

Legend:

1. CH1 = CMDVcc

2. CH2 = V

3. CH3 = OFF

4. CH4 = V

5. Conditions: VDD = 3.3V; V

6. Mode: ACTIVE

7. f

CC

DD

= 10MHz; CLKDIV2 = 0V

XTAL

≈ 2.393V.

TH2

≥ V

DD

+ V

TH2

= 5V; 5/3V = H

DDP

(≈ 2.498V) AND CMDVcc goes low, VCC goes high.

HYS2

8/25