ST AN2197 Application note

AN2197

APPLICATION NOTE

Guidelines for migrating ST72F324 & ST72F321 applications to ST72F324B, ST72F321B or ST72F325

Introduction

This application note provides information on using ST72F321B, ST72F324B and ST72F325 microcontroller devices in applications originally designed for the ST72F324 and ST72F321 series.

Table 1.	Migration cross-reference table
FROM		TO	Description
		ST72F324B	8K to 32K Flash, 32-pin and 44-pin
ST72F324
		ST72F325	16K to 32K Flash, 32-pin and 44-pin
			with I²C, Auto Reload Timer and Clock Security System
		ST72F321B	32K to 60K Flash, 44-pin and 64-pin,
			with I²C, Auto Reload Timer
ST72F321
		ST72F325	32K to 60K Flash, 44-pin and 64-pin
			with I²C, Auto Reload Timer and Clock Security System

Note: Use ST72F325 if your application requires CSS (Clock Security System).

	Rev 1
October 2005	1/13

www.st.com

			AN2187
	Contents
1	ST72F324 Migration: feature overview . . . . . . . . . . . . . . . . . . . . . . .		. . . . . 3
2	ST72F321 Migration: feature overview . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 4
3	Feature compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 5
	3.1	Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 5
	3.2	VDD Rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 5
	3.3	Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 5
	3.4	Oscillator pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 6
	3.5	Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 6
4	Performance improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 7
5	New features and peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 8
	5.1	Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 8
6	Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 9
	6.1	Register Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 9
	6.2	Register Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 10

6.2.1 SICSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7 Limitations summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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AN2187

1 ST72F324 Migration: feature overview

1 ST72F324 Migration: feature overview

	Table 2.	ST72F324 migration: feature overview
	Feature 1)		ST72F324	ST72F324B	ST72F325
	Package		TQFP44 / SDIP42 /	-	-
			TQFP32 / SDIP32
	Program Memory		8 to 32K Flash	-	16 to 32K Flash
	Operating Supply		3.8 V to 5.5V	-	-
	Register Map		128 bytes	-	-
	I/Os (High sink)		32/24 pins	-	-
	Power saving Modes		Slow / Wait / Active Halt /	- 2)	- 2)
			Halt
	Nested Interrupts		Yes	-	-
	MCC / RTC		Yes	-	-
	Watchdog		Yes	-	-
	16-bit Timer		2 Timers (3 / 3 / 2)	-	-
	(OC / IC / PWM)
	8-bit PWMART		No	-	1 Timer
	(OC / IC / PWM)				(4 / 0 / 4)
	SPI		Yes	-	-
	SCI		Yes	-	-
	I2C		No	-	Yes
	ADC		Yes (10-bit)	- 3)	- 3)
	LVD		3 Levels (No change)	-	-
	CSS		No	-	Yes
	ICC mode		39-pulse	39-pulse (32k Flash)	39-pulse
				36-pulse (8/16k Flash)
	Development tools		ST7MDT20x-EMU3 and ST7MTD20-DVP3
				ST7232X-SK/RAIS
	Programming tools4)		ST7MDT20x-EPB and ST7MTD20-DVP3

“-” stands for: No change vs. ST72F324, fully compatible with existing development

Note 1: Refer to the corresponding datasheets for more information.

Note 2: Exit from Active Halt available with external interrupts (see Section 7)

Note 3: improved ADC accuracy

Note 4: Go to http://www.st.com for information on third-party tools.

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2 ST72F321 Migration: feature overview

AN2187

2 ST72F321 Migration: feature overview

	Table 3.	ST72F321 Migration: feature overview
	Feature 1)		ST72F321	ST72F321B	ST72F325
	Package		TQFP44 / TQFP64	-	-
	Program Memory		32K to 60KFlash	-	16K to 60K Flash
	Operating Supply		3.8 V to 5.5V	-	-
	Register Map		128 bytes	-	-
	I/Os (High sink)		48/32 pins	-	-
	Power saving Modes		Slow / Wait / Active Halt /	- 2)	- 2)
			Halt
	Nested Interrupts		Yes	-	-
	MCC / RTC		Yes	-	-
	Watchdog		Yes	-	-
	16-bit Timer		2 Timers (3 / 3 / 2)	-	-
	(OC / IC / PWM)
	8-bit PWMART		1 Timer (4 / 0 / 4)	-	-
	(OC / IC / PWM)
	SPI		Yes	-	-
	SCI		Yes	-	-
	I2C		Yes	-	-
	ADC		Yes (10-bit)	- 3)	- 3)
	LVD		3 Levels	-	-
	CSS		No	-	Yes
	Development tools		ST7MDT20x-EMU3 and ST7MTD20-DVP3
				ST7232X-SK/RAIS
	Programming tools4)		ST7MDT20x-EPB and ST7MTD20-DVP3

“-” stands for: No change vs. ST72F321, fully compatible with existing development

Note 1: Refer to the corresponding datasheets for more information.

Note 2: Exit from Active Halt available with external interrupts (see Section 7)

Note 3: improved ADC accuracy

Note 4: Go to http://www.st.com for information on third-party tools.

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