ST AN2169 Application note

AN2169

Application note

Porting an application from the ST10F168 to the ST10F276

Introduction

The ST10F276 is a new derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. This document aims to describe the differences between the ST10F168 and ST10F276 and is intended for hardware or software designers who are adapting existing applications based on the ST10F168 to the ST10F276.

This document will present the modified functionalities of the ST10F276, then the new ones before looking at the modified and new registers. For each part, the differences with the ST10F168 that have an impact will be shown and some advice on the way they can be handled will be given.

July 2006

Rev 1

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www.st.com

AN2169

Contents

1 Modified features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 Pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1.1 Pin-out modification summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.2 Pin 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.3 Pins 143 & 144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.4 Pin 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.5 Pin 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Maximum CPU frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2.2 software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.5 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.5.1 Hardware / Software impact: conversion timing control . . . . . . . . . . . . . . . . . 10 1.5.2 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5.3 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.6 PLL and on-chip main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2	New functionalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	2.1 CAN module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14

2.1.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 MAC unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4 Additional X-peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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2.4.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5 New multiplexer for X-interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

	2.6	Programmable divider on CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
		2.6.1	Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
		2.6.2	Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
3	Modified registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			19

3.1 WDTCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2 PICON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3 IDCHIP register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.1 Hardware Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3.2 Software Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4 New registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1 XPERCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2 XPEREMU register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.1 Hardware Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.2 Software Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3	EXISEL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25
4.4	Additional Ports Input Control: XPICON register . . . . . . . . . . . . . . . . . . . . .		26
	4.4.1	Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	4.4.2	Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26

4.5 XMISC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.5.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.6 Emulation dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.6.1 Hardware impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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AN2169

4.6.2 Software impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		29
	5.1	DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29

5.1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.2 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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AN2169

Modified features

1 Modified features

1.1Pin-out

1.1.1Pin-out modification summary

Table 1 below summarizes the modifications made in the pin-out.

Table 1.		Pin-out modification summary
Pin no.			ST10F276 pin function			ST10F168 pin function
		HOLD External Master Hold request Input			HOLD External Master Hold request Input
6 (P6.5)		SCLK1 SSC1 Master Clock Output
		SCLK1 SSC1 Slave Clock Input
		HLDA Hold Acknowledge Output			HLDA Hold Acknowledge Output
7 (P6.6)		MTSR1 SS1 Master Transmit
		MTSR1 SS1 Slave Receive O/I
		BREQ Bus Request Output			BREQ Bus Request Output
8 (P6.7)		MRST1 SSC1 Master receive
		MRST1 SSC1 Slave Transmit I/O
		CC16IO: CAPCOM2 CC16 Capture-In			CC16IO: CAPCOM2 CC16 Capture-In
9 (P8.0)		CC16IO: CAPCOM2 CC16 Compare-Out			CC16IO: CAPCOM2 CC16 Compare-Out
		XPWM0: PWM1 Channel0 Output
12		CC19IO: CAPCOM2 CC19 Capture-In			CC19IO: CAPCOM2 CC19 Capture-In
		CC19IO: CAPCOM2 CC19 Compare-Out			CC19IO: CAPCOM2 CC19 Compare-Out
(P8.3)
		XPWM3: PWM1Channel3 Output
		CC22IO: CAPCOM2 CC22 Capture-In			CC22IO: CAPCOM2 CC22 Capture-In
15(P8.6)		CC22IO: CAPCOM2 CC22 Compare-Out			CC22IO: CAPCOM2 CC22 Compare-Out
		RXD1: ASC1 Data Input(Asynch) or I/O(Synch)
		CC23IO: CAPCOM2 CC23 Capture-In			CC23IO: CAPCOM2 CC23 Capture-In
16(P8.7)		CC23IO: CAPCOM2 CC23 Compare-Out			CC23IO: CAPCOM2 CC23 Compare-Out
		TXD1: ASC1Clock/Data output(Asyn/Syn)
89		A20 segment address line			A20 segment address line
		CAN2_RxD CAN2 Receive Data Input
(P4.4)
		SCL I2C Interface Serial Clock
90		A21 segment address line			A21 segment address line
		CAN1_RxD CAN1 Receive Data Input			CAN_RxD CAN Receive Data Input
(P4.5)
		CAN2_RXD CAN2 Receive Data Input
		A22 segment address line			A22 segment address line
91(P4.6)		CAN1_TxD CAN1 TransmitData Output			CAN_TxD CAN TransmitData Output
		CAN2_TXD CAN2 TransmitData Output
92		A23 segment address line			A23 segment address line
		CAN2_TxD CAN2 TransmitData Output
(P4.7)
		SDA I2C Interface Serial Data
			& VSTBY
99		EA			EA
143		XTAL3			Vss

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Modified features			AN2169
	Pin no.	ST10F276 pin function	ST10F168 pin function
	144	XTAL4	VDD Digital supply voltage
	84	RPD	Vpp / RPD
	56	V18 1.8v decoupling pin	VDD digital supply voltage

1.1.2Pin 99

On the ST10F168, pin 99 is EA and used upon reset to select the start from internal flash or external memory.

Now, on the ST10F276, it has an the additional function of providing the 5V power supply to the device in standby mode (new power saving mode) and is therefore named EA - VSTBY.

Hardware impact

For an application not using the Stand by mode, no change is required on the PCB. However,

for the application to use it , the EA - VSTBY pin must be separated from the common 5v and have a specific supply path.

Software impact

None.

1.1.3Pins 143 & 144

These pins were a Vss-VDD pair in the ST10F168. Now, on the ST10F276, they are used as XTAL3-XTAL4 pair for connection to an optional 32Khz crystal to clock the device during powerdown.

Hardware impact

PCB must be redesigned. In case the optional 32Khz is not used, XTAL3 must be linked to ground as it was in the ST10F168 but XTAL4 shall be left open.

Software impact

In case the optional 32Khz is not used, the bit OFF32 of the RTCCON register shall be set. Prior to setting the OFF32 bit in RTCCON register, the RTC must be enabled by setting RTCEN, bit 4 of XPERCON, and XPEN, bit3 of SYSCON.

1.1.4Pin 84

This pin was named Vpp/RPD on the ST10F168 and was the 12v input pin Flash programming. In the ST10F276, it is now only used as RPD.

Hardware impact

This pin is no longer designed to accept 12V inputs. Its ratings are the same as any other pin: - 0.5V to VDD + 0.5V.

Software impact

None.

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AN2169

Modified features

1.1.5Pin 56

For the ST10F168, this is VDD pin connected to 5Volts.

For the ST10F276, it is a 1.8V decoupling pin and named V18. A decoupling capacitor must be connected between this pin and the nearest Vss pin.

Hardware impact

The application board should be re-designed in order to introduce the decoupling capacitor.

Software impact

None

1.2Maximum CPU frequency

	ST10F168	ST10F276
Maximum CPU Frequency (MHz)	25	64

1.2.1Hardware impact

None.

1.2.2software impact

None.

1.3XRAM

The ST10F168 has only 6Kbytes of extension RAM while the ST10F276 has 66Kbytes.

The XRAM address range in the ST10F168 is 00’D000h-00’E7FFh and is enabled if XPEN (bit 2 of SYSCON register) is set.

The XRAM of the ST10F276 is divided into 2 ranges named XRAM1 of 2Kbytes and XRAM2 of 64 Kbytes:

●The XRAM1 address range is 00’E000h - 00’E7FFh if enabled (XPEN set -bit 2 of SYSCON register and XRAM1EN set -bit 2 of XPERCON register.

●The XRAM2 address range is 0F’0000h - 0F’FFFFh if enabled (XPEN set -bit 2 of SYSCON register and XRAM2EN set -bit 3 of XPERCON register).

1.3.1Hardware impact

None

1.3.2Software impact

The memory mapping of the application will be impacted by the difference in XRAM size and by the location of XRAM2 in the segment 15 while in the ST10F168, the whole XRAM is in page 3 of segment 0.

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Modified features

AN2169

Variables and PEC transfers

For architecture reasons, the PEC destination and source pointers must be in the segment 0. Therefore all RAM variables and arrays that will be PEC addressed must be located within either the DPRAM (00’F600h - 00’FDFFh) or the XRAM1 (00’E000h - 00’E7FFh).

About Toolchain memory model

A change in the Toolchain configuration will be needed to take into account the XRAM2 new location. In the ST10F168, all the XRAM is in page 3 and is then automatically addressed using DPP3 that points to the page 3 (in order to access the DPRAM and the SFR/ESFR). For the ST10F276, it will be necessary to dedicate a DPP to access some of the XRAM2.

Example for ST10F276 in case of Small Memory Model with Tasking toolchain:

The Small memory model allows to have a total code size up to 16M, up to 64K of fast accessible 'normal user data' in three different memory configurations and the possibility to access far/huge data, if more than 64K of data is needed.

The three memory configurations possible for this 64K of 'normal user data' are:

●Default

The four DPP registers are assumed to contain their system startup value (0-3), providing one linear data area of 64K in the first segment (00’0000h - 00’FFFFh).

●Addresses Linear

DPP3 contains page number 3, allowing access to SYSTEM (extended) SFR registers and bit addressable memory. DPP0 - DPP2 provide a linear data area of 48K anywhere in memory.

●Paged

DPP3 contains page number 3, allowing access to SYSTEM (extended) SFR registers and bit addressable memory. DPP0, DPP1 and DPP2 contain the page number of a data area of 16K anywhere in memory.

The Default configuration can no longer be used. The other configurations offer the following possibilities:

●with Addresses Linear configuration nearly all the XRAM2 block is covered with DPPs but then accesses to constants must be made via EXTP instructions

●Paged configuration allows to assign up to two DPPs to XRAM2 and one DPP for constants.

1.4Flash memory

Table 2.	Flash Memories key characteristics
		ST10F168	ST10F276
Flash Size		256K Bytes	832K Bytes
Flash		4 banks	4 banks, 17 blocks
Organization
Programming		12V	5 Volts
voltage

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AN2169			Modified features
		ST10F168	ST10F276
	Programming	STEAK TM	Write/Erase Controller
	method
	Program/Erase	10 Kcycles, 20 years data retention	100 Kcycles, 20 years data retention
	cycles

1.4.1Hardware impact

The 12 volts input on pin 84 is no longer needed.

1.4.2Software impact

The mapping of the application and the programming and erasing routines are impacted.

Figure 1. ST10F168 & ST10 F276 Flash Memories’ Mapping

		Segment		ST10F168 mapping			ST10F276 Mapping
		number
		14					0E’0000 - 0E’FFFF		Reserved for Flash registers
		13					0D’0000 - 0D’FFFF		B3F1: 64KB
		12					0C’0000 - 0C’FFFF		B3F0 : 64KB
		11					0B’0000 - 0B’FFFF		B2F2: 64KB
		10					0A’0000 - 0A’FFFF		B2F1 : 64KB
		9					09’0000 - 09’FFFF		B2F0 : 64KB
		8					08’0000 - 08’FFFF		B1F1 : 64KB
		7					07’0000 - 07’FFFF		B1F0 : 64KB
		6					06’0000 - 06’FFFF		B0F9 : 64KB
		5					05’0000 - 05’ FFFF		B0F8: 64KB
		4					04’0000 - 04’FFFF		B0F7: 64KB
				03’8000 - 04’FFFF	Bank 3 : 96 Kbytes
		3			Bank 2 : 96 Kbytes		03’0000 - 03’FFFF		B0F6: 64KB
				02’0000 - 03’7FFF
		2					02’0000 - 02’FFFF		B0F5: 64KB
				01’8000 - 01’FFFF	Bank 1 H : 32 Kbytes		01’8000 - 01’FFFF		B0F4: 32KB
		1
				01’4000 - 01’7FFF	Alternate Flash Area		01’0000 - 01’7FFF		Alternate Flash Area
				01’0000 - 01’3FFF	Alternate Flash Area
					External memory+IRAM
				00’8000 -00’FFFF			00’8000 -00’FFFF	External memory + IRAM
		0		00’4000 - 00’7FFF	Bank 1L : 16 Kbytes		00’4000 - 00’7FFF		B0F2:8KB & B0F3: 8KB
				00’0000 - 00’3FFF	Bank 0 : 16 Kbytes		00’2000 - 00’3FFF		B0F1:8KB
							00’0000 - 00’1FFF		B0F0:8KB

Note: On the ST10F168, Bank 0 and Bank 1L may be remapped from segment 0 to segment 1 by setting SYSCON.ROMS1.

On the ST10F276, sectors in segment 0 may be remapped to segment 1 by setting SYSCON.ROMS1.

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Modified features

AN2169

1.5A/D converter

The Analog Digital converter has been re-designed between the ST10F168 and ST10F276. The ST10F276 still provides an Analog / Digital Converter with 10-bit resolution and a sample & hold circuit on-chip.

1.5.1Hardware / Software impact: conversion timing control

The A/D converter is not fully compatible versus ST10F168 (timing and programming model). As for the ST10F168, the sample time ( for loading the capacitors) and the conversion time are programmable and can be adjusted to the external circuitry. The total conversion time is compatible with the formula used for ST10F168, while the meaning of the bit fields ADCTC and ADSTC is no longer compatible.

Table 3.	ST10F276 Conversion timing table
ADCTC	ADSTC	Sample	Comparison	Extra	Total Conversion
00	00	TCL * 120	TCL * 240	TCL * 28	TCL * 388
00	01	TCL * 140	TCL * 280	TCL * 16	TCL * 436
00	10	TCL * 200	TCL * 280	TCL * 52	TCL * 532
00	11	TCL * 400	TCL * 280	TCL * 44	TCL * 724
11	00	TCL * 240	TCL * 120	TCL * 52	TCL * 772
11	01	TCL * 280	TCL * 560	TCL * 28	TCL * 868
11	10	TCL * 400	TCL * 560	TCL * 100	TCL * 1060
11	11	TCL * 800	TCL * 560	TCL * 52	TCL * 1444
10	00	TCL * 480	TCL * 960	TCL * 100	TCL * 1540
10	01	TCL * 560	TCL * 1120	TCL * 52	TCL * 1732
10	10	TCL * 800	TCL * 1120	TCL * 196	TCL * 2116
10	11	TCL * 1600	TCL * 1120	TCL * 164	TCL * 2884

1.5.2Hardware impact

	Table 4.	ADC differences
				Limit values for		Limit values for ST10F276
	Parameter		Symbol	ST10F168				Unit
				min.	max.	min.	max.
	Analog Reference		VAREF	4.0	VDD + 0.1	4.5	VDD + 0.1	V
	voltage
	Reference supply
	current		IAREF	-		-	5000	µA
	running mode
				-		-	1
	power-down mode

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